DE3672605D1 - Datenverarbeitungssystem mit einer vorabrufschaltung. - Google Patents

Datenverarbeitungssystem mit einer vorabrufschaltung.

Info

Publication number
DE3672605D1
DE3672605D1 DE8686905533T DE3672605T DE3672605D1 DE 3672605 D1 DE3672605 D1 DE 3672605D1 DE 8686905533 T DE8686905533 T DE 8686905533T DE 3672605 T DE3672605 T DE 3672605T DE 3672605 D1 DE3672605 D1 DE 3672605D1
Authority
DE
Germany
Prior art keywords
data processing
processing system
preliminary switching
preliminary
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686905533T
Other languages
English (en)
Inventor
Kai Chan
Dang Nguyen
Revabhai Patel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Application granted granted Critical
Publication of DE3672605D1 publication Critical patent/DE3672605D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8686905533T 1985-08-29 1986-08-21 Datenverarbeitungssystem mit einer vorabrufschaltung. Expired - Lifetime DE3672605D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/770,459 US4722047A (en) 1985-08-29 1985-08-29 Prefetch circuit and associated method for operation with a virtual command emulator
PCT/US1986/001712 WO1987001482A1 (en) 1985-08-29 1986-08-21 Data processing system including a prefetch circuit

Publications (1)

Publication Number Publication Date
DE3672605D1 true DE3672605D1 (de) 1990-08-16

Family

ID=25088610

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686905533T Expired - Lifetime DE3672605D1 (de) 1985-08-29 1986-08-21 Datenverarbeitungssystem mit einer vorabrufschaltung.

Country Status (6)

Country Link
US (1) US4722047A (de)
EP (1) EP0235255B1 (de)
JP (1) JPH07117897B2 (de)
CA (1) CA1260618A (de)
DE (1) DE3672605D1 (de)
WO (1) WO1987001482A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6398737A (ja) * 1986-10-15 1988-04-30 Mitsubishi Electric Corp デ−タ処理装置
US4975869A (en) * 1987-08-06 1990-12-04 International Business Machines Corporation Fast emulator using slow processor
US5179703A (en) * 1987-11-17 1993-01-12 International Business Machines Corporation Dynamically adaptive environment for computer programs
US5287483A (en) * 1988-07-06 1994-02-15 Kabushiki Kaisha Toshiba Prefetched operand storing system for an information processor
JPH0752405B2 (ja) * 1988-12-14 1995-06-05 日本電気株式会社 シングルチップマイクロコンピュータ
US5150471A (en) * 1989-04-20 1992-09-22 Ncr Corporation Method and apparatus for offset register address accessing
US5278963A (en) * 1991-06-21 1994-01-11 International Business Machines Corporation Pretranslation of virtual addresses prior to page crossing
DE69325736T2 (de) * 1992-04-27 1999-11-18 Sony Corp Datenverarbeitungssystem, worin die Kompatibilität zwischen verschiedenen Modellen gewährleistet ist
US5450561A (en) * 1992-07-29 1995-09-12 Bull Hn Information Systems Inc. Cache miss prediction method and apparatus for use with a paged main memory in a data processing system
US5680632A (en) * 1992-12-24 1997-10-21 Motorola, Inc. Method for providing an extensible register in the first and second data processing systems
WO1994027214A1 (en) * 1993-05-07 1994-11-24 Apple Computer, Inc. Method for decoding sequences of guest instructions for a host computer
US5606685A (en) * 1993-12-29 1997-02-25 Unisys Corporation Computer workstation having demand-paged virtual memory and enhanced prefaulting
US5577227A (en) * 1994-08-04 1996-11-19 Finnell; James S. Method for decreasing penalty resulting from a cache miss in multi-level cache system
US5663924A (en) * 1995-12-14 1997-09-02 International Business Machines Corporation Boundary independent bit decode for a SDRAM
US6339752B1 (en) * 1998-12-15 2002-01-15 Bull Hn Information Systems Inc. Processor emulation instruction counter virtual memory address translation
US6401185B1 (en) * 1999-05-27 2002-06-04 Oracle Corp. Method and apparatus for accessing paged objects using a fast division technique
US6678817B1 (en) 2000-02-22 2004-01-13 Hewlett-Packard Development Company, L.P. Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine
US6701422B2 (en) * 2001-03-29 2004-03-02 Koninklijke Philips Electronics N.V. Memory control system with incrementer for generating speculative addresses
US8645609B2 (en) * 2010-12-06 2014-02-04 Brocade Communications Systems, Inc. Two-port memory implemented with single-port memory blocks
CN102541745B (zh) * 2010-12-31 2015-10-21 上海海尔集成电路有限公司 微控制器数据存储器的寻址方法和微控制器
US9329996B2 (en) * 2011-04-27 2016-05-03 Veris Industries, Llc Branch circuit monitor with paging register
US10671535B2 (en) * 2013-07-17 2020-06-02 Advanced Micro Devices, Inc. Stride prefetching across memory pages
US11809610B2 (en) * 2014-06-16 2023-11-07 Texas Instruments Incorporated Hardware protection of inline cryptographic processor

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3504349A (en) * 1967-09-27 1970-03-31 Ibm Address examination mechanism for use in a system operating with dynamic storage relocation
US3618041A (en) * 1968-10-31 1971-11-02 Hitachi Ltd Memory control system
DE2134816C3 (de) * 1971-07-13 1978-04-27 Ibm Deutschland Gmbh, 7000 Stuttgart Einrichtung zur Adressenübersetzung
US4218743A (en) * 1978-07-17 1980-08-19 International Business Machines Corporation Address translation apparatus
US4298927A (en) * 1978-10-23 1981-11-03 International Business Machines Corporation Computer instruction prefetch circuit
CA1134952A (en) * 1979-04-24 1982-11-02 Thomas E. Kloos Means and method within a digital processing system for prefetching both operation codes and operands
US4371924A (en) * 1979-11-09 1983-02-01 Rockwell International Corp. Computer system apparatus for prefetching data requested by a peripheral device from memory
JPS5687282A (en) * 1979-12-14 1981-07-15 Nec Corp Data processor
JPS6032220B2 (ja) * 1980-07-07 1985-07-26 日本電気株式会社 情報処理装置
US4422144A (en) * 1981-06-01 1983-12-20 International Business Machines Corp. Microinstruction substitution mechanism in a control store
US4432053A (en) * 1981-06-29 1984-02-14 Burroughs Corporation Address generating apparatus and method
US4613935A (en) 1983-02-02 1986-09-23 Couleur John F Method and apparatus for pipe line processing with a single arithmetic logic unit

Also Published As

Publication number Publication date
CA1260618A (en) 1989-09-26
JPH07117897B2 (ja) 1995-12-18
US4722047A (en) 1988-01-26
EP0235255A1 (de) 1987-09-09
WO1987001482A1 (en) 1987-03-12
EP0235255B1 (de) 1990-07-11
JPS63500688A (ja) 1988-03-10

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: KAHLER, K., DIPL.-ING., 8948 MINDELHEIM KAECK, J., DIPL.-ING. DIPL.-WIRTSCH.-ING., PAT.-ANWAELTE, 8910 LANDSBERG

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL INC., DAYTON, OHIO, US

8328 Change in the person/name/address of the agent

Free format text: KAHLER, K., DIPL.-ING., 8948 MINDELHEIM KAECK, J., DIPL.-ING. DIPL.-WIRTSCH.-ING., 8910 LANDSBERG FIENER, J., PAT.-ANWAELTE, 8948 MINDELHEIM

8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8339 Ceased/non-payment of the annual fee