DE3650578D1 - Informationsverarbeitungssystem mit einer Steuerschaltung zum Abwarten einer Registererneuerung und einem Aufnahmemittel des zu erneuernden Registers - Google Patents

Informationsverarbeitungssystem mit einer Steuerschaltung zum Abwarten einer Registererneuerung und einem Aufnahmemittel des zu erneuernden Registers

Info

Publication number
DE3650578D1
DE3650578D1 DE3650578T DE3650578T DE3650578D1 DE 3650578 D1 DE3650578 D1 DE 3650578D1 DE 3650578 T DE3650578 T DE 3650578T DE 3650578 T DE3650578 T DE 3650578T DE 3650578 D1 DE3650578 D1 DE 3650578D1
Authority
DE
Germany
Prior art keywords
register
renewed
waiting
control circuit
information processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3650578T
Other languages
English (en)
Other versions
DE3650578T2 (de
Inventor
Haruo Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3650578D1 publication Critical patent/DE3650578D1/de
Publication of DE3650578T2 publication Critical patent/DE3650578T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE3650578T 1985-06-17 1986-06-16 Informationsverarbeitungssystem mit einer Steuerschaltung zum Abwarten einer Registererneuerung und einem Aufnahmemittel des zu erneuernden Registers Expired - Fee Related DE3650578T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP13115685 1985-06-17
JP13115485 1985-06-17

Publications (2)

Publication Number Publication Date
DE3650578D1 true DE3650578D1 (de) 1996-11-28
DE3650578T2 DE3650578T2 (de) 1997-03-06

Family

ID=26466074

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3650578T Expired - Fee Related DE3650578T2 (de) 1985-06-17 1986-06-16 Informationsverarbeitungssystem mit einer Steuerschaltung zum Abwarten einer Registererneuerung und einem Aufnahmemittel des zu erneuernden Registers

Country Status (3)

Country Link
US (1) US4777592A (de)
EP (1) EP0205193B1 (de)
DE (1) DE3650578T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4852040A (en) * 1987-03-04 1989-07-25 Nec Corporation Vector calculation circuit capable of rapidly carrying out vector calculation of three input vectors
DE3852432T2 (de) * 1987-07-01 1995-07-13 Ibm Befehlssteuerungsvorrichtung für ein Computersystem.
JPH0769821B2 (ja) * 1988-03-04 1995-07-31 日本電気株式会社 情報処理装置におけるバイパスライン制御方式
US4935849A (en) * 1988-05-16 1990-06-19 Stardent Computer, Inc. Chaining and hazard apparatus and method
US4969117A (en) * 1988-05-16 1990-11-06 Ardent Computer Corporation Chaining and hazard apparatus and method
JP2674809B2 (ja) * 1988-11-07 1997-11-12 日本電気株式会社 情報処理装置
US5053987A (en) * 1989-11-02 1991-10-01 Zoran Corporation Arithmetic unit in a vector signal processor using pipelined computational blocks
JP2845578B2 (ja) * 1990-06-19 1999-01-13 甲府日本電気 株式会社 命令制御方式
EP0482706B1 (de) * 1990-10-24 1999-01-07 Koninklijke Philips Electronics N.V. Verfahren für Datenvorgriff in Cache-Speicher und Rechner zu dessen Durchführung
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
KR100248903B1 (ko) * 1992-09-29 2000-03-15 야스카와 히데아키 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템
US5463746A (en) * 1992-10-30 1995-10-31 International Business Machines Corp. Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes
CA2087678C (en) * 1993-01-20 1998-09-01 Makoto Omata Arrangement of controlling issue timing of a instruction in a vector processor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128880A (en) * 1976-06-30 1978-12-05 Cray Research, Inc. Computer vector register processing
FR2420168B1 (fr) * 1978-03-16 1986-09-26 Ibm Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
JPS57155666A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Instruction controlling system of vector processor
JPS58114274A (ja) * 1981-12-28 1983-07-07 Hitachi Ltd デ−タ処理装置
JPS5932045A (ja) * 1982-08-16 1984-02-21 Hitachi Ltd 情報処理装置
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
JPS60120439A (ja) * 1983-12-05 1985-06-27 Nec Corp 演算処理装置
JPS60156151A (ja) * 1983-12-23 1985-08-16 Nec Corp メモリアクセス制御装置
US4683547A (en) * 1984-10-25 1987-07-28 International Business Machines Corporation Special accumulate instruction for multiple floating point arithmetic units which use a putaway bus to enhance performance

Also Published As

Publication number Publication date
EP0205193B1 (de) 1996-10-23
EP0205193A3 (de) 1989-09-13
US4777592A (en) 1988-10-11
DE3650578T2 (de) 1997-03-06
EP0205193A2 (de) 1986-12-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee