DE3622514C2 - - Google Patents

Description

The invention relates to a data storage system according to the preamble of claim 1.

With modern private telephone systems at least a microprocessor is used to build the inner and to control external switching connections, what for stored operating system program is used. in the Contrary to most computers where system programs easily by using floppy disks are interchangeable, the control circuits of Telephone systems in relatively inaccessible places Installed. The control circuits are often located in remote premises, such as in basement storage rooms, where they are acoustic and are visually isolated from users. After building The system program is entered into the system to the intended use of the telephone system is coordinated. For example, there is for hotels and specially tailored applications for offices programs. The control circuits need a big one Have level of reliability.

System programs are usually used to store them erasable, programmable memories, so-called EPROMS, who are able to run an operating system program 14 kBytes. These stores point high reliability, but have the disadvantage to be very expensive.  

Because modern private telephone systems are always user-friendly Licher, it is necessary to have a high memory capacity to provide a large number of Data entered by users can be saved is. Often it is also desirable to have a system pro grams through a new improved system program to replace. To save the data entered by the users Data serves multiple RAM. In the same way several expensive EPROMS can be provided. For storage A more extensive system program is a memory capacity of about 0.5 megabytes required. By the variety of EPROM and RAM memories such control circuits for private telephone systems very expensive.

In the magazine "electronics industry" No. 10, 1979, Pages 15 to 16 and 19 to 20, is a ROM controlled Floppy disk system with DMA interface described, at a microprocessor via a control and a Data bus with a floppy disk control circuit, one ROM and a RAM memory is connected. The ROM The control program saves memory the control circuit via the microprocessor. The control circuit in turn controls the input and output of the Data on the floppy disk device. In this way the Stress on the microprocessor with control tasks reduced. The floppy disk drive is permanent in operation. Because of that when recording and reading of data disturbing dust particles on the Disk surface is making a backup recommended.

The operating manual CBM 8050, Commodore 16, 1981, Page 15, is a floppy disk device for a computer removable, whose floppy disk the system program for saves the computer when the computer is started up is transferred to the computer. During operation the computer finds a data exchange between the Flopy disk device and the computer instead. The floppy Disk device is shut down, even if the computer is stopped.

There is the task, the data storage mentioned above system to improve so that with undiminished memory capacity reduces the number of semiconductor memories can be.

This task is solved with the characteristic ones Features of claim 1. Advantageous refinements can be found in the subclaims.

As mentioned above, it is known in microcomputers for program storage To use floppy disks. Because on the magnetic disks very often data is written and retrieved, these disks and their drives have a relative low reliability. Form in such Magnetic discs oxides or dust is deposited on them particles, then there is a risk that whole blocks of data are deleted or no longer accessible are. It is known that the reliability of Floppy disks with the frequency of reading and reading  operations is decreasing. Since such microcomputers in immediate stand close to the user, the user has easy access to the floppy disk device and can be a defective magnetic disk easily against a new one change.

The control circuits of private telephone systems however, are not easily accessible. Because of the lack The casualness of floppy disk devices is out of the question here the use of such devices. According to of the invention, however, a floppy Disk device can be used because this is relatively rare is put into operation. This device is practical only turned on when the microprocessor the startrou tine executes, whereby the system pro stored in the device grams in the dynamic random access memory is transmitted. Data entered by hand stored in a static memory. Is this Memory full, then the device is also switched on and the data stored in the static memory are stored in the device for storage on the magnetic disc entered. After completion of this data transfer the device is switched off again.

As a result of the relatively rare start-up of the device the wear of the magnetic disc is relatively low, which is consequently more reliable than in the long run operation. This also leads to a higher one Lifetime of the magnetic disk drive. Furthermore is the power consumption and thus the heat ent winding relatively low.

An embodiment is described below with reference to Drawings explained in more detail. It shows:  

Fig. 1 is a schematic diagram of the data storage system;

Fig. 2 is a block diagram of the engine control and the motor power supply and

Fig. 3 is a circuit diagram of an EPROM memory for storing the boot routine.

As shown in FIG. 1, an EPROM 1 is connected to a microprocessor 3 via data, address and control buses 2 , 5 and 6 .

The EPROM 1 contains a program for executing a start routine when the microprocessor 3 is turned on or reset. The EPROM 1 is switched on by a signal from the control bus 6 , which is generated by the microprocessor 3 .

A direct access memory control circuit DMAC 10 is connected to the microprocessor 3 via the data bus 2 , the address bus 5 and the control bus 6 .

A control circuit FDC 13 for the floppy disk is connected on the one hand via the data bus 2 and the control bus 6 to the microprocessor 3 , and on the other hand to the drive 17 of the floppy disk. The floppy disk contains the operating system program.

In operation, the microprocessor 3 executes a start routine which is stored in the EPROM 1 . This configures FDC 13 to read data from disk drive 17 by inputting certain data signals to the inner registers of FDC 13 related to bit transmission speed, parity bit generation, etc. The microprocessor then configures DMAC 10 for data transfer from the FDC 13 to a dynamic memory DRAM 18 which is connected to the microprocessor 3 via the data, address and control buses 2 , 5 and 6 . DMAC 10 is configured by loading the inner data registers with the first and last occupied address of DRAM 18 , thereby defining the address frame in which the operating system program is stored.

The microprocessor 3 generates signals which are fed to the data bus 2 and from there to the control circuit 19 for executing further commands of the start routine stored in the EPROM 1 . These signals are stored in the control circuit 19 , the switch-on signals of the power supply circuit 32 and the drive 17 supplies. The Stromver supply circuit 32 consists of a transistor circuit that supplies a supply voltage of 12 volts and 5 volts to the voltage input VIN of the disk drive 17 . The control circuit 19 generates a switch-on signal which is fed to the input ON of the disk drive 17 , whereby the drive motor is switched on.

FDC 13 then performs a series of acknowledgment or handshaking operations through the input and output control buses ICTRL OCTRL and by using the disk drive 17, take a reading from the data floppy disk einzu. FDC 13 generates a DMA request signal in which the output DRQ assumes the value H. This DMA request signal is fed to the REQ input of DMAC 10 . DMAC 10 then generates a DMA confirmation signal, which is present at the ACK output and is fed to the ACK input by FDC 13 . Various arbitrary bus state signals are generated by the DMAC 10 and supplied to the microprocessor 3 via the control bus 6 , which indicates to the microprocessor that the control circuit DMAC has taken control of the address and data buses 5 and 2 .

FDC 13 then begins reading the operations system program which is in the form of digital series signals. These digital signals are fed to the RD input. The received signals are converted from the serial to a parallel format in the FDC 13 and fed to the data bus 2 via the DATA connection. The DMAC 10 reads these parallel digital signals from its data bus 2 via its DATA connection. These signals are then returned from the DMAC 10 to the data bus for transmission and storage in successive memory locations of the DRAM 18 , defined by certain address signals that occur in the bus 5 and are generated by the DMAC 10 . The data transfer of the operating system program from the floppy disk to the DRAM 18 continues until the entire program is stored in the DRAM 18 , in which case the last memory address of the DRAM 18 is loaded.

The DMAC 10 generates a signal at its DONE output which is fed to the counting input TC of FDC 13 , thereby indicating to the disk control circuit that the data transfer has been carried out.

The DMAC 10 then generates an interrupt signal I 1 at its output INT which is fed to a priority interruption encoder 11 . The encoder 11 determines from a number of interrupt signals, ie the signals I 1 and I 2 , which has the highest priority for interrupting the microprocessor 3 and generates an interrupt signal as a function thereof.

The microprocessor 3 generates further data signals as a function of the receipt of an interrupt signal, these data signals being fed to the control circuit 19 via the bus 2 . As a result, the control circuit 19 generates switch-off signals, whereby the power supply circuit 32 and the disk drive motor are switched off, as will be explained in detail with reference to FIG. 2.

Instructions of the operating system program, which are stored in the DRAM 18 , are then executed in a known manner by the microprocessor 3 .

The data entered by a user is temporarily stored in the static memory and periodically transferred to the floppy disk for permanent storage. Data entered by the user in the terminal 29 enter the data bus 2 via a UART 27 .

If the user wishes to enter data, these are entered into the terminal 29 , which then generates a request signal and feeds it to the UART 27 via a control bus 30 . In a known manner, an acknowledgment signal is transmitted from the UART to the data terminal via the control bus 30 . The data entered by the user is fed from the terminal 29 to the UART 27 via the input R × D. Then UART 27 generates an interrupt signal I 2 , which occurs at the output IRQ and which is fed to the encoder 11 , which then transmits an interrupt signal to the microprocessor 3 . The microprocessor 3 generates control signals which are fed to the control bus 6 for controlling the data transfer from the UART 27 to a CMOS RAM 25 , the data transfer being carried out via the data bus 2 after the interruption signal has been received. UART 27 converts the received data from a serial format into a parallel format and places them in parallel on the data bus 2 for storage in specific memory locations of the CMOS RAM 25 as soon as the aforementioned control signal has been received by the microprocessor 3 .

In the event that the user enters further data in the terminal 29 , the microprocessor is interrupted again and the data are entered via the data bus 2 in additional memory locations of the CMOS RAM 25 for storage. In this way, successive memory locations of the CMOS RAM 25 are occupied with data entered by the user in the terminal 29 .

In the event that each memory location of the CMOS RAM 25 is occupied, ie if the CMOS RAM 25 is full, the microprocessor 3 configures the DMAC 10 to carry out a DMA data transfer from the CMOS RAM 25 to the FDC 13 . FDC 13 then generates a DMA command at its DRQ output, whereupon DMAC 10 generates a confirmation signal. DMAC 10 then takes over control via address bus 5 and data bus 7 and performs a DMA data transfer from CMOS RAM 25 to FDC 13 . The disk drive 17 and also the power supply circuit 32 are switched on as soon as, as described above, the control circuit 19 is supplied with a data signal from the microprocessor 3 . The data from the FDC 13 are fed to the disk drive 17 for storage in the floppy disk in a known manner.

As soon as the DMA data transfer is complete, a signal appears at the DONE output of DMAC 10 which is fed to the FDC 13, indicating that the data transfer has ended. At the output INT of DMAC 10 , the interrupt signal I 1 occurs, which signals the microprocessor 3 that the data transfer has ended.

Details of the various control signals, such as acknowledgment signals, which are exchanged in the control bus 6 between the microprocessor 3 and the DMAC 10 , are conventional and are therefore not described.

The CMOS RAM 25 has a power supply input Vcc, the voltage on the supply - V is connected and to a capacitor 33, which in the event of a power failure takes over the power supply. In the event of a power failure, the data stored in the CMOS RAM 25 are not lost. In the case of a prototype, the capacitance of the capacitor 33 was approximately 3 farads, this capacitor being connected between -5 volts and ground.

In Fig. 2, the control circuit 19 for the disk drive is shown. This has two outputs Q 6 and Q 7 , each of which is connected to a buffer 40 , 41 . The control circuit 19 preferably consists of an addressable memory. The outputs of the buffers 40 and 41 are connected to resistors 42 and 43 which are connected to a positive voltage. The output of the buffer 40 is still a current limiter resistor was 44 A connected to the base of a PNP transistor 44 . The output of the buffer 41 is at the gate connection of a VMOS FET transistor 45 . The voltage at which resistors 42 and 43 are present is +12 volts.

The emitter of the PNP transistor 44 is connected to this voltage, while the collector is connected to the output terminal 47 , which leads to the disk drive 17 .

The VMOS FET transistor 45 is an n-channel FET transistor, the drain electrode of which is at +5 volts. The substrate of the VMOS FET transistor 45 is connected to the source electrode, which in turn is connected to the output terminal 48 for supplying an operating voltage of +5 volts to the disk drive 17 .

Another output of the control circuit 19 is connected to the inverting buffer 46 for switching on the disk drive 17 , as described above.

Data signals for a data transfer to or from the disk drive 17 are received by the data bus 2 and input into the control circuit 19 as a function of the reception of a signal via the control bus 6 . By the input data signals into the controller TIC 19, the outputs take the control circuit 19, the potential at H. These signals are fed to buffers 40 and 41 and inverting buffer 46 . The signal fed to the inverting buffer 46 is inverted by the latter and fed to the switch-on input of the disk drive 17 . The signals applied to buffers 40 and 41 cause transistors 44 and 45 to become conductive, thereby applying a voltage of +12 volts to terminal 47 via the emitter-collector path of PNP transistor 44 and via the VMOS FET transistor 45 has a voltage of +5 volts at terminal 48 .

The disk drive 17 is thus switched on and supplied with voltage via the connections 47 and 48 .

According to a preferred embodiment, the data bus 2 is a 16 bit data bus. As mentioned at the beginning, it is desirable to reduce the number of expensive EPROMS in the data storage system. According to the preferred embodiment and as shown in Fig. 3, a single 8 bit EPROM chip 1 A is used, which is connected to the 16 bit data bus via a latch circuit 1 B of 8 bits, which results in a circuit configuration to which normally two EPROM chips of 8 bits each are required.

Commands the start routine of 16 bits are stored in 8-bit EPROM chip 1A so that the first bytes are a command to a particular memory location and the last byte in the next sequential memory location is stored. In this way, 128 commands of 16 bits each can be stored in 256 memory locations of a single 8-bit 1 A EPROM chip.

In operation, the first byte of a command from the outputs D 0 to D 7 of the EPROM chip 1 A is fed to the inputs D 1 to D 8 of the latch circuit 1 B as a function of received address and control signals from the address and control buses 5 and 6 . The first and the last byte of the command are then output simultaneously from the outputs D 0 to D 7 of the EPROM chip 1 A and the outputs Q 1 to Q 8 of the latch circuit 1 B and occur in the lines D 0 to D 15 of the Data bus 2 on depending on the reception of further signals in the address and control buses 5 and 6 . In this way, a command of 16 bits is generated by a single 8 bit EPROM chip and fed to the data bus 2 .

In a prototype, the microprocessor consisted of the Motorola model 68,000, the FDC 13 was the model 765 from NEC Electronics USA Inc., the DMA control circuit 10 was the model 68 450 from Motorola and the disk drive 17 was a Mit subishi Model.

The system described above is a reliable, cheap data storage system for storing a Operating system program and data from the User can be entered. The disk drive closes a floppy disk on which the operating system is saved, which is much cheaper than storage in several EPROMS. For temporary Storage of data entered by the user periodically transferred to the floppy disk a relatively low memory capacity in the CMOS RAM required. The disk drive becomes very rare switched on, i.e. only while switching on of the system while resetting the system and when entering user-entered Data. Because the floppy disk storage is relatively cheap is, it is always possible to find new and complicated ones To use versions of the operating system program in which only the floppy disk is exchanged.  

Instead of a floppy disk or a floppy disk, it is also possible to use a different hardware memory. This may require minor changes to the control circuit 13 and to the power supply circuit 32 . It is possible to use several disk drives to store additional programs or data entered by the user.

The floppy disk drive can be encapsulated so that it is protected from dust. Instead of the transistor circuit 32 shown in FIG. 2, it is also possible to use relays or other switches.

Instead of the DMAC 10 , other circuits can also be used to carry out the data transfer between the floppy disk control circuit 13 and the CMOS RAM 25 or the DRAM 18 . As an alternative to this, the data transfer can also be carried out directly by the microprocessor 3 , whereby the microprocessor, however, requires additional time.

The circuit is not only limited to telephone systems but on all computer systems where one data access is not common.

Claims (6)

1. Data storage system with a dynamic random access memory, a ROM memory, a control signal-generating microprocessor, a floppy disk control circuit for controlling the data transmission from and to a floppy disk device, the memory, the microprocessor and the floppy disk Control circuit are connected to one another via data and control buses and a program stored in the ROM memory effects the control commands of the microprocessor for controlling the floppy disk control circuit, in use for controlling a telephone system, characterized in that
that a control circuit ( 10 ) is provided for the direct access memory ( 18 ) which, in addition to the data and control buses ( 2, 6 ), is connected to the microprocessor ( 3 ) and the direct access memory ( 18 ) via an address bus ( 5 ),
a drive control circuit ( 19 ) for switching the disk drive of the floppy disk device ( 17 ) on and off is connected to the control bus ( 6 ),
the disk of the floppy disk device ( 17 ) the system program of the telephone system and the ROM memory ( 1 ) store a start routine,
when the start routine is executed by a first control signal from the microprocessor ( 3 ), the drive control circuit ( 19 ) switches on the disk drive,
by means of a second control signal, the system program data read from the storage disk are fed via the data bus ( 2 ) to the control circuit ( 10 ), which it supplies with the associated address signals via the data and address buses ( 2, 5 ) for storage to the direct access memory ( 18 ) and which generates a first interrupt signal at the end of this data transmission, which is fed to the microprocessor ( 3 ), which generates a switch-off signal for the drive control circuit ( 19 ) for switching off the disk drive and which is now controlled by the system program stored in the random access memory ( 18 ). 2. Data storage system according to claim 1, characterized in that between the data bus ( 2 ) and the floppy disk device ( 17 ) a floppy disk control circuit ( 13 ) is connected, which converts the program data from the series format into a parallel format. 3. Data storage system according to claim 1 or 2, characterized in that a data terminal ( 29 ) for manual input of data and a static memory ( 25 ) is provided for storing this data, when entering data in the data terminal ( 29 ), a second interrupt signal Microprocessor ( 3 ) is supplied, which then generates a third control signal which effects the data transfer from the data terminal ( 29 ) to the static memory ( 25 ). 4. Data storage system according to claim 3, characterized in that between the data terminal ( 29 ) and the data bus ( 2 ) is connected to the control bus ( 6 ) connected circuit ( 27 ) which generates the second interrupt signal and feeds the control bus ( 6 ) and converts the data from the serial format into a parallel format. 5. Data storage system according to claim 3 or 4, characterized in that when the static memory ( 25 ) is full, the data stored in this memory ( 25 ) are fed to the floppy disk device ( 17 ), the first control signal for switching on the floppy disk. Disk device ( 17 ) and a further control signal are generated by the microprocessor ( 3 ), the latter, controlled by the control circuit ( 10 ), causing the data transfer from the static memory ( 25 ) to the floppy disk device ( 17 ), according to the latter Termination the control circuit ( 10 ) generates the first interrupt signal. 6. Data storage system according to one of claims 1 to 5, characterized in that the data bus ( 2 ) has a first bit capacity and the ROM memory ( 1 ) consists of an EPROM chip ( 1 A) and a latch memory ( 1 B) , the outputs ( D 0 to D 7 ) of the EPROM chip ( 1 A) with the first half of the data bus lines ( D 0 to D 7 ) and the inputs ( D 1 to D 8 ) of the latch memory ( 1 B) and its outputs ( Q 1 to Q 8 ) are connected to the second half of the data bus lines ( D 8 to D 15 ).