DE19818853B4 - Integrated logic circuitry - Google Patents

Abstract

The logic circuit has a processor (1) or controller arrangement with internal processor units such as an arithmetic-logic unit (4), command counters, address and data buffers, etc. and at least one internal register (2) or a memory element (3) with a register function. At least the internal register is in the form of a nonvolatile memory. Internal buffer areas can be implemented as nonvolatile buffer areas

Description

The invention relates to an integrated Logic circuit arrangement from a processor or controller arrangement with internal processor units, such as arithmetic logic unit, command counter, buffer, and with at least one internal register or storage element with register function. The invention also relates to an integrated Logic circuit which has a sequential mode of operation and consists at least partially of flip-flops.

The basic use of non-volatile memories in logic circuit arrangements is from the US 4,003,030 known. A discrete logic circuit is described therein, which is provided with a non-volatile memory array for the purpose of state storage. However, this circuit arrangement is not intended to be used to implement an integrated logic circuit.

Logic circuits are known which are designed as processors, which via volatile internal registers and address, Have data and other buffers.

Most of these processors are too provided with external and / or internal program and data memories. These memories consist of a memory matrix, which is a number of individual memory cells as well as those for selection and memory access contains the necessary logic (e.g. decoder, I / O stages and buffer).

The registers mentioned include, for example Command register, command counter, Data register, condition register, intermediate and auxiliary register, Interrupt register, pointer and / or stack register. To the buffers belong for example address buffers, Data buffer, buffer for Control and I / O signals, interrupt signals and additional Buffer elements, for example for state storage in internal function blocks, such as arithmetic logic unit, address unit, arithmetic unit, Control unit, interrupt control logic, memory access control, instruction decoder and sequence control.

The external and internal program and data storage are used as both volatile and non-volatile storage realized. fugitive Memories such as SRAMs and DRAMs have the advantage a high access speed, which makes the application as fast Read / write memory supported becomes. The disadvantage, however, is that this Memory will lose its content in the event of voltage interruptions if not additional Measures - e.g. a Battery backup - provided become.

One from the DE 34 24 765 C2 and the US 5,892,705 Known possibility for avoiding a program or data loss due to a voltage interruption consists in the realization of non-volatile memory areas for processors by using a ROM, (E) EPROM or a flash memory. These memories retain their content even without voltage buffering in the event of an interruption in the operating voltage, but cannot be written to, or only to a limited extent, repeatedly. Furthermore, they have relatively long write times compared to SRAMs and DRAMs. For these reasons, the non-volatile memory types mentioned are mainly used as memory for programs and parameters which do not have to be changed or only relatively rarely.

A combination of the advantages of one volatile Memory (high access speed) and a non-volatile Memory (data retention even in the event of a voltage interruption) are offered, for example, by nvSRAMs, Ferro RAMs and magnetoresistive RAMs.

Memory called nvSRAM (non volatile SRAM), as in the article of the DE magazine electronics 15/1996, p. 14, consist of an SRAM part and a EEPROM part, the EEPROM as a non-volatile Shadow storage for serves the SRAM so that the Data content is retained even when the power is interrupted. On nvSRAM is easy to change, a large number from write cycles and a high access speed. The nvSRAM enables the implementation of non-volatile, faster and easily changeable Read / write memory.

nvSRAMs are becoming special today used as external data storage. Basically, it is also a realization as an integrated memory area for data and programs in processors or controllers possible.

While the mentioned external and / or internal storage of storage of programs and data areas serve the internal register and buffers mainly for the temporary storage of data and program code, address and I / O information as well as intermediate results of operations of the processor, that of direct program execution and control of the How the processor and its peripherals work.

These internal registers and buffers be with a very large Number of read / write cycles claimed. Furthermore, it will be a high access speed required, as this is a direct Influence on the efficiency and operating speed of the processor. For this reason the registers and buffers are currently basically volatile memory elements with high working speed, for example as from flip-flops assembled units, executed.

The disadvantage here is that this internal registers and buffers in the event of voltage interruptions Lose content so the relevant information when the processor is restarted no longer available stand. This regularly results in the need for one Restart of the system with a reinitialization of the register contents.

To avoid this disadvantage, additional measures, such as a bat series buffering of the processor can be provided. However, the lifespan of the backup battery is a problem here. Additional measures, such as the implementation of power management, are required to solve the same. Various power saving methods, such as switching off partial components or reducing the clock rate, are used. However, these means increase the manufacturing expenditure of processor arrangements.

Processor arrangements are higher performance Moreover by a higher one Power consumption marked, so there are restrictions result in the long-term applicability of battery backup. This then involves further measures An additional Show effort required for data backup.

Another option for avoiding data loss in the event of an interruption is according to the JP 10-69336 and the associated JP abstract JP 10069336 A in swapping the current contents of internal registers, memories and buffers into a non-volatile memory. For example, EEPROMs or flash memory can be used for this.

This shows a similar effect Notebooks known suspend-to-disk processes, by which it is ensured that a secured before switching off Working condition, including the activated programs, can be restored.

After a power-up reset suitable start routines called, the correct continuation of the Support the work of the processor. The Access control to used memory areas can be controlled by software routines take place so that in Editing data segments or open files with undefined Content to be recognized.

An uninterrupted sequel the work of the processor or the microcontroller after outsourcing the internal register or buffer contents is not in the mentioned cases possible, basically after power-up carried out a start routine must become, which is a reload the register or memory contents saved during power-down. Besides, is securing the current work status in the event of unforeseen Voltage interruptions are problematic because the complete data set including the temporary register, address and data buffers as well as other state variables of the processor only guaranteed to a limited extent can be. This applies in particular to the suspend-to-disk process.

It is therefore an object of the invention to specify an integrated logic circuit while maintaining quick access to storage elements after a power failure a restart in the state before the power failure was given.

The object of the invention is integrated logic circuits from a processor or controller arrangement solved with internal processor units in that at least the internal register as nonvolatile Register is designed such that it consists of a static Storage element consists of a non-volatile shadow storage element is directly assigned and that a Voltage monitoring circuit with a control output that triggers a signal when the voltage falls below a target voltage is provided, the - the nonvolatile Memory acquisition controlling - with the register and buffer elements is connected.

Through the application according to the invention a shadow arrangement for internal registers and buffers from processors become the disadvantages of the state of the art, since maintaining the processor's fast operation after a power failure a restart of the processor in the Condition that existed before the power failure is enabled.

It is expedient that inner Buffer area also designed as non-volatile buffer areas of the non-volatile Register are executed, so that one Extensive interruptibility also achieved within instruction cycles can be.

With the described registers and Can buffer Processors are implemented, their internal data content in the event of a power failure remain so that the Processor practically uninterrupted when restarted can continue.

It may be appropriate for the control output for additional external connection trained is.

To adjust the working speeds to each other it is useful that the access time the non-volatile Registers and buffers at least in the order of magnitude equal to the access time of the processor units.

This is a particularly favorable embodiment characterized that too the internal and / or external program and data memories as non-volatile memories be realized so that a consistent System design with regard to the non-volatile mode of operation of the processor given is. This can protect the entire processor system from data loss be secured and practically a start / stop operation can be carried out in the event of voltage interruptions.

Finally, it is advisable that a STORE and RECALL functions in the register, in the internal and possibly in external Store synchronizing control line is provided.

Another advantageous embodiment of the invention is that non-volatile registers memory and / or buffer elements at least partially as ferro-RAMs or magnetoresistive RAMs are trained.

The task according to the invention is at integrated logic circuits that operate sequentially have and which at least partially consist of flip-flops, too solved by that at least a non-volatile flip-flop is trained.

The sequential way of working is for example for Control circuits, registers and counters typical. With the equipment through non-volatile flip-flops it is possible, Status information, for example, even in the event of voltage interruptions save.

The invention is based on the following of an embodiment are explained in more detail. In the associated Shows drawings

1 1 shows a schematic diagram of a processor according to the invention with non-volatile registers and memories with register function,

2 a section of a program to be processed,

3 a schematic representation of the behavior after a power failure based on the program section and

4 a flowchart to clarify the programmatic step into the process after a power failure.

As in 1 shown is a processor 1 with an internal register 2, an internal buffer 3 with register functions, an arithmetic logic unit 4 and other processor components 4a Mistake. The internal register 2 and the internal buffer 3 is implemented as a shadow configuration with an EEPROM cell. There is also an internal system bus 5 provided that serves to connect the modules with each other. There is also an internal memory 6 integrated, which is part of the program and data storage not shown.

Via an external system bus 7 additional non-volatile external data storage (nvSRAM) 8th and external program memory (flash) 9 to the processor 1 coupled. Via an internal control line 10 the STORE / RECALL processes are synchronized in the processor 1 and the external data storage 8th so that the necessary data consistency can be maintained.

The system supply voltage is constantly monitored by a voltage monitoring circuit 11 checked. If the supply voltage drops below a certain level, a STORE process is triggered. For the STORE process, the current computing and transmission processes in the system are stopped and then a backup of the contents of the register 2 and the buffer 3 caused in the EEPROM of the shadow arrangement. The forwarding of the STORE signal to the external data storage 8th takes place via an external control line 12 , The data backup in the EEPROM of the register 2 and the buffer 3 required energy is provided by an external capacitor 13 provided via a special V _CAP pin 14 is connected.

There is also a system clock 15 provided that also with a capacitor 16 can be buffered. The current time stamp is saved with a checksum so that after a power-up it can be recognized whether the system clock 15 was continuously active during a voltage interruption.

After a power-up, the EEPROM content becomes the shadow arrangement of the register 2 and the buffer 3 reloaded into the volatile part of the shadow arrangement, which is referred to as RECALL, and the content of the system clock stored during power-down 15 read. Instead of the power-up reset in conventional processor systems, a signal for a power-up interrupt routine can optionally be activated. The interrupted processes are then continued without restarting the system.

The interrupt routine can be started as soon as possible. Depending on whether time conditions have to be taken into account in the event of voltage interruptions (eg when used in process control), the difference between the system time saved in a memory cell is evaluated 17 is stored and the current time in a memory cell 18 is saved. If a predetermined time interval is determined, a system restart or other necessary measures, for example checking parameters or reinitializing peripheral modules, can be carried out. If no violation of time conditions and parameters was found, the interrupt routine is ended without further activities and the current program flow is continued. If such an interrupt routine is dispensed with, the program itself cannot detect an interruption in its work due to a power down.

In 2 is the part of a program to be processed. For example, when editing the program line 656 a power failure that causes a power down in the processor 1 forces. With this power-down, the current values are stored in a non-volatile manner in the manner shown and are available again for a power-up that occurs after the end of the voltage interruption. As in 3 can be seen immediately after the voltage interruption in line 656 to be continued.

In 4 it is shown that an interruption in the operating voltage has the effect that the normal sequence is immediately entered. The dashed line here represents the sequence after the voltage interruption.

A possible area of application for such processors 1 is the control technology in which microprocessors or microcontrollers are often used are set, which must save important process data even in the event of voltage interruptions and ensure a defined restart. With the use of a shadow arrangement according to the invention for internal registers 2 and internal buffers 3 the effort required for this can be significantly reduced for the user, since the essential data and the processor are backed up in a non-volatile manner 1 can continue his work from the point at which he was interrupted.

Another area of application for the processors mentioned 1 is computer technology. In the case of extensive program systems, the processor 1 a large amount of temporary data in internal registers 2 and buffering 3 managed, which are no longer available after additional power interruptions without additional measures.

With the use of non-volatile memory elements as registers 2 or buffer 3 significant application advantages can thus also be achieved in computer technology. In practical use, this means that a correspondingly constructed computer can also be switched off in an active application and the last processing state is available again when the computer is switched on again, ie started programs, screen orders and processed data are retained. This application is particularly interesting if inexpensive non-volatile RAMs with large storage capacities, such as those that can be used in the future, for example, Ferro-RAMs or magnetoresistive RAMs, are available.

1

processor

2

internal register

3

buffer

4

Arithmetic logic unit

4a

processor component

5

internal system

6

internal Storage

7

external system

8th

external data storage

9

external program memory

10

internal control line

11

Voltage monitoring circuit

12

external control line

13

capacitor

14

V _CAP pin

15

system clock

16

capacitor

17

memory cell

18

memory cell

Claims (8)

Integrated logic circuit arrangement from a processor or controller arrangement with internal processor units, such as arithmetic logic unit, command counter, address and data buffer or the like, and with at least one internal register or memory element with register function, thereby known records that at least the internal register ( 2 ) is designed as a non-volatile register such that it consists of a static memory element to which a non-volatile shadow memory element is directly assigned and that a voltage monitoring circuit ( 11 ) with a control output that triggers a signal when the voltage falls below a target voltage ( 10 ) is provided, which - controlling the non-volatile memory transfer - is connected to the register and buffer elements. Integrated logic circuit arrangement according to claim 1, characterized in that inner buffer areas also as a non-volatile Buffer areas with the design of the non-volatile register are executed. Integrated logic circuit arrangement according to Claim 1 or 2, characterized in that the control output ( 10 ) is designed for additional external connection. Integrated logic circuit arrangement according to one of the Expectations 1 to 3, characterized in that the access time of the non-volatile Storage at least in the order of magnitude is equal to the access time of the processor units. Integrated logic circuit arrangement according to one of the Expectations 1 to 4, characterized in that the internal and / or external program and Data storage as non-volatile Memory can be realized. Integrated logic circuit arrangement according to one of Claims 1 to 5, characterized in that one of the STORE and RECALL functions in the register ( 2 ), in the internal ( 3 ) and possibly in external memories ( 8th ; 9 ) synchronizing control line ( 12 ) is provided. Integrated logic circuit arrangement according to one of the Expectations 1 to 6, characterized in that non-volatile register, memory and / or buffer elements at least partially as ferro RAMs or magnetoresistive RAMs are formed. Integrated logic circuit that is a sequential Has working method and at least partially consists of flip-flops, characterized in that at least a non-volatile flip-flop is trained.