DE19818853A1 - Integrated logic circuit - Google Patents

Abstract

The logic circuit has a processor (1) or controller arrangement with internal processor units such as an arithmetic-logic unit (4), command counters, address and data buffers, etc. and at least one internal register (2) or a memory element (3) with a register function. At least the internal register is in the form of a nonvolatile memory. Internal buffer areas can be implemented as nonvolatile buffer areas

Description

The invention relates to an integrated logic circuit arrangement voltage from a processor or controller arrangement with inter NEN processor units, such as arithmetic logic unit, instruction counter, buffer, and with at least one internal register or storage element with register function. The invention be also hits an integrated logic circuit that sequences one tial working method and at least partially from flip Flops exist.

Logic circuits are known which are designed as processors which are via volatile internal registers and Address, data and other buffers.

Most of these processors are also with external and / or internal program and data memories. This store consist of a memory matrix, which is a number individual memory cells as well as those for selection and storage access required logic (e.g. decoder, I / O stages and Buffer) contains.

The registers mentioned include, for example, command registers, Command counter, data register, condition register, intermediate and auxiliary register, interrupt register, pointer and / or stack  register. The buffers include, for example, address buffers, Data buffer, buffer for control and I / O signals, interrupt interrupt nale and additional buffer elements, for example for the State storage in internal function blocks, such as arithmetic logic unit, address unit, arithmetic unit, control unit, inter main control logic, memory access control, instruction decoder and sequence control.

The external and internal program and data storage will be both as volatile and non-volatile memories realized. Volatile memories, such as SRAMs and DRAMs have the advantage of high access speed speed, which makes the application a fast read / write memory is supported. The disadvantage, however, is that this memory lose their content in the event of voltage interruptions if not additional measures - e.g. B. battery backup - be provided.

A known way to avoid a program or Data loss due to a voltage interruption exists in the realization of non-volatile memory areas for processes sensors by using a ROM, (E) EPROM or a flash Memory. These memories keep their content even without one Voltage buffering in the event of interruptions in the operating voltage, cannot, however, be described more than once or only to a limited extent become. They also have compared to SRAMs and DRAMs relatively long writing times. For these reasons, they find named non-volatile memory types mainly as Memory for programs and parameters that are not used or only need to be changed relatively rarely.

A combination of the advantages of volatile memory (high Access speed) and a non-volatile memory (Data retention even in the event of a power failure) offer at for example nvSRAMs, Ferro-RAMs and magnetoresistive RAMs.

Memory with the designation nvSRAM (non volatile SRAM) best consist of an SRAM part and an EEPROM part, the EE  PROM serves as a non-volatile shadow memory for the SRAM, so that the data content is maintained even when the voltage is interrupted remains. An nvSRAM is characterized by a slight change Ability, a large number of write cycles and a high Access speed. The nvSRAM allows the reali non-volatile, faster and easily changeable Read / write memory.

nvSRAMs are used today especially as external data storage used. In principle, implementation as an inte Free memory area for data and programs in processing or controllers possible.

While the external and / or internal storage of the Storage of programs and data areas are used the internal registers and buffers mainly for intermediate Storage of data and program code, address and I / O information mations and intermediate results of operations of the process used for direct program processing and controlling the operation of the processor and its peri serve pheria.

These internal registers and buffers are very large large number of read / write cycles. Will continue a high access speed is required for them, since this a direct impact on performance and work processor speed. For this reason the registers and buffers are currently basically called volatile memory elements with high working speed, for example, as units constructed from flip-flops leads.

The disadvantage here is that these internal registers and buffers lose their content in the event of voltage interruptions, so that the relevant information when the Processor are no longer available. From this results regularly the need to restart the system with a reinitialization of the register contents.  

To avoid this disadvantage, additional measures, such as battery backup of the processor, be provided. However, this represents the lifespan the backup battery is a problem. To solve the same who the additional measures, such as implementation power management. Here are different energy saving procedures, such as switching off sub-components or reducing the clock rate. Increase these funds hen, however, the manufacturing cost of processor arrangement gene.

Higher performance processor arrays are also through characterized a higher power consumption, so that one limitations in the long-term applicability of a battery buffering result. In this case, further measures that represent an additional effort for data backup required.

Another way to avoid data loss in the event of an interruption, the current content of internal registers, stores and buffers in one not swap volatile memory. For example EEPROMs or flash memory can be used.

The known effect of notebooks shows a similar effect Suspend-to-disk procedure, which ensures that a working state secured before switching off, a finally the activated programs, whoever is restored that can.

After a power-up reset, suitable start routines are opened called the correct continuation of the work of the Pro support the cessors. Access control to used memory areas can be done by software routines, so that in Processing existing data segments or open files with undefined content can be recognized.

An uninterrupted continuation of the processor's work  or the microcontroller after outsourcing the internal regi There is no stereos or buffer content in the cases mentioned possible because basically a start routine after power-up must be carried out, the reloading of the power Down saved register or memory contents caused. The current work status is also included unforeseen voltage interruptions problematic because a storage of the complete data set including the temporary registers, address and data buffers and others State variables of the processor only guaranteed to a limited extent can be. This applies particularly to the suspend-to-disk Procedure to.

It is therefore an object of the invention, an integrated logic circuit specify that while maintaining a fast Access to storage elements after a power failure a restart in the state before the power cut case was made possible.

The object of the invention is in the case of integrated logic circuits from a processor or controller arrangement with internal Processor units solved in that at least internal regi ster are designed as non-volatile memory elements.

In addition, the implementation is non-volatile inner buffer areas, so that a largely interruptible speed can also be achieved within command cycles.

Processors can be used with the registers and buffers described can be realized, their internal data content at voltage failure remain, so that the processor when re- start practically without interruption can.

In a favorable embodiment it is provided that registers and buffer areas made up of static memory elements with a associated shadow EEPROM exist and that a voltage Monitoring circuit with a if a target is undershot  voltage signal triggering control output is provided, the controlling the non-volatile memory takeover with the Register and buffer elements is connected. Here it is possible that the control output to the additional external An conclusion is formed.

By using a shadow arrangement according to the invention for internal registers and buffers of processors Disadvantages of the prior art overcome, since under Beibe keeping the processor working fast after one Power failure a restart of the processor in the close status that existed before the power failure becomes.

It is to adapt the working speeds to each other expedient that the access time of the non-volatile register and buffers at least on the order of equal to access time of the processor units.

A particularly favorable embodiment is characterized net that also the internal and / or external program and Data storage can be realized as non-volatile storage, so that a consistent system design in terms of non-volatile mode of operation of the processor is given. Consequently can secure the entire processor system from data loss and practically a start / stop operation with voltage interruptions are carried out.

Finally, it is advisable that the STORE and RECALL Functions in the register, in the internal and possibly control line synchronizing in external memories is seen.

A further advantageous embodiment of the invention exists in that non-volatile register memory and / or buffer elements at least partially as ferro RAMs or magnetoresi stive RAMs are formed.  

The task according to the invention is integrated Logic circuits that operate sequentially and which at least partially consist of flip-flops, too solved in that at least one flip-flop is non-volatile is trained.

The sequential way of working is for example for tax circuits, registers and counters typical. With the equipment through non-volatile flip-flops there is the possibility to Status information, for example, even in the event of a voltage drop save refractions.

The invention is described below with reference to an embodiment game are explained in more detail. In the accompanying drawings shows

Fig. 1 is a schematic representation of an inventive Pro zessors with non-volatile registers and memories with register function,

Fig. 2 shows a section of a program to be executed,

Fig. 3 is a schematic diagram of the behavior after a power cut using the program section and

Fig. 4 is a flowchart to illustrate the programmtech African jump in the process after a power interruption.

As shown in Fig. 1, a processor 1 is provided with an internal register 2 , an internal buffer 3 with register functions, an arithmetic logic unit 4 and other processor components 4 a. The internal register 2 and the internal buffer 3 are designed as a shadow configuration with an EEPROM cell. Furthermore, an internal system bus 5 is seen before, which serves to connect the modules to one another. Furthermore, an internal memory 6 is integrated, which is part of the program and data memory (not shown).

Via an external system bus 7 , additional non-volatile external data memories (nvSRAM) 8 and external program memories (flash) 9 are coupled to the processor 1 . The STORE / RECALL processes in the processor 1 and the external data memory 8 are synchronized via an internal control line 10 , so that the necessary data consistency can be maintained.

The supply voltage of the system is constantly checked by a voltage monitoring circuit 11 . If the supply voltage drops below a certain level, a STORE process is triggered. For the STORE process, the current computing and transmission processes in the system are stopped and then a backup of the contents of register 2 and buffer 3 in the EEPROM of the shadow arrangement is initiated. The STORE signal is forwarded to the external data memory 8 via an external control line 12 . The energy required for data backup in the EEPROM of register 2 and buffer 3 is provided by an external capacitor 13 which is connected via a special V _CAP pin 14 .

A system clock 15 is also provided, which can also be buffered with a capacitor 16 . The current time stamp is saved with a checksum, so that after a power-up it can be recognized whether the system clock 15 was continuously active during a voltage interruption.

After a power-up, the EEPROM content of the shadow arrangement of register 2 and buffer 3 is first reloaded into the volatile part of the shadow arrangement, which is referred to as RECALL, and the content of system clock 15 stored during power-down is read out . Instead of the power-up reset in conventional processor systems, a signal for a power-up interrupt routine can optionally be activated. The interrupted processes are then continued without restarting the system.

The interrupt routine can be started at the next possible time. Depending on whether time conditions in the event of voltage interruptions are to be taken into account (e.g. when used in process control), the difference between the saved system time, which is stored in a memory cell 17 , and the current time, which is in a memory cell, is evaluated 18 is stored. If an exceeding of a predetermined time interval is determined, a system restart or other necessary measures, e.g. B. Checking parameters or reinitialization of peripheral assemblies. If no violation of time conditions and parameters was found, the interrupt routine is ended without further activities and the current program flow is continued. If such an interrupt routine is dispensed with, the program itself cannot detect an interruption in its work due to a power down.

In Fig. 2 the part of a program to be processed is provided. For example, a voltage interruption occurs during the processing of program line 656 , which forces a power down in processor 1 . With this power-down, the current values are stored in a non-volatile manner in the manner shown and are again available for a power-up that occurs after the voltage interruption has ended. As can be seen in FIG. 3, work can be continued immediately in line 656 after the voltage interruption.

In Fig. 4 it is shown that an interruption of the Be operating voltage causes immediate jump to the normal process. The dashed line here represents the sequence after the voltage interruption.

A possible area of application for such processors 1 is control technology, in which microprocessors or microcontrollers are often used, which must store important process data even in the event of voltage interruptions and ensure a defined restart. With the use of a shadow arrangement according to the invention for internal registers 2 and internal buffers 3 , the effort required for this can be significantly reduced for the user, since the essential data are saved in a non-volatile manner and the processor 1 can continue its work at the point at which he was interrupted.

Another area of application for the processors 1 mentioned is computer technology. In the case of extensive program systems, processor 1 manages a large number of temporary data in internal registers 2 and buffers 3 , which are no longer available without additional measures after voltage interruptions.

With the use of non-volatile memory elements as register 2 or buffer 3 , we can achieve significant application advantages in computer technology. In practical application, this means that a correspondingly constructed computer can also be switched off in an active application and the last processing state is available again when the computer is switched on again, ie started programs, screen arrangements and processed data are retained. This application is particularly interesting when low-cost, non-volatile RAMs with large storage capacities, such as those that can be used in the future, such as ferro-RAMs or magnetoresistive RAMs, are available.

Reference list

1

processor

2nd

internal register

3rd

buffer

4th

Arithmetic logic unit

4th

a processor component

5

internal system bus

6

Internal memory

7

external system bus

8th

external data storage

9

external program memory

10th

internal control line

11

Voltage monitoring circuit

12th

external control line

13

capacitor

14

V _CAP

-Pin code

15

System clock

16

capacitor

17th

Memory cell

18th

Memory cell

Claims (9)

1. Integrated logic circuit arrangement from a processor or controller arrangement with internal processor units, such as arithmetic logic unit, command counter, address and data buffer or the like, and with at least one internal register or memory element with register function, as characterized in that at least the internal register ( 2 ) is formed as a non-volatile memory. 2. Integrated logic circuit arrangement according to claim 1, characterized in that inner Buffer areas as non-volatile buffer areas leads are. 3. Integrated logic circuit arrangement according to claim 1 or 2, characterized in that regi ster and buffer areas consist of static memory elements with an associated shadow EEPROM and that a voltage monitoring circuit ( 11 ) is provided with a signal-triggering control output ( 10 ) when the target voltage drops below , which controls the non-volatile memory transfer with the register and buffer elements. 4. Integrated logic circuit arrangement according to claim 3, characterized in that the control er output ( 10 ) is formed out for additional external connection. 5. Integrated logic circuit arrangement according to one of the An sayings 1 to 4, characterized net that the access time of the non-volatile memory at least in the order of magnitude equal to the access time of the Processor units. 6. Integrated logic circuit arrangement according to one of the An sayings 1 to 5, characterized net that the internal and / or external program and data storage realized as non-volatile storage become. 7. Integrated logic circuit arrangement according to one of claims 1 to 6, characterized in that one of the STORE and RECALL functions in the register ( 2 ), in the internal ( 3 ) and optionally in external memories ( 8 ; 9 ) synchronizing Control line ( 12 ) is provided. 8. Integrated logic circuit arrangement according to one of the An sayings 1 to 7, characterized net that non-volatile register, memory and / or Buffer elements at least partially as ferro RAMs or magnetoresistive RAMs are formed. 9. Integrated logic circuit, which is a sequential working has wise and at least partially from flip-flops consists, characterized in that at least one flip-flop is designed to be non-volatile.