DE3619636A1 - Housing for integrated circuits - Google Patents

Housing for integrated circuits

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Publication number
DE3619636A1
DE3619636A1 DE19863619636 DE3619636A DE3619636A1 DE 3619636 A1 DE3619636 A1 DE 3619636A1 DE 19863619636 DE19863619636 DE 19863619636 DE 3619636 A DE3619636 A DE 3619636A DE 3619636 A1 DE3619636 A1 DE 3619636A1
Authority
DE
Germany
Prior art keywords
strip
conductor tracks
housing
housing according
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19863619636
Other languages
German (de)
Inventor
Wolfgang Dipl Phys Dr Hauger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE19863619636 priority Critical patent/DE3619636A1/en
Publication of DE3619636A1 publication Critical patent/DE3619636A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01028—Nickel [Ni]
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A housing is proposed for integrated circuits whose connections are connected to a respectively predetermined number of conductor tracks. In this case, the integrated circuits are inserted in a blank strip which has the conductor tracks on the edges and are coated with a potting compound. The individual housings can then be sawn off the complete blank strip in a simple manner. Housings having extremely small external dimensions can be produced easily in this way. <IMAGE>

Description

Stand der TechnikState of the art

Die Erfindung geht aus von einem Gehäuse für inte­ grierte Schaltkreise gemäß Oberbegriff des Hauptanspruchs. Beispielsweise bei Hörgeräteverstärker sind die Außen­ maße eines Gehäuses zur Aufnahme eines integrierten Schaltkreises genau vorgeschrieben. Diese Außenmaße sind im Verhältnis zu der gewünschten Anzahl der elektrischen Anschlüsse so gering, daß bekannte Gehäuse für integrierte Schaltungen keine Anwendung finden können. Beispielsweise haben die Leadless Chip-Carrier und die sogenannten SOL-Gehäuse ein Rastermaß für die Anschlüsse, d.h. für den Abstand der Anschlüsse, von 1,27 mm und benötigen deshalb bei gewünschten vier Anschlüssen pro Gehäuseseite zumindest eine Breite des Gehäuses von über 5 mm. Für viele Anwendungsfälle sind jedoch deutlich geringere Außenabmessungen erwünscht.The invention relates to a housing for inte free circuits according to the preamble of the main claim. In the case of hearing aid amplifiers, for example, the outside dimensions of a housing to accommodate an integrated Circuit prescribed exactly. These external dimensions are in relation to the desired number of electrical Connections so small that known housings for integrated Circuits cannot find application. For example have the leadless chip carriers and the so-called SOL housing a grid dimension for the connections, i.e. For the distance of the connections, of 1.27 mm and need therefore with four desired connections per side of the housing at least a width of the housing of over 5 mm. For however, many use cases are significantly smaller Outside dimensions desired.

Vorteile der ErfindungAdvantages of the invention

Das erfindungsgemäße Gehäuse für integrierte Schalt­ kreise mit den Merkmalen des Hauptanspruchs hat demgegen­ über den Vorteil, daß die Außenmaße des Gehäuses wesentlich verringert und die Montagetechnik beziehungs­ weise die Herstellung des einzelnen Bauelements verein­ facht sind. Die Befestigung der integrierten Schaltkreise an einem Nutzenstreifen und seine Verbindung mit den randseitig angeordneten Leiterbahnen benötigt nur wenige Arbeitsschritte, nämlich das Festlegen der integrierten Schaltkreise und das Bonden der Anschlüsse mit den Leiterbahnen.The housing according to the invention for integrated switching circles with the features of the main claim has  about the advantage that the outer dimensions of the housing significantly reduced and the assembly technology relation as the manufacture of the individual component are fold. The attachment of the integrated circuits on a utility strip and its connection with the only a few are required on the edge-side arranged conductor tracks Work steps, namely the determination of the integrated Circuits and bonding the connectors with the Conductor tracks.

Bevorzugt sollen die integrierten Schaltkreise in einer rillenförmigen Vertiefung in dem Nutzenstreifen fest­ gelegt sein, so daß das Bonden der Anschlüsse mit den Leiterbahnen etwa auf gleicher Höhe stattfindet. Das Festlegen der Schaltkreise in oder an dem Nutzenstreifen kann durch Klebung mit einem geeigneten Haftvermittler erfolgen.The integrated circuits should preferably be in one groove-shaped depression in the benefit strip be placed so that the bonding of the connections with the Conductor tracks take place at approximately the same height. The Define the circuits in or on the utility strip can be done by gluing with a suitable bonding agent respectively.

Es ist vorgesehen, die randseitig an dem Nutzenstreifen angeordneten Leiterbahnen mittels Durchkontaktieren von der Ober- auf die Unterseite des Nutzenstreifens zu führen. Das gleiche Ergebnis wird aber auch erzielt, wenn die Leiterbahnen um den Nutzenstreifen herum von dessen Ober- auf seine Unterseite geführt werden. Als Material für die Leiterbahnen bietet sich Kupfer an, welches galvanisch vernickelt und vergoldet ist. Das Bonden wird bevorzugt durch Ultraschallschweißen von Gold­ drähten durchgeführt. Für den Nutzenstreifen selbst kommt übliches Leiterplattenmaterial in Betracht. Es ist leicht erkennbar, daß bei der Wahl der Werkstoffe und der Ver­ ringerung der Arbeitsschritte auch mit geringeren Stoff- und Werkzeugkosten zu rechnen ist. Die bekannten Leadless Chip-Carrier sind dagegen vom Material her wesentlich teurer, die SOL-Gehäuse benötigen hohe Werkzeugkosten.It is provided that the edge of the benefit strip arranged conductor tracks by means of plated-through holes from the top to the bottom of the benefit strip to lead. The same result is also achieved if the conductor tracks around the utility strip from the top of which are led to its bottom. As Copper is the material for the conductor tracks, which is galvanically nickel-plated and gold-plated. The Bonding is preferred by ultrasonic welding of gold wires performed. For the benefit strip itself comes usual PCB material into consideration. It is easy recognizable that in the choice of materials and Ver reduction of work steps even with less material and tool costs can be expected. The well-known leadless Chip carriers, on the other hand, are materially important more expensive, the SOL housings require high tool costs.

Nach dem Festlegen und Bonden der integrierten Schalt­ kreise wird auf den Nutzenstreifen eine Vergußmasse in Form aufgebracht. Diese Vergußmasse kann gegebenenfalls noch mit Glasfasern gefüllt sein. Bei dieser Montageart können Gesamtdicken für Nutzenstreifen plus Vergußmasse von 1,4 mm und ein Rastermaß von weniger als 0,7 mm erreicht werden.After setting and bonding the integrated circuit  a potting compound is placed in circles on the Form applied. This potting compound can if necessary still be filled with glass fibers. With this type of installation can total thicknesses for benefit strips plus casting compound of 1.4 mm and a grid dimension of less than 0.7 mm can be achieved.

Von dem Nutzstreifen werden nun die einzelnen Bauelemente mittels einer Diamantsäge oder dergleichen abgetrennt, wobei jedes Bauelement einen integrierten Schaltkreis und eine vorgegebene Anzahl von elektrischen Anschlüssen enthält. Es können beispielsweise 8 elektrische Anschlüsse an jedem Bauelement vorgesehen sein, dessen Breite des Gehäuses 2,7 mm betragen kann. Selbstverständlich ist dieser Lösungsvorschlag auch für inte­ grierte Schaltkreise mit einer größeren oder kleineren Anzahl von elektrischen Anschlüssen geeignet.The individual components are now made from the useful strip separated by means of a diamond saw or the like, each component being an integrated circuit and a predetermined number of electrical connections contains. For example, there can be 8 electrical connections on each Component may be provided, the width of the housing being 2.7 mm can. Of course, this proposed solution is also for inte circuits with a larger or smaller number of electrical connections.

Zeichnungdrawing

Die Erfindung wird nachfolgend anhand der Zeichnung erläutert. Diese zeigt inThe invention is described below with reference to the drawing explained. This shows in

Fig. 1 eine Draufsicht auf ein erfindungsgemäßes Gehäuse mit integriertem Schaltkreis vor dem Aufbringen einer Vergußmasse; Figure 1 is a plan view of a housing according to the invention with an integrated circuit before the application of a potting compound.

Fig. 2 einen Querschnitt durch das Gehäuse nach Fig. 1 entlang Linie II-II in einer geringfügig abgeänderten Ausführungsform und mit aufgebrachter Vergußmasse. Fig. 2 shows a cross section through the housing of FIG. 1 along line II-II in a slightly modified embodiment and with potting compound applied.

Gemäß Fig. 1 weist ein Nutzenstreifen 1 aus Leiter­ plattenmaterial eine rinnenförmige Vertiefung 2 entlang seiner Längsachse 3 auf. Randseitig sind an den Nutzen­ streifen 1 beidseits Kupfer-Leiterbahnen 4 angeordnet, welche nach dem Ausführungsbeispiel in Fig. 1 mittels Durchkontaktierung von der Ober- auf die Unterseite geführt sind. In dem Ausführungsbeispiel nach Fig. 2 sind gegen die Kupfer-Leiterbahnen 4 a die Seitenkanten des Nutzenstreifens 1 herum gelegt und so von der Ober- auf die Unterseite geführt. Die Kupfer-Leiterbahnen 4 bzw. 4 a sollen bevorzugt galvanisch vernickelt und vergoldet sein.According to Fig. 1 has a benefit strip 1 of circuit board material to a trough-shaped recess 2 along its longitudinal axis 3. On the edge strips 1 are arranged on both sides of copper strip conductors 4 which, according to the exemplary embodiment in FIG. 1, are guided from the top to the bottom by means of plated-through holes. In the exemplary embodiment according to FIG. 2 , the side edges of the utility strip 1 are placed around the copper conductor tracks 4 a and are thus guided from the top to the bottom. The copper conductor tracks 4 and 4 a should preferably be electroplated and gold-plated.

In der rillenförmigen Vertiefung 2 ist ein integrierter Schaltkreis 5 festgelegt, bevorzugt eingeklebt. Die elektrische Verbindung zwischen dem integrierten Schalt­ kreis 5 und den Leiterbahnen 4 bzw. 4 a wird mittels Ultraschweißen (Bonden) von Golddrähten 6 durchgeführt.An integrated circuit 5 is fixed, preferably glued, in the groove-shaped recess 2 . The electrical connection between the integrated circuit 5 and the conductor tracks 4 and 4 a is carried out by means of ultrasonic welding (bonding) of gold wires 6 .

Danach wird auf den Nutzenstreifen 1 in einer Form eine glasfasergefüllte Vergußmasse 7 aufgebracht, die durch Aufheizen aushärtet. Die Form ist so gewählt, daß der Nutzenstreifen 1 inklusive der Vergußmasse 7 eine Dicke d von 1,4 mm aufweist. Die Länge l des Nutzenstreifens 1 bzw. der Vergußmasse 7 beträgt 3,5 mm.Thereafter, a glass fiber-filled casting compound 7 is applied to the utility strip 1 in a mold and cures by heating. The shape is chosen so that the utility strip 1 including the sealing compound 7 has a thickness d of 1.4 mm. The length l of the useful strip 1 or the casting compound 7 is 3.5 mm.

Im vorliegenden Ausführungsbeispiel wird ein Nutzen­ streifen 1 für 20 Bauelemente verwendet. Nach dem Aufbringen der Vergußmasse 7 auf den Nutzenstreifen 1 mit dem integrierten Schaltkreis 5 werden die einzelnen Bauelemente mittels einer Diamantsäge voneinander getrennt und anschließend elektrisch gemessen. Die Schrittbreite der Diamantsäge ist in Fig. 1 mit s be­ zeichnet. Sie ist so gewählt, daß jedes Bauelement eine Breite b von 2,7 mm erhält.In the present embodiment, a strip 1 is used for 20 components. After the potting compound 7 has been applied to the utility strip 1 with the integrated circuit 5 , the individual components are separated from one another by means of a diamond saw and then measured electrically. The step width of the diamond saw is marked in Fig. 1 with s be. It is chosen so that each component has a width b of 2.7 mm.

Im vorliegenden Ausführungsbeispiel sind gemäß Fig. 1 acht Leiterbahnen 4 für elektrische Anschlüsse gezeigt. Je nach Wunsch ist diese Anzahl aber jederzeit variierbar. Im dargestellten Ausführungsbeispiel ist das Rastermaß (mittlerer Abstand) der Leiterbahnen 4 nur 0,6235 mm.In the present exemplary embodiment, eight conductor tracks 4 for electrical connections are shown in accordance with FIG. 1. However, this number can be varied at any time as desired. In the illustrated embodiment, the grid dimension (average distance) of the conductor tracks 4 is only 0.6235 mm.

Claims (8)

1. Gehäuse für integrierte Schaltkreise, deren Anschlüsse mit einer jeweils vorgegebenen Anzahl von Leiterbahnen verbunden sind, dadurch gekennzeichnet, daß die integrierten Schaltkreise (5) an einem Nutzenstreifen (1) befestigt sind, der randseitig die Leiterbahnen (4, 4 a) aufweist, welche mit den Anschlüssen der integrierten Schaltkreise (5) durch Bondverbindungen elektrisch verbunden sind.1. Housing for integrated circuits, the connections of which are connected to a respectively predetermined number of conductor tracks, characterized in that the integrated circuits ( 5 ) are fastened to a utility strip ( 1 ) which has the conductor tracks ( 4 , 4 a ) at the edge, which are electrically connected to the connections of the integrated circuits ( 5 ) by means of bond connections. 2. Gehäuse nach Anspruch 1, dadurch gekennzeichnet, daß die Schaltkreise (5) in einer rillenförmigen Vertiefung (2) in dem Nutzenstreifen (1) festgelegt, bevorzugt aufgeklebt, sind.2. Housing according to claim 1, characterized in that the circuits ( 5 ) in a groove-shaped recess ( 2 ) in the utility strip ( 1 ) fixed, preferably glued. 3. Gehäuse nach Anspruch 1 oder 2, dadurch gekenn­ zeichnet, daß die Leiterbahnen (4) mittels Durch­ kontaktieren von der Ober- auf die Unterseite des Nutzenstreifens (1) geführt sind.3. Housing according to claim 1 or 2, characterized in that the conductor tracks ( 4 ) by means of contact from the top to the bottom of the utility strip ( 1 ) are guided. 4. Gehäuse nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die Leiterbahnen (4 a) um den Nutzenstreifen (1) herum von dessen Ober- auf seine Unterseite geführt sind.4. Housing according to claim 1 or 2, characterized in that the conductor tracks ( 4 a ) are guided around the utility strip ( 1 ) from its top to its bottom. 5. Gehäuse nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß der Nutzenstreifen (1) mit festge­ legtem und gebondetem, integriertem Schaltkreis (5) von einer gegebenfalls glasfasergefüllten Vergußmasse (7) belegt ist.5. Housing according to one of claims 1 to 4, characterized in that the useful strip ( 1 ) with festge laid and bonded, integrated circuit ( 5 ) is occupied by an optionally glass-fiber-filled sealing compound ( 7 ). 6. Gehäuse nach Anspruch 5, dadurch gekennzeichnet, daß bei einer Dicke (d) des Nutzenstreifens (1) zuzüglich der Vergußmasse (7) von 1,4 mm, einer Länge (l) von 3,5 mm und einer Breite (b) von 2,7 mm die Anschlüsse ein Rastermaß von 0,635 mm haben.6. Housing according to claim 5, characterized in that at a thickness ( d ) of the utility strip ( 1 ) plus the sealing compound ( 7 ) of 1.4 mm, a length ( l ) of 3.5 mm and a width ( b ) of 2.7 mm the connections have a grid dimension of 0.635 mm. 7. Gehäuse nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß der Nutzenstreifen (1) aus Leiterplattenmaterial, vorzugsweise aus Epoxydharz, besteht, auf dem die Leiterbahnen (4, 4 a) in an sich bekannter Weise galvanisch vernickelt und vergoldet sind.7. Housing according to one of the preceding claims, characterized in that the useful strip ( 1 ) consists of printed circuit board material, preferably of epoxy resin, on which the conductor tracks ( 4 , 4 a ) are galvanically nickel-plated and gold-plated in a manner known per se. 8. Gehäuse nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß eine Vielzahl von inte­ grierten Schaltkreisen (5) auf einem Nutzenstreifen (1) befestigt ist, und daß die Gehäuse für die einzelnen Schaltkreise (5) vom Nutzenstreifen (1) mittels einer Säge abgetrennt sind.8. Housing according to one of the preceding claims, characterized in that a plurality of inte grated circuits ( 5 ) on a utility strip ( 1 ) is fixed, and that the housing for the individual circuits ( 5 ) from the utility strip ( 1 ) by means of a saw are separated.
DE19863619636 1986-06-11 1986-06-11 Housing for integrated circuits Withdrawn DE3619636A1 (en)

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US4980753A (en) * 1988-11-21 1990-12-25 Honeywell Inc. Low-cost high-performance semiconductor chip package
DE4101790C1 (en) * 1991-01-18 1992-07-09 Technisch-Wissenschaftliche-Gesellschaft Thiede Und Partner Mbh, O-1530 Teltow, De Chip-support arrangement prodn. - in tape form, in dual-in-line format by film-bond technology
EP0689245A3 (en) * 1994-06-22 1996-08-07 Seiko Epson Corp Electronic device, its arrangement and method of manufacturing the same
US5832600A (en) * 1995-06-06 1998-11-10 Seiko Epson Corporation Method of mounting electronic parts
FR2764111A1 (en) * 1997-06-03 1998-12-04 Sgs Thomson Microelectronics METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGES INCLUDING AN INTEGRATED CIRCUIT
DE19743365A1 (en) * 1997-09-30 1999-04-08 Siemens Ag Method for producing a multi-level wiring carrier (substrate), in particular for multichip modules
US6054338A (en) * 1996-05-17 2000-04-25 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980753A (en) * 1988-11-21 1990-12-25 Honeywell Inc. Low-cost high-performance semiconductor chip package
DE4101790C1 (en) * 1991-01-18 1992-07-09 Technisch-Wissenschaftliche-Gesellschaft Thiede Und Partner Mbh, O-1530 Teltow, De Chip-support arrangement prodn. - in tape form, in dual-in-line format by film-bond technology
EP0689245A3 (en) * 1994-06-22 1996-08-07 Seiko Epson Corp Electronic device, its arrangement and method of manufacturing the same
US5832600A (en) * 1995-06-06 1998-11-10 Seiko Epson Corporation Method of mounting electronic parts
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US6054338A (en) * 1996-05-17 2000-04-25 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
EP0883171A1 (en) * 1997-06-03 1998-12-09 STMicroelectronics S.A. Semiconductor package manufacturing method having an integrated circuit
US6087202A (en) * 1997-06-03 2000-07-11 Stmicroelectronics S.A. Process for manufacturing semiconductor packages comprising an integrated circuit
FR2764111A1 (en) * 1997-06-03 1998-12-04 Sgs Thomson Microelectronics METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGES INCLUDING AN INTEGRATED CIRCUIT
DE19820319B4 (en) * 1997-07-08 2005-12-01 National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara Semiconductor device
DE19743365A1 (en) * 1997-09-30 1999-04-08 Siemens Ag Method for producing a multi-level wiring carrier (substrate), in particular for multichip modules
US6451628B1 (en) 1997-12-25 2002-09-17 Sanyo Electric Co., Ltd. Method fabricating a semiconductor device with a decreased mounting area

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