DE3612233A1 - SAMPLE TESTING PROCEDURE - Google Patents

Description

HITACHI, LTD.

6, Kanda Surugadai 4-chome

Chiyoda-ku, Tokyo, Japan

Sample test procedure

The invention relates to a method for testing wiring smus te rs on a printed wiring board, one integrated circuit or the like, and in particular a comparative test method, through the two patterns that have the same Shape have to be compared with each other in order to capture that part of a pattern as a defect that differs from one corresponding part of the other pattern.

[Α / In general, when the image of an integrated circuit circuit pattern formed on a photo mask or other patterns are to be examined, a reference image and an image to be examined must be prepared. These images are optically superimposed and then visually compared to find a place where the images differ from each other, thereby detecting an error. With visual inspection, the likelihood of overlooking a mistake increases due to the person inspecting being tired.

In view of this problem, a feature comparison method has already been developed developed by each of the reference image and the examined image from an image pickup device are supplied in the form of image signals and the two image signals thus obtained together for automatic Detection of an error can be compared. However, this method is due to character errors in the creation of a

-X- 3812233

Circuit pattern from a drawn pattern (namely, a reference pattern) and because of positioning errors in each Image a misalignment between the two images is inevitable. Japanese Patent Laid-Open No. 59-24361 discloses a Comparative tester for two-dimensional images. this device can detect both a defect as large as a circuit pattern and a very small defect »A complicated, fine and normal circuit pattern becomes when this normal circuit pattern deviates from a reference pattern within a tolerable alignment error range, not recognized as an error.

This device converts two image signals supplied by an image recording device into binary signals and one with inputs A stored comparison element connected to a logic network is used for each of the binary signals for the detection of boundary lines used parallel to the coordinate axes of a right-angled coordinate system. To grasp the border lines precisely In order to be able to do this, different types of predicates must be stored, i.e. that an element must be used to acquire a Boundary line that forms an angle of 4 5 ° to the coordinate axis and further comparison elements for capturing a corner area of a pattern must be saved. However, this results in the problem that a logical network, the content each stored element are supplied, extensive and thus the hardware in the device becomes extensive. aside from that there is a risk that if a complicated pattern is checked by comparing it with a few stored elements some errors will be missed, and the amount of incorrect information will grow.

The disadvantages of the prior art will now be explained in detail. To simplify matters, we take a case where Patterns only have border lines parallel to the X and Y directions (which are perpendicular to each other). Fig = 8 shows extraction operators, which is used to test a sample by the

time comparison method are necessary. Each extracting operator in Fig. 8 represents a kind of stored element. In this case, irregularities of a two-dimensional pattern composed of two or more picture elements (pixels) cannot be judged as a quantization error but only as an error. An extracting operator (hereinafter referred to as "operator") in part (a) of Fig. 8 for selecting (extracting) a boundary line will now be described. The operator is moved both on the reference sample and on the sample to be tested. If the relationships a. = a ₂ , b .. = b "and a ^ b. are satisfied, it is known that a boundary line runs parallel to the Y direction in an area where the operator is placed. The pattern irregularity corresponding to two or more pixels as shown in part (a) in Fig. 8 is judged to be a defect in the following manner. When the above operator is used on both the test pattern indicated by a solid line in Fig. 8 (a) and the reference pattern shown by a broken line, boundary lines parallel to the Y direction become only in the test pattern recorded. Thus, a pattern area containing the above boundary lines is judged to be defective. Although only the operator for detecting a boundary line parallel to the Y direction is shown in Fig. 8 (a), an operator for detecting a boundary line parallel to the Y direction is also absolutely necessary, which can be obtained by rotating the operator in part (a) of Fig. 8 can be formed by 90 °. However, an isolated defect corresponding to one pixel shown in Fig. 8 (b) cannot be detected by the above operators. Accordingly, an operator shown in Fig. 8 (b) is needed to detect small isolated patterns. When this operator is placed on part of a pattern and the relationship a. = a ₂ = a ₃ = b .. = b "= b ₃ and one of the relationships a. k C ₁ , a. 3 c "and a .. 3 c_ are fulfilled, it is known that a fine pattern is present in the area. When this operator is applied to both the test pattern shown by a solid line in Fig. 8 (b),

and the reference pattern shown by the solid line in Fig. 8 (b) is used, the fine pattern is detected only in the pattern to be inspected, and thus it is decided that it is an error. However, in a case where a defect several pixels long along a boundary line and one pixel wide is adjacent to the boundary line as shown in FIG Boundary line parallel to the X direction is extracted from both patterns at substantially the same position by the operator for detecting a boundary line parallel to the X direction, and thus an error cannot be detected. For this reason, one needs an operator shown in FIG. 8 (c) which is formed by rotating the operator in FIG. 8 (b) by 90 °. In another case where a two-dimensional pattern is defective at one of its corner portions, as shown in Fig. 8 (d), a boundary line of the irregularity (namely, the defect) parallel to the Y- The direction and the boundary line of the reference pattern parallel to the Y direction can be extracted at substantially the same position, whereby the above error cannot be detected. Therefore, in this case, the operator shown in Fig. 8 (d) is absolutely necessary. If this operator is placed on an area of a pattern, and all relationships a ₁ = a "= a ~ = a ^ = a, - = a _fi = a ₇ ; b ₁ = b ₂ = b ₃ = b ^ ; and a. ib are satisfied, it is known that there is a corner of the pattern in this area. When the operator is used both on the pattern to be checked indicated by a solid line in Fig. 8 (d) and on the reference pattern shown by a broken line, the corner is only present in the reference pattern, whereby can detect an error at the corner area of the sample to be inspected. There can be four types of corners in a pattern, so four operators are required to detect these corners. From the above explanation

It follows that in the conventional feature comparison method, eight types of operators (namely two types of operators for Selection of boundary lines, two types of operators for selecting fine patterns and four types of operators for selecting corners) will. In addition, eight logic circuits are required for a sample to be tested and a reference sample to the eight types of operators and thus 16 logic circuits It is necessary to record the above errors. Although FIG. 8 only shows boundary lines parallel to the X and Y directions, frequently Patterns formed with more intricate shapes. In order to examine such patterns, the scope of the tester must necessarily be to grow. It is the object of the invention to enable a sample test method that can also be carried out in a complicated manner Pattern can reliably detect an error without the likelihood of generating incorrect information and without increasing the scope of a test device executing the method.

According to the invention, a sample test method is used to achieve the above object indicated by which a local pattern is cut out of a binary pattern to be tested, an insensitive one Area set next to the boundary line of the local sample to be tested and the local sample to be tested with the exception of the insensitive area with a corresponding one local reference pattern with the exception of the insensitive area for the elimination of incorrect information due to of a quantization error and for detecting an error in the local pattern to be checked is compared without that the volume of a pattern testing machine increases, even if the local pattern to be tested is complicated.

In addition, a circuit arrangement which implements the above-mentioned pattern checking method is disclosed which is very fast and represents reliable error checking technology.

The invention is described in more detail below in exemplary embodiments with reference to the drawing. Show it:

1 shows a block diagram of an overall structure of a for the execution of the sample test method according to the invention intended device;

Fig. 2 is a block diagram of a circuit part which the Setting circuits 3 and 4 for the insensitive area and the output circuits 5, 6 and 7 for the local The image in Fig. 1 corresponds to that for cutting out a local image area and two insensitive image areas is used from an image to be inspected;

3 shows a block diagram of the structure of shift register groups, those used in the apparatus shown in Fig. 1;

Fig. 4 is a block diagram of a circuit part with which a local image from the image of a specified pattern (namely, a reference pattern) is cut out;

Fig. 5 is a circuit diagram of the error extraction circuit 10 of Fig. 1;

6 schematically shows a reference image and a corresponding image to be checked with various defects;

Fig. 7 schematically insensitive areas, the outside and within the boundary line of the errors shown in FIG. 6, so that the errors shown in FIG Device can perform a predetermined operation regardless of the nature of each failure; and

Fig. 8 is a diagram explaining that it is necessary to detect various kinds of defects by a conventional pattern selection method Extract operators corresponding to the errors are required.

In the following, with reference to FIGS. 1 to 6, an embodiment of a Sample test method according to the invention explained.

Fig. 1 shows a from a detector (this is an image recording device) 1 supplied image signal, which is converted by means of a binary conversion circuit 2 into a binary signal, which as image to be checked of an output circuit 5 for a local image and setting circuits 3 and 4 each for setting an insensitive one Area inside or outside the boundary line of the image to be inspected and for extracting the insensitive Area is fed. The output signals of the setting circuits 3 and 4 become insensitive image areas, respectively Output circuits 6 and 7 for local images are supplied. A reference picture signal stored in a reference picture memory 8 is stored in the form of a binary signal is fed to a local image output circuit 9 as a reference image. Of the Reference image memory 8 supplies the reference image signal accordingly of an image to be checked in synchronism with the scanning operation of the detector 1. An error is detected by an error extraction circuit 10 is detected on the basis of the outputs of the image output circuits 5, 6, 7 and 9 and as an error signal 11 submitted.

Fig. 2 shows the circuit structure of a setting circuits 3 and 4 and the location image output circuits 5 and 7 containing Circuit part. This circuit uses three memories 22 to 24, each containing 5x5 pixels, to enlarge, Contracting and judging a border area of the image to be inspected, thereby selecting three kinds of border areas.

An output signal 12 from the transfer circuit 2 of FIG. 1 is through a shift register group 13, which consists of three shift registers, each to a boundary line to one test pattern correspond to a location memory 14 is supplied, which has 3x3 bits and series input / parallel output shift registers is formed. The 3x3 outputs of the location memory 14 are an AND circuit 13 and an OR circuit 16 supplied. A limit area that results

when an original boundary area around a corresponding one pixel Amount is contracted is output from the AND circuit 13. A limit area that results when an original limit area is enlarged by an amount corresponding to one pixel is supplied from the OR circuit 16. The exit of the center pixel of the location memory 14 and the output of the AND circuit 13 are fed to an exclusive OR circuit 17, the a signal over an insensitive area, which is along an original boundary line on the inside with the Width of a pixel extends, generated with the level "1". Besides that the output of the center pixel of the location memory 14 and the output of the OR circuit 16 of a further exclusive OR circuit 18, which generates a signal over an insensitive area, which is in an area that is one pixel wide along the original boundary line on the outside thereof, assumes the "1" level.

The following is a circuit part for cutting out a local image of 5x5 pixels from the image to be inspected an insensitive area within a boundary line and an infinite area outside a boundary line. The output of the center pixel of the location memory 14, the output of the exclusive-OR circuit 17 and the output of the Exclusive-OR circuits 18 are fed to the local memories 22, 23 and 24 through shift register groups 19, 20 and 21, respectively. Each of the location memories 22 to 24 consists of a serial input / parallel output shift register and contains 5x5 pixels. Each shift register group 19 to 21 consists of five shift registers, each corresponding to a scan line of the pattern to be checked. In this way, the location memory 22 receives local images each containing 5x5 pixels and from the image to be checked, the location memory 23, local images each containing 5x5 pixels are cut out and are cut out of the insensitive image area lying within the boundary line, and the location memory 24 local images, each with 5x5 pixels and from

1*

insensitive area lying outside the borderline are cut out, successively fed. Fig. 3 shows an embodiment of the device in Fig. used shift register groups. Thereby η shift registers are connected in series and give the individual shift registers Output signals 26.1, 26.2, ... and 26.n. As FIG. 3 shows, the first shift register receives an input signal 25 fed.

Fig. 4 shows a circuit part for cutting out a local Image from the image of the designated pattern (namely the reference pattern). In general, it is between the one to be examined Pattern and the reference pattern an inevitable misalignment available. Accordingly, if a site image cut out from the image of the reference pattern must be a local one To obtain reference image that corresponds to the local image of the location memory 22, the location image that from the reference image is cut out to be larger than the location image of the location memory 22 by an amount corresponding to the alignment error, so that a part of the location image cut out from the reference image corresponds to the location image of the location memory 22. Fig. 4 shows a case where the alignment error in each of the X and Y directions is at most + 1 pixel.

A location image in each of the location memories 22 to 24 contains 5x5 Pixel. In a case where the above location image with respect to the corresponding reference location image by + 1 pixel in each case in X- and Can be shifted in the Y direction, a local reference image, which comprises 7x7 pixels, must be cut from the reference image as Fig. 4 shows. 4 shows a reference image signal 27 which is transmitted to a location memory 29 comprising 7 × 7 pixels a shift register group 28 is applied, which consists of seven shift registers, each one scanning line of the correspond to the sample to be tested. In addition, the reference image signal 27 from the reference image memory 28 of FIG. 1 becomes synchronous with the scanning of the detector 1 read out so that

/ is

the center pixel d. of location memory 29 and the center pixel a_-, the location memory 22, if the sample to be tested is accurate is aligned with respect to the reference pattern (which means that the alignment error is zero), corresponding parts of the to the test sample and the reference sample.

5 shows the circuit configuration of the error extraction circuit 10, which assesses an error by means of the location images of the location memories 22, 23, 24 and 29, in detail. In Fig. 5, symbols a .., b .. and c .. (where i = 1, 2, 3, 4 and 5 assume) the output of each pixel of the location memory 22, the output of each pixel of the location memory 23 and the Output of each pixel of the location memory 24 again. Symbols d. _at . . (where i = 1, 2, 3, 4 and 5; j = 1, 2, 3, 4 and 5; 1 = 0, 1 and 2; k = 01 and 2) give the output of each pixel of the location memory 29 at. Values of 1 = 0.1 and 2 become values of i = 1, 2, 3, 4 and 5 and values of k = 0, 1 and 2 become values of j = 1.2, 3, 4 and 5 added up. The output a .. and the output d. ₊₁ - _{+ k} are supplied to an exclusive OR circuit 30. This logical processing means that the location image obtained from the location memory 22 is moved on the location image obtained from the location memory 29; and an exclusive OR operation is performed on a pair of pixels of the same position to provide the exclusive ORing result for each pair of pixels from the exclusive OR circuit 30. In addition, the output of each pixel of the local insensitivity area, which is supplied by the location memory 23, is applied to a NOT circuit 31, the output of which is applied to an AND circuit 31 together with the output of the exclusive OR circuit 30. In the same way, the output of a respective pixel of the local insensitivity image area, which is obtained from the location memory 24, is applied to a NOT circuit 32, the output of which is applied to an AND circuit 34 together with the output of the exclusive OR circuit 30. This is done by the AND circuit

A signal is supplied which indicates whether the image of the location memory 22 with a 5 × 5 pixel reference location image, if the insensitivity range of the location memory 23 is neglected, coincides or not. In the same way, a signal supplied by the AND circuit 34 indicates whether
the location image of the location memory 22 with a 5x5 pixel reference location image if the insensitivity area
of the location memory 24 is neglected, matches or not. The output of the AND circuit 33 is applied to a corresponding one of the OR circuits 35 in accordance with each of the values of (f and k, and the output of the AND circuit 34 is applied to a corresponding one in accordance with the respective values of C and k
the OR circuits 36 supplied.

That is, 5 × 5 outputs of 5 × 5 pixels of a location image given by the output of the AND circuit 33 or 34 are fed to one of the OR gates 35 or 36. The outputs of the OR circuits 35 are supplied to an AND circuit 37, and the outputs of the OR circuits 36 are supplied to an AND circuit 38. The outputs of the AND circuits 3 7
and 38 are fed to an OR circuit 39 which outputs an error signal 11. According to this circuit structure, one of the outputs E ^> of the OR circuit 35 indicates whether or not the test location image of the location memory 22 coincides with a corresponding local reference image comprising 5 × 5 pixels in a case where the test pattern of a reference pattern in the X direction by (£ - 1 pixel and in the Y direction
deviates by (k − 1) pixels if the insensitive area of the location memory 23 lying within the boundary line is removed from these location images. In addition, the output is F-.
one of the OR circuits 36 to determine whether the local image to be checked of the local memory 22 with a corresponding, 5x5
Local reference image comprising pixels coincides in the above case or not if the insensitivity area of the location memory 24 lying outside the boundary line is removed from these location images. If at least one of the

Outputs E ^, (where 1 = 0, 1 and 2 and k = 0, 1 and 2), Indicates coincidence, the output of the AND circuit 37 becomes "0" level. If all outputs from E », mismatch indicate, the output of the AND circuit 37 becomes "1" level. If at least one of the outputs F ^, match indicates, the output of the AND circuit 38 becomes "0" level.

If all outputs indicate F-, mismatch, the takes The output of the AND circuit 38 has "1" level. If both outputs of AND circuits 37 and 38 indicate a match, picks up the output of the OR circuit 39 indicates "0" level, thus indicating that there is no error. If at least one of the Outputs 37 and 38 indicates disagreement, the output of the OR circuit assumes "1" level, thus indicating that a Error is present.

Let us now consider how the present invention is applied to an inspection image and a reference image shown in FIG Fig. 6 are shown. Reference numerals a to g denote local ones Areas of the image to be inspected. 7 shows how each of the local areas a to g is stored in the local memories 23 and 24 represents. According to the invention in the local areas b, d, e, f and e are extracted as errors. Irregularities in the local areas a and c, however, are not considered to be errors, as these are irregularities can be viewed as quantization errors.

As the above explanation shows, according to the invention, when the patterns to be examined are complicated. Defects in the patterns without modifying the structure of a test device and an error extraction method. The above description uses a drawn pattern as a reference pattern. the However, the invention is also applicable to cases where the image

of a body having the same shape as the sample to be inspected is generated by an image pickup device and this image as Reference image is used.

To carry out the invention it is also not necessary that an image signal indicating a reference pattern is always at the same time and outputted from an image pickup device an image signal indicating a pattern to be inspected and converted into binary image signals are converted, and that at the same time local images extracted from these image signals for mutual comparison will. Namely, the present invention is also applicable to, for example, a case where a plurality of The image signal representing patterns of the same shape is previously stored in a memory and the image signal read out from the memory is compared in each case with the remaining patterns representing image signals.

Claims (6)

Claims 1. Procedure for testing a sample, being two each a reference pattern and a pattern to be tested corresponding images converted into binary image signals from the binary Image signals local binary image signals or local images cut out of the images and then converted into local ones binary image signals are converted, and the local binary image signals are compared with one another, to capture the area of an image from an error that differs in its logical value from a corresponding one Area of the other image is different, characterized by the following steps: - Define insensitive areas on both sides a boundary line of a desired local binary image, - Cut out one of the local binary images so that one area of the local binary image coincides with the other local binary image corresponds if the misalignment between the reference pattern and the one to be checked Pattern corresponding images is within a tolerable range, 81-B 700-02-Atlei - Comparison of the remaining part with the exception of the insensitive areas of the other local binary image with the remaining part with the exception of the insensitive areas of a corresponding part of the one local binary image at positions where a part of one local binary image corresponds to the other local binary image to generate an error signal if the remainder of the other local binary image not with the remaining part of the corresponding area of the one local binary image coincides at all of these positions. 2. The method according to claim 1,
characterized, that the insensitive areas on broad sides of the Boundary line of the desired local binary image by means of a logic circuit for enlarging and contracting the desired one local binary image. 3. The method according to claim 1,
characterized, that the local binary images are cut out so that the one local binary image by an amount that is tolerable Alignment error area is larger than the other local binary image. 4. The method according to claim 1,
characterized, that both local binary images are cut out so that they are larger than the tolerable range of misregistration . 5. The method according to claim!
characterized, that a picture belonging to one area among several in the too 8612233 areas to be tested corresponds to, respectively have the same shape used as the image of the reference pattern. 6. The method according to claim 1,
characterized, that at least two types of images, each corresponding to the reference pattern and correspond to the pattern to be checked, are temporarily stored in a memory and that a local Image is cut out of the one image that is read out from the memory.