DE3584058D1 - Funktionelle, redundante logiknetzwerkarchitekturen mit logikauswahlmitteln. - Google Patents

Funktionelle, redundante logiknetzwerkarchitekturen mit logikauswahlmitteln.

Info

Publication number
DE3584058D1
DE3584058D1 DE8585901763T DE3584058T DE3584058D1 DE 3584058 D1 DE3584058 D1 DE 3584058D1 DE 8585901763 T DE8585901763 T DE 8585901763T DE 3584058 T DE3584058 T DE 3584058T DE 3584058 D1 DE3584058 D1 DE 3584058D1
Authority
DE
Germany
Prior art keywords
logic
functional
selection means
network architecture
redundant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585901763T
Other languages
English (en)
Inventor
Donald W Moore
Rik Verstraete
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aerojet Rocketdyne Inc
University of California
Original Assignee
University of California
Aerojet General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of California, Aerojet General Corp filed Critical University of California
Application granted granted Critical
Publication of DE3584058D1 publication Critical patent/DE3584058D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
DE8585901763T 1984-03-15 1985-03-14 Funktionelle, redundante logiknetzwerkarchitekturen mit logikauswahlmitteln. Expired - Lifetime DE3584058D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/589,943 US4551815A (en) 1983-12-12 1984-03-15 Functionally redundant logic network architectures with logic selection means
PCT/US1985/000435 WO1985004296A1 (en) 1984-03-15 1985-03-14 Functionally redundant logic network architectures with logic selection means

Publications (1)

Publication Number Publication Date
DE3584058D1 true DE3584058D1 (de) 1991-10-17

Family

ID=24360215

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585901763T Expired - Lifetime DE3584058D1 (de) 1984-03-15 1985-03-14 Funktionelle, redundante logiknetzwerkarchitekturen mit logikauswahlmitteln.

Country Status (5)

Country Link
US (1) US4551815A (de)
EP (1) EP0173744B1 (de)
AU (1) AU4112685A (de)
DE (1) DE3584058D1 (de)
WO (1) WO1985004296A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
JPS6124250A (ja) * 1984-07-13 1986-02-01 Nippon Gakki Seizo Kk 半導体集積回路装置
US4697241A (en) * 1985-03-01 1987-09-29 Simulog, Inc. Hardware logic simulator
US4742252A (en) * 1985-03-29 1988-05-03 Advanced Micro Devices, Inc. Multiple array customizable logic device
US5225719A (en) * 1985-03-29 1993-07-06 Advanced Micro Devices, Inc. Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix
US4792909A (en) * 1986-04-07 1988-12-20 Xerox Corporation Boolean logic layout generator
US4723242A (en) * 1986-06-27 1988-02-02 Sperry Corporation Digital adaptive voting
US4821173A (en) * 1986-06-30 1989-04-11 Motorola, Inc. Wired "OR" bus evaluator for logic simulation
US4816999A (en) * 1987-05-20 1989-03-28 International Business Machines Corporation Method of detecting constants and removing redundant connections in a logic network
FR2626422B1 (fr) * 1988-01-27 1994-04-15 Elf Aquitaine Ste Nale Circuit logique a structure programmable, procede de cablage d'un arbre et dispositif de mise en oeuvre du procede de cablage
US4937475B1 (en) * 1988-09-19 1994-03-29 Massachusetts Inst Technology Laser programmable integrated circuit
US5055712A (en) * 1990-04-05 1991-10-08 National Semiconductor Corp. Register file with programmable control, decode and/or data manipulation
US5291612A (en) * 1991-02-11 1994-03-01 University Technologies International System for evaluating boolean expressions using total differential generating tree structured processing elements controlled by partial subfunction differentials
WO1994022142A1 (en) * 1993-03-17 1994-09-29 Zycad Corporation Random access memory (ram) based configurable arrays
US5495589A (en) * 1993-12-23 1996-02-27 Unisys Corporation Architecture for smart control of bi-directional transfer of data
US5450578A (en) * 1993-12-23 1995-09-12 Unisys Corporation Method and apparatus for automatically routing around faults within an interconnect system
US5548715A (en) * 1994-06-10 1996-08-20 International Business Machines Corporation Analysis of untestable faults using discrete node sets
US5999961A (en) * 1997-09-15 1999-12-07 California Institute Of Technology Parallel prefix operations in asynchronous processors
US6374144B1 (en) * 1998-12-22 2002-04-16 Varian Semiconductor Equipment Associates, Inc. Method and apparatus for controlling a system using hierarchical state machines
US7035886B1 (en) * 2002-03-28 2006-04-25 Cypress Semiconductor Corporation Re-configurable combinational logic device
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US20120030451A1 (en) * 2010-07-28 2012-02-02 Broadcom Corporation Parallel and long adaptive instruction set architecture
US10824952B2 (en) * 2014-09-22 2020-11-03 International Business Machines Corporation Reconfigurable array processor for pattern matching
US9891912B2 (en) 2014-10-31 2018-02-13 International Business Machines Corporation Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE631780A (de) * 1962-05-09
US3291974A (en) * 1964-12-14 1966-12-13 Sperry Rand Corp Planar function generator using modulo 2 unprimed canonical form logic
US3619583A (en) * 1968-10-11 1971-11-09 Bell Telephone Labor Inc Multiple function programmable arrays
DE2951946A1 (de) * 1979-12-22 1981-07-02 Ibm Deutschland Gmbh, 7000 Stuttgart Fehlererkennungs- und -korrektureinrichtung fuer eine logische anordnung
US4357678A (en) * 1979-12-26 1982-11-02 International Business Machines Corporation Programmable sequential logic array mechanism
DE3015992A1 (de) * 1980-04-25 1981-11-05 Ibm Deutschland Gmbh, 7000 Stuttgart Programmierbare logische anordnung
JPS5916050A (ja) * 1982-07-16 1984-01-27 Nec Corp ダイナミツクゲ−トアレイ
DE3342354A1 (de) * 1983-04-14 1984-10-18 Control Data Corp., Minneapolis, Minn. Weich programmierbare logikanordnung

Also Published As

Publication number Publication date
AU4112685A (en) 1985-10-11
EP0173744A4 (de) 1988-04-27
WO1985004296A1 (en) 1985-09-26
US4551815A (en) 1985-11-05
EP0173744A1 (de) 1986-03-12
EP0173744B1 (de) 1991-09-11

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Legal Events

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