DE3486152T2 - Funktionsmässig redundante logische netzwerkarchitekturen. - Google Patents
Funktionsmässig redundante logische netzwerkarchitekturen.Info
- Publication number
- DE3486152T2 DE3486152T2 DE85900405T DE3486152T DE3486152T2 DE 3486152 T2 DE3486152 T2 DE 3486152T2 DE 85900405 T DE85900405 T DE 85900405T DE 3486152 T DE3486152 T DE 3486152T DE 3486152 T2 DE3486152 T2 DE 3486152T2
- Authority
- DE
- Germany
- Prior art keywords
- network architecture
- logical network
- redundant logical
- functional redundant
- functional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/560,109 US4551814A (en) | 1983-12-12 | 1983-12-12 | Functionally redundant logic network architectures |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3486152D1 DE3486152D1 (de) | 1993-07-01 |
DE3486152T2 true DE3486152T2 (de) | 1994-01-05 |
Family
ID=24236412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE85900405T Expired - Lifetime DE3486152T2 (de) | 1983-12-12 | 1984-12-10 | Funktionsmässig redundante logische netzwerkarchitekturen. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4551814A (de) |
EP (1) | EP0165975B1 (de) |
JP (1) | JPS61501121A (de) |
AU (1) | AU3743585A (de) |
DE (1) | DE3486152T2 (de) |
WO (1) | WO1985002730A1 (de) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE34363E (en) * | 1984-03-12 | 1993-08-31 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4870302A (en) * | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4697241A (en) * | 1985-03-01 | 1987-09-29 | Simulog, Inc. | Hardware logic simulator |
US4644353A (en) * | 1985-06-17 | 1987-02-17 | Intersil, Inc. | Programmable interface |
GB2180382B (en) * | 1985-09-11 | 1989-11-22 | Pilkington Micro Electronics | Semi-conductor integrated circuits/systems |
US4723242A (en) * | 1986-06-27 | 1988-02-02 | Sperry Corporation | Digital adaptive voting |
US4816999A (en) * | 1987-05-20 | 1989-03-28 | International Business Machines Corporation | Method of detecting constants and removing redundant connections in a logic network |
US4839851A (en) * | 1987-07-13 | 1989-06-13 | Idaho Research Foundation, Inc. | Programmable data path device |
US4800302A (en) * | 1987-07-17 | 1989-01-24 | Trw Inc. | Redundancy system with distributed mapping |
FR2626422B1 (fr) * | 1988-01-27 | 1994-04-15 | Elf Aquitaine Ste Nale | Circuit logique a structure programmable, procede de cablage d'un arbre et dispositif de mise en oeuvre du procede de cablage |
US4899067A (en) * | 1988-07-22 | 1990-02-06 | Altera Corporation | Programmable logic devices with spare circuits for use in replacing defective circuits |
US5416719A (en) * | 1992-12-17 | 1995-05-16 | Vlsi Technology, Inc. | Computerized generation of truth tables for sequential and combinatorial cells |
JPH06250994A (ja) * | 1993-02-22 | 1994-09-09 | Sunao Shibata | 演算装置 |
CA2158467A1 (en) * | 1993-03-17 | 1994-09-29 | Richard D. Freeman | Random access memory (ram) based configurable arrays |
CH688425A5 (fr) * | 1993-05-24 | 1997-09-15 | Suisse Electronique Microtech | Circuit électronique organisé en réseau matriciel de cellules. |
US5450578A (en) * | 1993-12-23 | 1995-09-12 | Unisys Corporation | Method and apparatus for automatically routing around faults within an interconnect system |
US5495589A (en) * | 1993-12-23 | 1996-02-27 | Unisys Corporation | Architecture for smart control of bi-directional transfer of data |
US5828578A (en) * | 1995-11-29 | 1998-10-27 | S3 Incorporated | Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield |
US5825199A (en) * | 1997-01-30 | 1998-10-20 | Vlsi Technology, Inc. | Reprogrammable state machine and method therefor |
US6091258A (en) * | 1997-02-05 | 2000-07-18 | Altera Corporation | Redundancy circuitry for logic circuits |
US6034536A (en) * | 1997-02-05 | 2000-03-07 | Altera Corporation | Redundancy circuitry for logic circuits |
EP0983549B1 (de) | 1997-05-23 | 2001-12-12 | Altera Corporation (a Delaware Corporation) | Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisen |
US6201404B1 (en) | 1998-07-14 | 2001-03-13 | Altera Corporation | Programmable logic device with redundant circuitry |
JP2000276210A (ja) * | 1999-01-21 | 2000-10-06 | Giichi Kuze | ゲートアレイ構成の読み出し専用のシーケンス・コントローラ |
FR2846491B1 (fr) * | 2002-10-25 | 2005-08-12 | Atmel Corp | Architecture comprenant des cellules de remplacement pour reparer des erreurs de conception dans des circuits integres apres fabrication |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US10824952B2 (en) * | 2014-09-22 | 2020-11-03 | International Business Machines Corporation | Reconfigurable array processor for pattern matching |
US9891912B2 (en) | 2014-10-31 | 2018-02-13 | International Business Machines Corporation | Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements |
DE102016118000B4 (de) | 2016-09-23 | 2018-12-20 | Infineon Technologies Ag | Programmierbare logikschaltung und verfahren zur implementierung einer booleschen funktion |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE631780A (de) * | 1962-05-09 | |||
US3291974A (en) * | 1964-12-14 | 1966-12-13 | Sperry Rand Corp | Planar function generator using modulo 2 unprimed canonical form logic |
US3619583A (en) * | 1968-10-11 | 1971-11-09 | Bell Telephone Labor Inc | Multiple function programmable arrays |
JPS5159518A (ja) * | 1974-11-18 | 1976-05-24 | Gen Corp | Fukushakirokuyoshi |
JPS5219100A (en) * | 1975-08-04 | 1977-01-14 | Iwata Shoji Kk | Automatic perfume exhalation type name-plate |
SE419421B (sv) * | 1979-03-16 | 1981-08-03 | Ove Larson | Bojlig arm i synnerhet robotarm |
JPS5626531A (en) * | 1979-08-08 | 1981-03-14 | Hitachi Ltd | Method and apparatus for dry type flue gas desufurization |
DE2951946A1 (de) * | 1979-12-22 | 1981-07-02 | Ibm Deutschland Gmbh, 7000 Stuttgart | Fehlererkennungs- und -korrektureinrichtung fuer eine logische anordnung |
DE3015992A1 (de) * | 1980-04-25 | 1981-11-05 | Ibm Deutschland Gmbh, 7000 Stuttgart | Programmierbare logische anordnung |
DE3342354A1 (de) * | 1983-04-14 | 1984-10-18 | Control Data Corp., Minneapolis, Minn. | Weich programmierbare logikanordnung |
-
1983
- 1983-12-12 US US06/560,109 patent/US4551814A/en not_active Expired - Lifetime
-
1984
- 1984-12-10 JP JP60500222A patent/JPS61501121A/ja not_active Expired - Lifetime
- 1984-12-10 AU AU37435/85A patent/AU3743585A/en not_active Abandoned
- 1984-12-10 DE DE85900405T patent/DE3486152T2/de not_active Expired - Lifetime
- 1984-12-10 WO PCT/US1984/002031 patent/WO1985002730A1/en active IP Right Grant
- 1984-12-10 EP EP85900405A patent/EP0165975B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0165975A4 (de) | 1988-04-27 |
US4551814A (en) | 1985-11-05 |
JPS61501121A (ja) | 1986-05-29 |
AU3743585A (en) | 1985-06-26 |
DE3486152D1 (de) | 1993-07-01 |
EP0165975B1 (de) | 1993-05-26 |
WO1985002730A1 (en) | 1985-06-20 |
EP0165975A1 (de) | 1986-01-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: SAMSUNG ELECTRONICS CO. LTD., SUWON, KYUNGKI, KR |
|
8381 | Inventor (new situation) |
Free format text: MOORE, DONALD W., LOS ANGELES, CALIF., US |