DE3583674D1 - PROGRAMMABLE LOGICAL ARRANGEMENT WITH RELATIVE FIELD EFFECT TRANSISTORS. - Google Patents
PROGRAMMABLE LOGICAL ARRANGEMENT WITH RELATIVE FIELD EFFECT TRANSISTORS.Info
- Publication number
- DE3583674D1 DE3583674D1 DE8585201979T DE3583674T DE3583674D1 DE 3583674 D1 DE3583674 D1 DE 3583674D1 DE 8585201979 T DE8585201979 T DE 8585201979T DE 3583674 T DE3583674 T DE 3583674T DE 3583674 D1 DE3583674 D1 DE 3583674D1
- Authority
- DE
- Germany
- Prior art keywords
- field effect
- effect transistors
- logical arrangement
- programmable logical
- relative field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
- H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/684,638 US4636661A (en) | 1984-12-21 | 1984-12-21 | Ratioless FET programmable logic array |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3583674D1 true DE3583674D1 (en) | 1991-09-05 |
Family
ID=24748911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585201979T Expired - Lifetime DE3583674D1 (en) | 1984-12-21 | 1985-11-27 | PROGRAMMABLE LOGICAL ARRANGEMENT WITH RELATIVE FIELD EFFECT TRANSISTORS. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4636661A (en) |
EP (1) | EP0188834B1 (en) |
JP (1) | JPH065818B2 (en) |
DE (1) | DE3583674D1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1257343A (en) * | 1986-07-02 | 1989-07-11 | Robert C. Rose | Self-timed programmable logic array with pre-charge circuit |
US5083083A (en) * | 1986-09-19 | 1992-01-21 | Actel Corporation | Testability architecture and techniques for programmable interconnect architecture |
US5309091A (en) * | 1986-09-19 | 1994-05-03 | Actel Corporation | Testability architecture and techniques for programmable interconnect architecture |
US5544078A (en) * | 1988-06-17 | 1996-08-06 | Dallas Semiconductor Corporation | Timekeeping comparison circuitry and dual storage memory cells to detect alarms |
US4959646A (en) * | 1988-06-17 | 1990-09-25 | Dallas Semiconductor Corporation | Dynamic PLA timing circuit |
KR920004385B1 (en) * | 1989-11-18 | 1992-06-04 | 삼성전자 주식회사 | Chain free-charge circuit an power supply |
US5579206A (en) * | 1993-07-16 | 1996-11-26 | Dallas Semiconductor Corporation | Enhanced low profile sockets and module systems |
US5528463A (en) * | 1993-07-16 | 1996-06-18 | Dallas Semiconductor Corp. | Low profile sockets and modules for surface mountable applications |
WO1997014220A2 (en) * | 1995-10-13 | 1997-04-17 | Philips Electronics N.V. | Electrically reprogrammable, reduced power, programmable logic device circuit |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3866186A (en) * | 1972-05-16 | 1975-02-11 | Tokyo Shibaura Electric Co | Logic circuit arrangement employing insulated gate field effect transistors |
US4040015A (en) * | 1974-04-16 | 1977-08-02 | Hitachi, Ltd. | Complementary mos logic circuit |
DE2544434A1 (en) * | 1975-10-04 | 1977-04-14 | Philips Patentverwaltung | Rapid switching LSI circuitry - has clock pulses to consecutive FET stages mutually inverse for binary signal processing |
US4291247A (en) * | 1977-12-14 | 1981-09-22 | Bell Telephone Laboratories, Incorporated | Multistage logic circuit arrangement |
DE2853517A1 (en) * | 1977-12-14 | 1979-06-21 | Western Electric Co | MULTI-LEVEL LOGIC CIRCUIT |
US4295064A (en) * | 1978-06-30 | 1981-10-13 | International Business Machines Corporation | Logic and array logic driving circuits |
US4346310A (en) * | 1980-05-09 | 1982-08-24 | Motorola, Inc. | Voltage booster circuit |
JPS5897922A (en) * | 1981-12-07 | 1983-06-10 | Toshiba Corp | And and or circuit |
US4577190A (en) * | 1983-04-11 | 1986-03-18 | At&T Bell Laboratories | Programmed logic array with auxiliary pull-up means to increase precharging speed |
US4611133A (en) * | 1983-05-12 | 1986-09-09 | Codex Corporation | High speed fully precharged programmable logic array |
JPS60233933A (en) * | 1984-05-04 | 1985-11-20 | Nec Corp | Programmable logical array |
-
1984
- 1984-12-21 US US06/684,638 patent/US4636661A/en not_active Expired - Fee Related
-
1985
- 1985-11-27 DE DE8585201979T patent/DE3583674D1/en not_active Expired - Lifetime
- 1985-11-27 EP EP85201979A patent/EP0188834B1/en not_active Expired
- 1985-12-18 JP JP60285403A patent/JPH065818B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS61154315A (en) | 1986-07-14 |
JPH065818B2 (en) | 1994-01-19 |
EP0188834B1 (en) | 1991-07-31 |
EP0188834A3 (en) | 1988-02-10 |
EP0188834A2 (en) | 1986-07-30 |
US4636661A (en) | 1987-01-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL |
|
8339 | Ceased/non-payment of the annual fee |