WO1997014220A2

WO1997014220A2 - Electrically reprogrammable, reduced power, programmable logic device circuit

Info

Publication number: WO1997014220A2
Application number: PCT/IB1996/001041
Authority: WO
Inventors: Ronald L. Cline
Original assignee: Philips Electronics N.V.; Philips Norden Ab
Priority date: 1995-10-13
Filing date: 1996-10-03
Publication date: 1997-04-17
Also published as: WO1997014220A3

Abstract

Large multi-input CMOS logic gates may be formed by a sequence of alternating CMOS NAND and NOR logic gates. The sequence of alternating gates may be compactly laid out in an integrated circuit to form arrays of functional AND or OR gates useful in PLAS. These arrays of CMOS gates consume low power and have response times suitable for integrated circuits. These arrays may be programmed by EEPROM or EPROM transistors or in the alternative, binary latches may be used to store information determinative of the desired programming.

Description

Electrically reprogrammable, reduced power, programmable logic device circuit.

FIELD OF THE INVENΗON

The present invention relates to integrated circuits and, more particularly, programmable logic arrays (PLAs).

BACKGROUND OF THE INVENTION

Any logic function can be reduced to what is called the "sum of the products" of the input variables. Each product term is the logically ANDed combination of input variables. The "sum" of these product terms are the logically ORed combination of the product terms. Any logic function can be reduced to this form. Based on the sum of products idea, programmable logic arrays (PLAs) are integrated circuit devices which permit a user to implement any logic function by programming an array of AND gates and an array of OR gates. The two arrays of AND and OR gates are coupled. The programming of the array of AND gates determines the product terms of the function; the programming of the array of OR gates selects which product terms will be ORed together.

FIG. 1 is a diagrammatic illustration of a typical PLA. The PLA has j number of input terminals which are connected to an array 10 of AND logic gates. The array 10 is, in turn, coupled to an array 12 of OR logic gates, k number of output terminals of the OR logic gate array 12 are the output terminals of the PLA. In the exemplary device of FIG. 1, each of the input terminals Ii-I: is coupled to a set of inverters 16 so that each input signal gives rise to true and complementary input signals. These input signals are carried on true, and complementary input signal lines 14 and 15, respectively. Each of the true and complementary input signal lines is connectable to each of n number of AND gates 11, which form the array 10 of AND gates. Each AND gate 11 generates a product term of input variables I_j-L and their complements. The particular variables selected for each product term are determined by the programming of the connections of the input signal lines 14, 15 to the AND gates 11 (i.e., whether an AND gate 11 is connected to a particular signal line).

The output terminals of the AND gates 11 are each, in turn, connectable to an input terminal of each of the OR gates 13 of the array 12. Each connection of an input terminal of an OR gate 13 to an output terminal of an AND gate 11 is programmable. If no connection is made to a particular AND gate 11 , then that particular product term is missing from the sum of products of the OR gate 13.

Thus, the output signal of each OR gate 13 is independently programmable. Each output function may be the sum of up to k product terms, each product term having up to 64 input variables, true and complementary. It should be noted that each of the AND gates 11 and OR gates 13 is a large multi-input logic gate. The AND gate 11 having up to j input terminals and the OR gate 13 having up to k input terminals.

A typical way of programming the PLA is through the use of masks which make the programmable connections desired by the user of the PLA. The programming of the PLA is done by the manufacturer of the PLA according to the user's specifications. Another common form of programming PLAs is the use of fuses for the programmable connection. Fuses permit the user to program the PLA by "blowing" the fuse to disconnect the undesired input connections to the logic gates 11 and 13. The remaining connections determine the output functions of the PLA.

A common semiconductor technology for PLAs is bipolar technology in which bipolar transistor circuits implement the PLA in an integrated circuit device. PLA's have been implemented in MOS technology also. MOS transistors of one polarity, such as N- channel or NMOS transistors, are used in the integrated circuit. Being smaller, MOS transistors permit more integration and complexity than do bipolar transistors at comparable costs. As in bipolar technology, MOS transistors act as passive load devices which allow a DC current path for the MOS PLA. While not as high as in a bipolar PLA, the MOS PLA still has fairly high power consumption.

A technology with very low power consumption is complementary MOS, or CMOS or more generally complementary insulated gate field effect transistor (IGFET) technology. In IGFET/CMOS technology, a typical logic circuit has an output node located between a pair of active transistors of opposite channel polarity. Each gate of the transistor pair is connected to the same input signal so that a signal turning one transistor on, turns the other off. There is never a DC power path and power consumption is very low in IGFET/CMOS circuits.

However, PLAs heretofore have not fully been implemented in complementary IGFET/CMOS technology. In prior art devices the input and output buffer circuits are typically complementary true IGFET/CMOS circuits, but the arrays of AND and OR gates remain single polarity MOS (typically NMOS) transistor circuits with passive loads discussed above.

An examination of a large multi-input complementary IGFET/CMOS logic gate reveals why the gate arrays remain in single polarity MOS, rather than complementary IGFET/MOS (CMOS) technology. FIG. 2 shows a circuit diagram of a 16 input (actually 32- input, since each input signal has its complementary signal) complementary IGFET/CMOS NAND gate which would be used to implement an AND gate 11 in the array 10. The circuit in FIG. 2 has two groups of transistors, one group 19 of transistors with channels of one polarity and the second group 20 of transistors with channels of opposite polarity. Each transistor of one group is paired with a transistor in the second group so that the gates of the paired transistors receive the same input signal. To show that the transistors of the group 20 have channel regions of opposite polarity to that of the transistors in group 19, the transistors of group 20 have an additional circular symbol representing inversion with the normal symbol of a MOS transistor gate. From this view of a complementary IGFET/CMOS NAND gate it can be appreciated that the problems of laying out such a circuit in the semiconductor substrate of an integrated circuit are difficult. Each pair of transistors in groups 19 and 20 are connected together. Hence the large number of lines for layout in a large input complementary IGFET/CMOS logic gate becomes a problem. As the number of input lines increases, the problem correspondingly becomes more and more complicated.

A second problem is that the operational response time of the complementary IGFET/CMOS NAND gate shown in FIG. 2 is very slow. The string of transistors in group 19 have a very large resistance. Combined with the typical capacitance of such a circuit, the resistance-capacitance (RC) time constant of the circuit becomes large, and the performance of the circuit is unacceptable.

A large multi-input complementary IGFET/CMOS NOR gate has the same problems. With these difficulties of layout and performance for a single large multi-input complementary IGFET/CMOS logic gate, the problem of designing an array of these logic gates for a PLA has prevented the creation of a completely complementary IGFET/CMOS PLA.

The present invention solves, or substantially mitigates, these problems. With the present invention, arrays of true complementary IGFET/CMOS AND and OR logic gates are possible. This permits PLAs with very low power consumption and acceptable response times. SUMMARY OF THE INVENTION

The present invention provides for an integrated circuit comprising a plurality of complementary IGFET/CMOS NAND and NOR gates. Each complementary IGFET/CMOS logic gate has at least two pairs of opposite polarity MOS transistors coupled about an output node between two voltage terminals. The gates of each transistor pair are coupled to an input terminal. The input terminal of a complementary IGFET/CMOS NAND logic gate is connected to an output node of a complementary IGFET/CMOS NOR logic gate and the input terminal of a complementary IGFET/CMOS NOR logic gate is connected to an output node of a complementary IGFET/CMOS NAND logic gate, whereby an alternating sequence of complementary IGFET/CMOS NAND and NOR gates is connected serially to operate as a multi-input AND or OR gate.

The present invention also provides for an integrated circuit PLA having an array of functional AND logic gates coupled to an array of functional OR logic gates, where at least one of the arrays has its functional logic gates comprised of a sequence of alternating complementary IGFET/CMOS NAND and NOR gates, and whereby the array is implemented in complementary IGFET/CMOS.

The present invention further provides for an integrated circuit PLA having an array of functional AND logic gates coupled to an array of functional OR logic gates, where each functional AND and OR gate comprises a plurality of serially connected, alternating complementary IGFET/CMOS NAND and NOR gates. Each NAND and NOR gate has at least one programmable input terminal, a matrix of input signal lines and fixed voltage lines over the complementary IGFET/CMOS NAND and NOR gates, and whereby each NAND and NOR gate may be programmed by connecting the programmable input terminal to one of the matrix of lines. Finally, the present invention provides for the integrated circuit PLA formed from an alternating sequence of serially connected complementary IGFET/CMOS NAND and NOR gates to operate as a multi-input AND or OR gate, having MOS transistors which operatively couple the input terminals at the complementary IGFET/CMOS NAND and NOR logic gates to selected input signal terminals. The MOS transistors perform the coupling functions by charge stored above the channel regions of the transistors to program the input signals to the complementary IGFET/CMOS NAND and NOR logic gates.

In this manner an integrated circuit PLA is provided which may have its AND gate array input terminals programmed by the charge storage MOS transistors. Additionally, the OR gate array of the PLA may be programmably coupled to the output terminals of the AND gate array by these charge storage MOS transistors.

In another embodiment of the invention, EPROM's or EEPROM's may be used as the charge storage MOS transistors. In a further embodiment, the charge storage elements (transistors) are replaced with binary latches which hold the information determinative of which signal is coupled to the logic gate.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and features of the present invention will become apparent from the following detailed description considered in connection with the accompanying drawings which disclose several embodiments of the present invention. It should be understood, however, that the drawings are designed for the purpose of illustration only and not as a definition of the limits of the invention.

FIG. 1 is a block diagram of a typical programmable logic array (PLA); FIG. 2 is a circuit diagram of a large multi-input CMOS NAND logic gate;

FIG. 3A shows a sequence of alternating CMOS two-input NAND and NOR gates of the present invention;

FIG. 3B shows a sequence of alternating CMOS three-input NAND and NOR gates of the present invention;

FIG. 4A is a schematic circuit diagram of a three-input CMOS NAND gate;

FIG. 4B is a schematic circuit diagram of a three-input CMOS NOR gate;

FIG. 5A is a top view of two layers of conducting lines over a semiconductor substrate having two adjacent CMOS OR gates according to the present invention;

FIG. 5B is a top view of the underlying CMOS OR gates as laid out in a semiconductor substrate in the present invention;

FIG. 6A is a schematic diagram of a two-input CMOS NAND gate with its programmable input terminal connected to EEPROM transistors, each of which can couple the input terminal to a different input signal terminal;

FIG. 6B shows the same configuration as Fig. 6A with a CMOS NAND gate having three inputs; and FIG. 7 is a schematic diagram of another embodiment of the electrically programmable PLA according to the invention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS FIG. 3A shows one embodiment of the present invention. A sequence of alternating NAND gates 21 and NOR gates 22 is used in place of the large multi-input AND or OR gate of the prior art. The sequence of alternating logic gates starts with a NAND gate followed by a NOR gate and so on. With the input signals to the NOR gates inverted, a sequence ending in a NOR gate is equivalent to a multi-input AND gate or a multi-input NOR gate with inverted input signals. A sequence ending in a NAND gate is equivalent to a multi-input NAND gate or an OR gate with inverted input signals.

The sequence of alternating NAND and NOR logic gates could start with a NOR gate. In that case, with the input signals to the NAND gates inverted, the sequence is equivalent to a multi-input OR gate or a multi-input NAND gate with input signals inverted if the sequence ends in a NAND gate. If the sequence ends in a NOR gate, the sequence is equivalent to a multi-input NOR gate or a multi-input AND gate with inverted input signals. All of these relationships follow from Demorgan's Theorem.

The polarity of any signal can be changed simply by an inverter. For example, an inverter at the end of a sequence of alternating gates can change the equivalent multi-input NOR gate into an OR gate. Thus, the present invention makes it possible to duplicate the logic function of any large multi-input AND or OR (and NAND or NOR) gate.

With the embodiment disclosed with reference to FIGS. 3A and 3B, the sequence starts with a NAND gate. The NAND gate is faster than the NOR gate since the series switching transistors of the NAND gate are NMOS transistors, which have an inherently faster switching speed than PMOS series switching transistors. In the CMOS NOR gate of FIGS. 3A and 3B the NOR gate has PMOS series switching transistors. By starting the sequence with a NAND gate, the response time of the sequence is desirably minimized. In FIG. 3 A only two-input NAND gates 21 and NOR gates 22 are used. Each logic gate 21 and 22 has a certain amount of delay. In present day standard sub-1 micron CMOS technology, this delay should be approximately a few hundred picoseconds per logic gate. Thus, it is possible to use a long sequence of alternating NAND and NOR gates as a functional AND or OR gate, such as found in a PLA. The response of the sequence is still fast enough to be of practical use. Moreover, the sequence permits an array of an AND or OR gates using the present invention to be laid out very compactly with a grid of input signal lines and voltage supply lines.

For purposes of simplification, logic gates 21 and 22 are depicted as receiving N programmable input signals -O-IN-I- Ea^cn logic gate 21 and 22 has one input terminal which links that gate to a preceding logic gate in the alternating sequence. The other input terminal is an input signal terminal which is programmable. Each input signal terminal of logic gates 21 and 22 may be coupled to the a line carrying an input signal or its complement, or to a fixed voltage line so as to render the particular logic gate 21 and 22 in a "DON'T CARE" state. In this state an input signal terminal is not responsive to an input signal or its complement. The functional logic gate represented by the sequence of alternating NAND and NOR gates is independent of the particular input signal. For NAND gate 21, the "DON'T CARE" signal voltage is a logic one signal, while the "DON'T CARE" voltage signal for NOR gate 22 is a logic zero signal.

FIG. 3B illustrates another embodiment of the invention using three-input NAND gates 23 with three-input NOR gates 24. Only the first NAND gate 25 which starts the sequence has two input terminals. A third input terminal I_s not needed since there is no prior NOR gate to link to.

For the same number of input signals, the embodiment of FIG. 3B shortens the sequence of alternating NAND and NOR gates 23 and 24, while increasing the complexity of each particular logic gate. As the complexity of each logic gate increases, its response time necessarily slows. The exact amount the response time of a logic gate is increased by the addition of more input signal lines, and is highly technology dependent. A shorter sequence of alternating three-input CMOS NAND and NOR gates is not necessarily faster or slower than a longer sequence of two-input NAND and NOR gates. That determination must be made on a case-by-case basis.

The present invention may also be implemented with four-input CMOS NAND and NOR gates. However, beyond this number, the complexity of laying out the signal lines and the increase in response time becomes evident so that a sequence of alternating NAND and NOR gates with more than four input lines to each logic gate is considered impractical.

The particular embodiment which follows is the three-input NAND and NOR gate. However, many of the comments are applicable to two-input and four-input CMOS NAND and NOR gates. FIGS. 4A and 4B show a three input CMOS NAND gate and a three-input CMOS NOR gate, respectively, in a sequence of alternating NAND and NOR gates which permits the easy implementation of a large multi-input AND or OR gate useful in PLAS.

The CMOS NAND gate in FIG. 4A has multiple pairs of transistors 44A and 44B, 45A and 45B, and 46A and 46B having opposing polarity and being connected between a power supply terminal at voltage V_cc (typically +5 volts) and a second power supply terminal at ground. Coupled between each pair of transistors is a circuit node 48 which is connected to an output terminal 47. Each pair of transistors 44, 45, and 46 have their gates connected to input terminals 41, 42 and 43, respectively. Transistors 44A, 45A and 46A are connected in series between node 48 and ground, and complementary transistors 44B, 45B, and 46B are connected in parallel between the power supply terminal at V_cc and the node 48.

Input terminal 41 , which is connected to the gates of the transistor pair 44A and 44B, which pair is most closely coupled to the node 48, is linked to the output terminal of the CMOS NOR gate which precedes it in the alternating sequence. Similarly the output terminal 47 is linked to the input terminal connected to the gates of the transistor pair most closely coupled to the node of the succeeding NOR gate. This arrangement improves the response time of the sequence by increasing the speed at which signals can ripple through the sequence of logic gates. The input terminals 42 and 43 may be coupled to receive arbitrary input signals I_j, I_{j+ 1} or their complements ϊ_j, and ϊ_{j+ 1}. To render a transistor pair into a "DON'T CARE" state, the input signal terminals 42 and 43 may also be connected to a source of voltage for a logic one. In this embodiment this voltage source is the voltage supply terminal at V_cc. Similarly, in the CMOS NOR gate of FIG. 4B, pairs of transistors 34A.B;

35A,B; and 36A,B are connected between two voltage sources at V_cc and ground. A circuit node 38, connected to an output terminal 37, is coupled between these transistor pairs. Since the illustrated gate is a NOR gate, transistors 34A, 35A, and 36A are connected in parallel between node 38 and ground. The complementary transistors 34B, 35B, and 36B, on the other hand, are connected in series between node 38 and power terminal at V_cc.

Each of the transistor pairs 34, 35 and 36 have their gates connected together to a single input terminal 31, 32 and 33, respectively. The input terminal 31 of the transistor pair 34A,B, which is most closely coupled to the node 38, is linked to the output terminal of the preceding CMOS NAND gate. Similarly, the output terminal 37 is linked to the input gate of the transistor pair of the succeeding NAND gate. This arrangement facilitates the response time of the logic gate sequence as discussed previously.

The other two input terminals 32 and 33 may be coupled to receive input signals I_j (or its complement) and I_i+ι (or its complement), respectively. Additionally, input signal terminals 32 and 33 may be connected to a voltage source of logic 0 state (here ground), which renders that input terminal into a "DON'T CARE" state.

Thus, the sequence of alternating CMOS NAND and NOR gates may be formed with each gate having three input terminals, one linking input terminal and two input signal terminals. The manner by which the logic gate sequence of the present invention may be laid out is illustrated in Figs. 5A and 5B. The techniques used to manufacture the present invention described herein are well known to those versed in the semiconductor processing technology.

FIG. 5B shows the mask layout of two adjacent three-input CMOS NOR gates. The following discussion refers mostly to the NOR gate on the right side of FIG. 5B. Lines 50 show the outline of the source-drain diffusion region into the silicon substrate of the integrated circuit. The gate is a NOR logic gate and this source-drain region is a heavily positively doped (P+) region. Lines 51 delineate another source-drain region in the substrate; this region is a heavily negatively doped (N+) region. Over the substrate is a layer of polysilicon which masks outline shown by lines 53, and over the polysilicon layer is a first metal layer which is shown by lines 54.

In FIG. 5B only part of the first metal layer is shown. The other portions of the first metal, or metal 1, layer is illustrated in Fig. 5 A. Contact regions 60-69 (FIG. 5b) show the locations where the metal 1 layer contacts the silicon substrate in the P+ and N+ regions or where the metal 1 layer contacts the polysilicon layer. For example, the contact area 60 is connected to a metal line at V_cc.

P-channel, or PMOS, transistors are formed by the P+ region outlined by the lines 50 with the polysilicon layer delineated by the lines 53 forming the gate electrodes of the MOS transistors. Regions 70, 71 and 72 show the gate regions of the three PMOS transistors which are connected in series.

Similarly, the N+ region outlined by the lines 51 and the polysilicon layer outlined by the lines 53 form N-channel, or NMOS, transistors. Part of the source- drain region outlined by the lines 51 is connected to ground through a contact region 66. Reference numerals 73, 74, and 75 show the channel regions under the polysilicon electrodes of the NMOS transistors.

Through a contact area 62, a linking input terminal of the CMOS NOR gate is coupled by the metal 1 layer to the output terminal of the preceding CMOS NAND gate. The contact area 62 provides the connection for the output signal of the preceding CMOS NAND gate to the gate electrodes of the PMOS transistor having channel region 70 and the NMOS transistor having channel region 73. It should be noted that these two transistors are most closely coupled to the contact region 63 from which the output signal of the NOR gate is transmitted through a metal 1 layer to the succeeding CMOS NAND gate, through the contact region 68. As illustrated, the sequence of alternating CMOS NAND and NOR gates are in a vertical direction.

To obtain the succeeding CMOS NAND gate, the same circuit layout is used but the polarities of the source-drain regions outlined by the lines 50A and 51 are reversed. The layout is also inverted about a centered vertical axis through the layout so that the contact region corresponding to region 60 is on the left side under, and in contact with, the vertical metal 1 line at ground. The region corresponding to contact region 66 is on the right under, and in contact with, the vertical metal 1 line at V_cc. In other words, the NAND gate appears like the NOR gate on the left side of FIG. 5B, except that the polarities of the source-drain regions are reversed. FIG. 5B also shows parts of the neighbouring logic circuit layouts as it might be used in an array. It can be seen that the embodiment shown in FIGS. 5B (and 5A) are highly suitable for a logic array layout.

FIG. 5A shows part of the metal 1 layer and the complete metal 2 layer portions which lie over the substrate and delineated polysilicon layer. Reference marks 90 in both Figs. 5A and 5B show the exact relationship and location of the masks defined in the two drawings with respect to each other.

In FIG. 5 A the metal regions are outlined by lines 54 and 55. Lines 54 show the bottom metal 1 layer, while lines 55 show the top metal 2 layer. The metal 2 lines are horizontal and carry arbitrary input signals I_n. The metal 2 layer also makes contact to the metal 1 layer below. Contact areas 80-84 show the location of these contact areas which may be programmed to be connected to different parts of the top metal 2 layer.

For example, the contact areas 80 and 82 are connected to the input signal terminals of the NOR gate lying below. The contact area 80 is connected to the gate electrodes of the PMOS transistor having the channel region 71 and the NMOS transistor having the channel region 74. The contact region 72 is connected to the PMOS transistor having the channel region 71 and the NMOS transistor having the channel region 75. These contact regions may be programmed by selecting to which metal lines these contact regions are to be connected. Lines 56 show these optional connections. For example, the contact region 82 may be connected to the metal 2 layer bearing an I_n input signal, or be connected to the metal 2 line above bearing the complement I_n input signal. Additionally, the contact area 82 may be connected to the vertical metal I layer at the left through the contact area 83. This metal 1 line is at a fixed voltage, ground, to render that input terminal into a "DON'T CARE" state. Thus, the sequence of alternating NAND and NOR logic gates is programmed in one of the final steps in the manufacture of the integrated circuit. A PLA according to the present invention is programmed when the top metal 2 layer is delineated into the desired pattern. This is desirable since it permits a PLA manufacturer to process semiconductor wafers almost to completion including the deposition of the metal 2 layer. The wafers may be stored and, upon a customer's specifications, may be quickly programmed by delineating the metal 2 layer into the desired pattern. As such, the time between a customer's request for a PLA and the delivery of the programmed part is minimized.

As can be seen in FIGS. 5A and 5B, the present invention has a matrix of conduction lines over a semiconductor substrate which bears CMOS logic gates. The matrix has vertical metal 1 lines at fixed voltages, ground and V_cc, and horizontal metal 2 lines carrying true and complementary input signals to form a grid. Within each rectangular grid element there is a contact area as an input signal terminal to the CMOS logic gate below. The input signal terminal may be simply programmed by the delineation of the topmost metal layer of the integrated circuit. This physical association between grid elements and input terminals is also possible with two-input and four-input CMOS logic gates.

Thus, the present invention provides for the implementation of arrays of CMOS AND and OR gates. For a PLA the present invention may be used for one or both arrays. For example, a PLA having eight output functions, each output function having up to 48 product terms with each product term having up to 16 true or complementary input signals, may be designed by utilizing the present invention for the functional array of AND gates. Each of the 48 sequences of alternating CMOS logic gates is connectable up to 32 true and complementary input signals.

On the other hand, the functional array of OR gates is best implemented by more conventional means. Each of the eight output function terminals is coupled to three levels of CMOS NOR and NAND gates which receive the product terms in parallel. A first level of twelve NOR gates receives the 48 product terms signals (each NOR gate connectable to four product terms). A second level of three NAND gates receives the signals from the NOR gates, a NOR gate with an inverter at its output terminal combines the output signals of the three NAND gates. This is a conventional logic tree structure.

While not as compact as a layout of eight sequences of alternating NAND and NOR gates according to the present invention, the conventional logic tree structure is suitable for the function array of OR gates in the PLA. Since the incoming signals are processed in parallel, the response time of the conventional array is faster than the longer sequence of alternating logic gates of this invention. If three-input logic gates are used, then a sequence would provide a response of some 24 serially connected gates. The conventional layout has a response of three serially connected gates.

One can balance performance and layout considerations by mixing conventional logic design with the present invention to obtain the best results. Rather than having the input terminals of the alternating sequence of

CMOS NAND and NOR gates programmed by the definition of a top metal layer, the present invention has another embodiment which uses charge storage MOS transistors to program the input terminals of the CMOS logic gates. FIGS. 6A and 6B show an embodiment of the present invention with the charge storage MOS transistors 91-96 shown with a special symbol in which each transistor has two-gate symbols. It is understood by those in the art that the top gate symbol represents the control gate while the gate symbol below represents the floating gate.

FIG. 6A shows a two-input CMOS NAND gate described previously. The output terminal 47 of the CMOS logic gate is connected to the linking input terminal of a CMOS NOR gate. Likewise, the linking input terminal 41 is connected to the output terminal of a preceding CMOS NOR gate. However, instead of having its input terminal 42 defined by a metal masking operation as described with respect to FIGS. 5A and 5B, the input terminal 42 is connected to a circuit having three charge storage MOS transistors 91-93. The input terminal 42 is connected to the source regions of transistors 91-93 and to ground through a transistor 97. The drain regions of the transistors 91-93 are respectively connected to input signal terminals 87-89.

Operationally, the charge storage MOS transistor circuit couples the input terminal 42 to any one of the input signal terminals 87-89. The coupling is done by storing charge on any one of the floating gates of the transistors 91-93. The charge stored puts the particular charge storage MOS transistor in a conducting state.

To charge a selected transistor 91-93, transistor 97 is turned on by raising a Program Enable voltage, V_PE, high. The source regions of the transistors 91-93 are thus coupled to ground for the programming current. The control electrodes on the transistors 91- 93 are raised to a special programming voltage, V_P1, and the input signal terminal 87-89 of the selected transistor is also raised to another special programming voltage, V_P2. These programming voltages are typically + 15-20 volts. Electrons will tunnel from the channel and source regions of the selected transistor through the gate oxide to the floating gate. The programming of the charge storage MOS transistors is performed by decoder circuits which respond to address signals to charge the floating gates of the said MOS transistors. The charge storage MOS transistors may be arranged in an array themselves such that a particular charge storage MOS transistor is selected by identifying the particular column and row of the transistor. The column address allows the address decoder to operate the V_pι and V_PE voltages, while the row address decoders operate the V_P2 voltage of the selected charge storage MOS transistor. The specific designs and operations of such address decoders are well known to those skilled in the art of designing semi-conductor memory devices, especially MOS memory devices.

If the transistor 91 is thus programmed, the input terminal 42 is coupled to the terminal 87. Since the input signal at this terminal 87 is a bias signal, V_cc, the CMOS NAND gate is in a "DON'T CARE" state, as described previously. If the transistor 92 is selected, then the CMOS NAND gate is coupled to the input signal I_j. Similarly, if transistor 93 is selected, the CMOS NAND gate is coupled to the inverse of the I input signal or .

In the case of a CMOS NOR logic gate, the bias signal is not a logic high signal, V_cc, but rather a logic low signal, ground in this case. This implements the "DON'T CARE" state for the CMOS NOR logic gate.

In another embodiment of the invention, EPROM (Erasable Programmable Read Only Memory) transistors and EEPROM (Electrically Erasable Programmable Read Only Memory) transistors may be used as the charge storage MOS transistors. For EPROM transistors, the charge stored on the floating gates are erased by exposing the transistors to ultraviolet light. This deprograms the input terminals of the CMOS logic gates. On the other hand, EEPROM transistors are erased by altering the programming operation of V_P1, V_p2 and V_PE. Obviously, in the case of EEPROM transistors, the decoder circuits are necessarily more complicated than those for EPROM transistors in order to handle the deprogramming operation of said EEPROM transistors.

FIG. 6B shows an embodiment using charge storage MOS transistors to couple input terminals to the CMOS logic gate for three input CMOS gates. The drawing shows a CMOS NAND gate having the linking input terminal 41 and input terminals 42 and 43 each connected to a set of three input signal terminals by a corresponding set of three charge storage MOS transistors. As described above, the operation of this circuit is identical. The charge storage transistors 91-96 may be used in the PLA to program the input terminals of the functional AND gate array, while the input terminals of the functional OR gate array is defined by metal connections. Alternatively, both functional gate arrays may be programmable by the charge storage transistors. Other combinations are also conceivable.

The same principles apply for any type of storage element applied to the control gates of the coupling transistors 91-93. For example, FIG. 7 shows another embodiment of the invention where the charge storage elements are binary latch devices 100a, 100b and 100c. The binary latch holds the information determinative of which input signal is to be coupled to the logic gate. Thus, in this embodiment the programming transistors 97 and 98 (shown in previous embodiments) are not needed.

Upon power-up of the device, the specific pattern of signal coupling to the logic gates is written into the latches via the write control lines. This process is analogous to the writing of information into a static RAM (random access memory).

While several embodiments of the present invention has been shown and described, it is to be understood that many changes and modifications may be made thereunto without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

CLAIMS:

1. An integrated circuit programmable logic array (PLA) having an array of functional AND gates coupled to an array of functional OR gates, at least one of said arrays comprising complementary IGFET NAND logic gates and IGFET NOR logic gates, each complementary logic gate having at least two pairs of opposite polarity insulated gate transistors (IGFET) coupled about an output node between two voltage source terminals, the gates of each transistor pair being coupled to an input terminal; a first input terminal of a complementary NAND logic gate being connected to an output node of a complementary NOR logic gate and a first input terminal of a complementary NOR logic gate being connected to an output node of a complementary NAND logic gate to form an alternating sequence of serially connected complementary NAND and NOR gates to operate as a large multi-input AND or OR gate the PLA comprising control means for operatively coupling second input terminals of said complementary NAND and NOR logic gates to selected input signal terminals to program said PLA. 2. The PLA according to claim 1, wherein said control means comprises a plurality of charge storage IGFET transistors having channel regions and polarity, said IGFET transistors selectively coupling said input signal terminals to said input terminals of said complementary NAND and NOR gates by a charge stored above said channel regions of said IGFET transistors. 4. The PLA according to claim 3, wherein said each of said complementary

NAND and NOR logic gates comprises: an output terminal connected to a circuit node coupled between pairs of said charge storage IGFET transistors of opposite channel polarity, the gates of each pair of IGFET transistors being connected together and coupled to said input terminals; an output terminal of the logic gate in the sequence of alternating complementary NAND and NOR gates coupled to an input terminal of a first pair of opposite polarity transistors closest to the circuit node; and an input terminal to a second pair of opposite polarity IGFET transistors capable of being coupled to a plurality of said input signal terminals through a plurality of said charge storage IGFET transistors, one charge storage IGFET transistor associated with one input signal terminal, said input terminal programmed to receive a selected input signal by placing an associated charge storage IGFET transistor in a first charge storage state to couple said input terminal of said complementary NAND and NOR gates to said selected input signal terminal.

5. The PLA according to claim 4, wherein said charge storage IGFET transistors associated with unselected input signal terminals are in a second charge storage state to decouple said input terminal from said unselected input signal terminals.

6. The PLA according to claim 5, wherein each of said charge storage IGFET transistors has a floating gate, the presence or absence of charge on said floating gate controlling the coupling operation of said charge storage IGFET transistor.

7. The PLA according to claim 6, wherein said charge storage IGFET transistors comprise EEPROM transistors.

8. The PLA according to claim 6 or 7, wherein said charge storage IGFET transistors comprise EPROM transistors.

9. The PLA according to claim 6, 7 or 8, wherein said plurality of input signals terminals comprises: a first terminal to receive a predetermined input signal; a second input terminal to receive the inverse of said predetermined input signal; and, a third input terminal to receive a bias signal to render said complementary logic gate into a DON'T CARE state for said input.

10. The PLA according to claim 1 or 2, wherein said control means comprises a plurality of binary latch devices for receiving and holding information determinative of which input signal terminal is to be coupled to the input terminal of the logic gate upon power of the PLA.