DE3484669D1 - Leseverstaerker. - Google Patents

Leseverstaerker.

Info

Publication number
DE3484669D1
DE3484669D1 DE8484401825T DE3484669T DE3484669D1 DE 3484669 D1 DE3484669 D1 DE 3484669D1 DE 8484401825 T DE8484401825 T DE 8484401825T DE 3484669 T DE3484669 T DE 3484669T DE 3484669 D1 DE3484669 D1 DE 3484669D1
Authority
DE
Germany
Prior art keywords
reading amplifier
amplifier
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484401825T
Other languages
English (en)
Inventor
Atuo Koshizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3484669D1 publication Critical patent/DE3484669D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE8484401825T 1983-09-17 1984-09-14 Leseverstaerker. Expired - Fee Related DE3484669D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58171683A JPS6063786A (ja) 1983-09-17 1983-09-17 センスアンプ

Publications (1)

Publication Number Publication Date
DE3484669D1 true DE3484669D1 (de) 1991-07-11

Family

ID=15927757

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484401825T Expired - Fee Related DE3484669D1 (de) 1983-09-17 1984-09-14 Leseverstaerker.

Country Status (5)

Country Link
US (1) US4634900A (de)
EP (1) EP0136229B1 (de)
JP (1) JPS6063786A (de)
KR (1) KR890002960B1 (de)
DE (1) DE3484669D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62167698A (ja) * 1986-01-20 1987-07-24 Fujitsu Ltd 半導体記億装置
JPS62170097A (ja) * 1986-01-21 1987-07-27 Fujitsu Ltd 半導体記憶装置
JP2514330B2 (ja) * 1986-05-30 1996-07-10 日本テキサス・インスツルメンツ株式会社 センスアンプ回路
US4791324A (en) * 1987-04-10 1988-12-13 Motorola, Inc. CMOS differential-amplifier sense amplifier
US5034636A (en) * 1990-06-04 1991-07-23 Motorola, Inc. Sense amplifier with an integral logic function
EP0626693A3 (de) * 1993-03-31 1995-03-22 Sgs Thomson Microelectronics Multiplex-Leseverstärker.
US5487048A (en) * 1993-03-31 1996-01-23 Sgs-Thomson Microelectronics, Inc. Multiplexing sense amplifier
US5377143A (en) * 1993-03-31 1994-12-27 Sgs-Thomson Microelectronics, Inc. Multiplexing sense amplifier having level shifter circuits
US5610573A (en) * 1995-09-13 1997-03-11 Lsi Logic Corporation Method and apparatus for detecting assertion of multiple signals
FR2748617B1 (fr) * 1996-05-13 1998-08-14 Texas Instruments France Cellule de bit de courant et reseau a courant commute forme de telles cellules
US6160507A (en) * 1996-05-13 2000-12-12 Texas Instruments Incorporated Current bit cell and switched current network formed of such cells
KR100297324B1 (ko) * 1998-12-16 2001-08-07 김영환 반도체 집적회로의 증폭기

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3879621A (en) * 1973-04-18 1975-04-22 Ibm Sense amplifier
US3953839A (en) * 1975-04-10 1976-04-27 International Business Machines Corporation Bit circuitry for enhance-deplete ram
JPS6019599B2 (ja) * 1977-06-13 1985-05-16 日本電気株式会社 相補型絶縁ゲ−ト半導体差動増幅回路
JPS5593587A (en) * 1978-12-29 1980-07-16 Fujitsu Ltd Sense amplifier circuit of mos memory
JPS5616992A (en) * 1979-07-20 1981-02-18 Hitachi Ltd Signal readout circuit
JPS5629889A (en) * 1979-08-21 1981-03-25 Seiko Epson Corp Mos random access memory
US4376987A (en) * 1980-08-18 1983-03-15 Mcdonnell Douglas Corporation Threshold referenced MNOS sense amplifier
JPS5838873B2 (ja) * 1980-10-15 1983-08-25 富士通株式会社 センス回路
JPS5819760Y2 (ja) * 1981-11-26 1983-04-22 株式会社東芝 半導体記憶装置

Also Published As

Publication number Publication date
KR850002638A (ko) 1985-05-15
JPH0325875B2 (de) 1991-04-09
EP0136229A2 (de) 1985-04-03
EP0136229A3 (en) 1988-03-30
KR890002960B1 (ko) 1989-08-14
JPS6063786A (ja) 1985-04-12
US4634900A (en) 1987-01-06
EP0136229B1 (de) 1991-06-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee