DE3465221D1 - Method of manufacturing a semiconductor device having isolation regions - Google Patents

Method of manufacturing a semiconductor device having isolation regions

Info

Publication number
DE3465221D1
DE3465221D1 DE8484301289T DE3465221T DE3465221D1 DE 3465221 D1 DE3465221 D1 DE 3465221D1 DE 8484301289 T DE8484301289 T DE 8484301289T DE 3465221 T DE3465221 T DE 3465221T DE 3465221 D1 DE3465221 D1 DE 3465221D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
isolation regions
isolation
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484301289T
Other languages
English (en)
Inventor
Kentaro Oki Electric Yoshioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE3465221D1 publication Critical patent/DE3465221D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
DE8484301289T 1983-02-28 1984-02-28 Method of manufacturing a semiconductor device having isolation regions Expired DE3465221D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3099683A JPS59158534A (ja) 1983-02-28 1983-02-28 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3465221D1 true DE3465221D1 (en) 1987-09-10

Family

ID=12319204

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484301289T Expired DE3465221D1 (en) 1983-02-28 1984-02-28 Method of manufacturing a semiconductor device having isolation regions

Country Status (3)

Country Link
EP (1) EP0120614B1 (de)
JP (1) JPS59158534A (de)
DE (1) DE3465221D1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4654120A (en) * 1985-10-31 1987-03-31 International Business Machines Corporation Method of making a planar trench semiconductor structure
US4818235A (en) * 1987-02-10 1989-04-04 Industry Technology Research Institute Isolation structures for integrated circuits
US4876217A (en) * 1988-03-24 1989-10-24 Motorola Inc. Method of forming semiconductor structure isolation regions
US5382541A (en) * 1992-08-26 1995-01-17 Harris Corporation Method for forming recessed oxide isolation containing deep and shallow trenches
JP3022714B2 (ja) * 1993-10-29 2000-03-21 日本電気株式会社 半導体装置およびその製造方法
US5393694A (en) * 1994-06-15 1995-02-28 Micron Semiconductor, Inc. Advanced process for recessed poly buffered locos

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
IE52971B1 (en) * 1979-07-23 1988-04-27 Fujitsu Ltd Method of manufacturing a semiconductor device wherein first and second layers are formed
DE3265339D1 (en) * 1981-03-20 1985-09-19 Toshiba Kk Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS59158534A (ja) 1984-09-08
EP0120614A1 (de) 1984-10-03
EP0120614B1 (de) 1987-08-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee