DE3379132D1 - Method for fabricating deis structure between two polysilicon gate electrodes and memories resulting therefrom - Google Patents

Method for fabricating deis structure between two polysilicon gate electrodes and memories resulting therefrom

Info

Publication number
DE3379132D1
DE3379132D1 DE8383112058T DE3379132T DE3379132D1 DE 3379132 D1 DE3379132 D1 DE 3379132D1 DE 8383112058 T DE8383112058 T DE 8383112058T DE 3379132 T DE3379132 T DE 3379132T DE 3379132 D1 DE3379132 D1 DE 3379132D1
Authority
DE
Germany
Prior art keywords
fabricating
gate electrodes
polysilicon gate
resulting therefrom
deis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383112058T
Other languages
German (de)
English (en)
Inventor
Anthony John Hoeg
Charles Thomas Kroll
Geoffrey Brownell Stephens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3379132D1 publication Critical patent/DE3379132D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/682—Floating-gate IGFETs having only two programming levels programmed by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction
DE8383112058T 1983-04-01 1983-12-01 Method for fabricating deis structure between two polysilicon gate electrodes and memories resulting therefrom Expired DE3379132D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/481,212 US4458407A (en) 1983-04-01 1983-04-01 Process for fabricating semi-conductive oxide between two poly silicon gate electrodes

Publications (1)

Publication Number Publication Date
DE3379132D1 true DE3379132D1 (en) 1989-03-09

Family

ID=23911080

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383112058T Expired DE3379132D1 (en) 1983-04-01 1983-12-01 Method for fabricating deis structure between two polysilicon gate electrodes and memories resulting therefrom

Country Status (4)

Country Link
US (1) US4458407A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0123726B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS59186375A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3379132D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56116670A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPS61127159A (ja) * 1984-11-26 1986-06-14 Nippon Texas Instr Kk スタテイツク形記憶素子
US4656729A (en) * 1985-03-25 1987-04-14 International Business Machines Corp. Dual electron injection structure and process with self-limiting oxidation barrier
IT1191755B (it) * 1986-04-29 1988-03-23 Sgs Microelettronica Spa Processo di fabbricazione per celle eprom con dielettrico ossido-nitruro-ossido
EP0250611B1 (de) * 1986-06-21 1990-12-19 Deutsche ITT Industries GmbH Verfahren zum Entfernen einer strukturierten Maskierungsschicht
JP2633541B2 (ja) * 1987-01-07 1997-07-23 株式会社東芝 半導体メモリ装置の製造方法
JP2633555B2 (ja) * 1987-03-23 1997-07-23 株式会社東芝 半導体装置の製造方法
CA1276314C (en) * 1988-03-24 1990-11-13 Alexander Kalnitsky Silicon ion implanted semiconductor device
EP0464196B1 (en) * 1990-01-22 2002-05-08 Silicon Storage Technology, Inc. Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate
US5763937A (en) * 1990-03-05 1998-06-09 Vlsi Technology, Inc. Device reliability of MOS devices using silicon rich plasma oxide films
US5290727A (en) * 1990-03-05 1994-03-01 Vlsi Technology, Inc. Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors
US5266509A (en) * 1990-05-11 1993-11-30 North American Philips Corporation Fabrication method for a floating-gate field-effect transistor structure
US5331189A (en) * 1992-06-19 1994-07-19 International Business Machines Corporation Asymmetric multilayered dielectric material and a flash EEPROM using the same
US5427967A (en) * 1993-03-11 1995-06-27 National Semiconductor Corporation Technique for making memory cells in a way which suppresses electrically conductive stringers
US5306657A (en) * 1993-03-22 1994-04-26 United Microelectronics Corporation Process for forming an FET read only memory device
US5432749A (en) * 1994-04-26 1995-07-11 National Semiconductor Corporation Non-volatile memory cell having hole confinement layer for reducing band-to-band tunneling
KR960039197A (ko) * 1995-04-12 1996-11-21 모리시다 요이치 실리콘 산화막의 형성방법 및 반도체 장치의 제조방법
US5724374A (en) * 1996-08-19 1998-03-03 Picolight Incorporated Aperture comprising an oxidized region and a semiconductor material
US6596590B1 (en) * 1997-04-25 2003-07-22 Nippon Steel Corporation Method of making multi-level type non-volatile semiconductor memory device
US5899713A (en) * 1997-10-28 1999-05-04 International Business Machines Corporation Method of making NVRAM cell with planar control gate
US6445029B1 (en) 2000-10-24 2002-09-03 International Business Machines Corporation NVRAM array device with enhanced write and erase
US20060189167A1 (en) * 2005-02-18 2006-08-24 Hsiang-Ying Wang Method for fabricating silicon nitride film

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4355455A (en) * 1979-07-19 1982-10-26 National Semiconductor Corporation Method of manufacture for self-aligned floating gate memory cell
EP0034653B1 (en) * 1980-02-25 1984-05-16 International Business Machines Corporation Dual electron injector structures

Also Published As

Publication number Publication date
EP0123726B1 (en) 1989-02-01
JPS59186375A (ja) 1984-10-23
US4458407A (en) 1984-07-10
EP0123726A3 (en) 1987-02-25
EP0123726A2 (en) 1984-11-07
JPH0259633B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-12-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee