DE3374102D1 - Method of making ohmic contacts regions and device manufactured by the method - Google Patents

Method of making ohmic contacts regions and device manufactured by the method

Info

Publication number
DE3374102D1
DE3374102D1 DE8383105022T DE3374102T DE3374102D1 DE 3374102 D1 DE3374102 D1 DE 3374102D1 DE 8383105022 T DE8383105022 T DE 8383105022T DE 3374102 T DE3374102 T DE 3374102T DE 3374102 D1 DE3374102 D1 DE 3374102D1
Authority
DE
Germany
Prior art keywords
device manufactured
ohmic contacts
making ohmic
contacts regions
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383105022T
Other languages
German (de)
English (en)
Inventor
Masakazu Kakumu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3374102D1 publication Critical patent/DE3374102D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/923—Diffusion through a layer
DE8383105022T 1982-05-21 1983-05-20 Method of making ohmic contacts regions and device manufactured by the method Expired DE3374102D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57085937A JPS58202525A (ja) 1982-05-21 1982-05-21 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3374102D1 true DE3374102D1 (en) 1987-11-19

Family

ID=13872669

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383105022T Expired DE3374102D1 (en) 1982-05-21 1983-05-20 Method of making ohmic contacts regions and device manufactured by the method

Country Status (4)

Country Link
US (1) US4536943A (https=)
EP (1) EP0098941B1 (https=)
JP (1) JPS58202525A (https=)
DE (1) DE3374102D1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4702000A (en) * 1986-03-19 1987-10-27 Harris Corporation Technique for elimination of polysilicon stringers in direct moat field oxide structure
US4818725A (en) * 1986-09-15 1989-04-04 Harris Corp. Technique for forming planarized gate structure
US4871688A (en) * 1988-05-02 1989-10-03 Micron Technology, Inc. Sequence of etching polysilicon in semiconductor memory devices
US4957878A (en) * 1988-05-02 1990-09-18 Micron Technology, Inc. Reduced mask manufacture of semiconductor memory devices
JP3285934B2 (ja) * 1991-07-16 2002-05-27 株式会社東芝 半導体装置の製造方法
KR960008558B1 (en) * 1993-03-02 1996-06-28 Samsung Electronics Co Ltd Low resistance contact structure and manufacturing method of high integrated semiconductor device
US5342798A (en) * 1993-11-23 1994-08-30 Vlsi Technology, Inc. Method for selective salicidation of source/drain regions of a transistor
JPH08255907A (ja) * 1995-01-18 1996-10-01 Canon Inc 絶縁ゲート型トランジスタ及びその製造方法
JP3525316B2 (ja) * 1996-11-12 2004-05-10 株式会社半導体エネルギー研究所 アクティブマトリクス型表示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967981A (en) * 1971-01-14 1976-07-06 Shumpei Yamazaki Method for manufacturing a semiconductor field effort transistor
JPS49131585A (https=) * 1973-04-20 1974-12-17
US4127931A (en) * 1974-10-04 1978-12-05 Nippon Electric Co., Ltd. Semiconductor device
US4282647A (en) * 1978-04-04 1981-08-11 Standard Microsystems Corporation Method of fabricating high density refractory metal gate MOS integrated circuits utilizing the gate as a selective diffusion and oxidation mask
JPS5561037A (en) * 1978-10-31 1980-05-08 Toshiba Corp Preparation of semiconductor device
NL7900280A (nl) * 1979-01-15 1980-07-17 Philips Nv Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan.
US4319395A (en) * 1979-06-28 1982-03-16 Motorola, Inc. Method of making self-aligned device
US4431460A (en) * 1982-03-08 1984-02-14 International Business Machines Corporation Method of producing shallow, narrow base bipolar transistor structures via dual implantations of selected polycrystalline layer

Also Published As

Publication number Publication date
JPH0371768B2 (https=) 1991-11-14
EP0098941A1 (en) 1984-01-25
JPS58202525A (ja) 1983-11-25
US4536943A (en) 1985-08-27
EP0098941B1 (en) 1987-10-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee