DE3328736A1 - CIRCUIT BOARD - Google Patents

Description

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description

The invention relates to chip assembly techniques for (printed) circuit boards, especially compact ones Packaging of memory chips on circuit boards, and a circuit board therefor.

Heretofore, the address pins have been used on memory chips placed side by side on the same circuit board electrically connected or combined using a process known as "daisy-chaining": - switches. By connecting selected address pins of the neighboring memory chips in this way, the Allows data to be entered and retrieved from the chips.

As is known, there is a constant need to increase the so-called packing density of circuit boards without impermissible Complication of their construction. This is particularly true of memory chips. The invention now represents an improvement compared to the previous "daisy-chaining" process with regard to improved circuit board utilization without undue complication of the structure.

The object of the invention is thus to create an improved circuit board for attachment on both sides of chips on it according to a compact construction process (packaging technique) to increase the packing density of memory

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Chips on the circuit board with optimal use of the circuit board area.

The chips should be mounted and selected directly on opposite sides of a circuit board Pins of the chips can be connected together via common or collective contact holes (common vias).

In addition, a composite connection pattern is intended for the interconnection of the address or addressing pins of a chip can be used with those of an opposing chip via common contact holes.

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The stated task is supported by the in the attached Patent claims characterized features solved.

According to the invention, the chips are one on both sides Circuit board immediately opposite one another by means of a metallized / composite or composite connection pattern mounted on both sides of the circuit board. Electroplated Contact holes penetrate the circuit board to connect the opposing connection patterns (pad patterns). By means of these contact holes, the greatest possible number of pins is attached to the opposite one Chips interconnected so that optimal use of the circuit board area is achieved.

According to the invention is a circuit board that only

one side carries chips, folded over halfway so that chips are on both sides of the circuit board and therefore their size compared to a gg circuit board, in which the conventional connection

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drive is only applied on one side, scaled down by half. In the circuit board according to the invention is the so-called. "Daisy-Chaining" connection method on both sides of the circuit board in combination with the through-electroplated collective via / bonded connection pattern concept applied. By folding the circuit board down while shrinking its sizes up half the lengths of address and signal lines are also reduced *. So this way will doubles the overall circuit density of the circuit board assembly »

In a preferred embodiment, the invention is applied to memory chips, the address pins of the chips mounted opposite being interconnected via common or collective contact holes (common vias). The composite metallized pad patterns used in connection therewith enable the interconnection of the largest possible number of pins on the oppositely mounted chips.

In the following, a preferred embodiment of the 2g invention is explained in more detail with reference to the drawing. Ee show:

Fig. 1 is a side view of a circuit board of the invention, with certain collection Kontaktlächer ^are located in accordance with dashed lines'

Fig. 2 is a plan view of the circuit board, seen in the direction of arrows 2-2 in Fig. 1,

FIG. 3 is a plan view similar to FIG. 2 for illustration

the composite connection pattern with the chip omitted,

Fig. 4 is a section along the line 4-4 in Fig. 1,

Fig. 5 is a plan view similar to Fig. 4 of the bonded connection pattern with omitted chip and

6 is a plan view showing the overlap of the composite connection pattern according to FIG. 3 with that of FIG. 5.

According to Fig. 1, a first chip 1 is on the top a circuit board 150 is arranged. A second chip 201 is mounted directly opposite on the underside j5 154 of the circuit board 150. According to the invention the first chip 1 is thus directly above the second chip 201, with certain pins of both chips still on are interconnected in a manner to be described for the best possible use of the circuit board area.

2 illustrates a top view of the first chip 1 mounted on the upper side 152 of the circuit board 150, which has a plurality of external contacts or pins 11-30 around its periphery. At the dar-

The embodiment shown in FIG. 2g is the chip 1 a 16-kilobit memory chip with 20 pins. On top 152 of circuit board 150 is a a composite connection pattern 3 5 forming metallization pattern applied. That according to FIG. 2 under the chip 1 lying connection pattern 35 is illustrated more clearly in FIG. The composite connection pattern 35 consists of a series of electrically conductive contact points or conductor tracks ^ n (pads) 41 to 64, each of which is galvanized or metallized through hole or

_oc a contact hole 71 to 94 are penetrated. The contact

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Holes 71 to 94 are electrically connected to the associated conductor tracks 41 to 64 and run completely

• 5 through the circuit board 150. FIG. 3 contains alphanumeric pin designations for the chip A to be described in more detail. The circuit board 150 is formed in multiple layers with circuit or circuit layers 160 to 165 (cf. FIG. 1) = the contact holes (vias) 41 to 64 are selectively connected to the circuit layers 160 to 165 ′ in a conventional manner.

As best seen in Figure 2, the pins are 11 to 30 of the chip 1 via soldered connections 101 to 120 connected to the conductor tracks 41 to 48, 51 to 54 and 57-64 of the connection pattern 35. Each pin 11 to 30 of the chip 1 is thus by means of soldered connections 101 to 120, conductor tracks 41 to 48, 51 to 54 and 57 to 64 as well Contact holes 71 to 86 and 88, 90, 91, 93 connected to the relevant circuit layers 160 to 165.

The second chip 201 is similar to the immediate opposite side 154 of the Schaltungsple-te 150 switched. According to FIG. 4 (section along the line 4-4 in FIG. 1), the pins 211 to 230 are provided

Chip 202, with the exception of its arrangement rotated by 180 °, with the chip 1 formed identically. The compound connection pattern 235 for chip 201 also corresponds essentially the connection raster 35, only that it is before the

Attaches to the underside 154 of the circuit board has been rotated by 180 ° with respect to the chip 1; in addition, the conductor tracks 250, 251, 254 and 255 of the connection pattern 235 with respect to the relevant conductor tracks 50, 51, 54 and 46 of the connection pattern 35 according to FIG. 3 and 5 designed a little differently.

As shown in FIG. 5, the composite terminal pattern 235 is composed of Contact points or conductor tracks (pads) 241 to 264, each of which is penetrated by contact holes 71 to 94. The alphanumeric pin designations for the chip 201 will be explained in more detail later. The contact holes 71 to 94 are the same, which penetrate the conductor tracks 41 to 64 of the connection pattern 35. Since the

1 (3 contact holes 71 to 94 are electrically conductive galvanized or metallized, through holes they electrically connect the conductor tracks 41 to 64 of the connection pattern 35 to the conductor tracks 241 to 264 of the connection pattern 235. According to FIG. 4, the pins 211 to 230 of the chip 201 are connected via solder points 271 to 290 to the relevant Conductor tracks 241 to 248, 251 to 254 and 257 to 264 are connected.

A comparison of FIG. 2 with FIG. 4 shows that the contact holes 71 to 86 "common" or "collective" contact holes are. For example, the contact hole 71 is the pin 11 of the chip 1 and the pin 230 of the chip 201, the contact hole 72 to the pin 12 of the chip 1 and the pin 212 of the chip 201, the contact hole 73 to the pin 13 of the Chip 1 and pin 213 of chip 201 commonly assigned, and so on. Pins 211-217, 220, 221 and 224-12 230 of the chip 201 are thus via the common contact holes 71 to 86 with the pins 11 to 17, 20, 21 and to 30 interconnected. In this embodiment, there are sixteen pins that are mounted opposite one another Memory chips 1 and 201 are commoned, while four pins of each chip 1 and 201 are not connected ^. These latter pins are pins 18, 19, 22 and 23 of chip 1 and pins 218, 219 222 and 223 of the chip 201. These not connected together

The eight non-common contacts or pins Associated with single contact holes 87 to 94. 5

Fig. 6 illustrates the bonded bond pattern 35 as well as disposed over the bonded bond pattern 235 the common assignment of the contact holes 71 to 86 and the non-common (separate) assignment of the contact holes 87 to 94.

After explaining the basic idea of a bonded connection pattern and the use of the common or collective contact holes is hereinafter the application of Invention to a 20-pin 16K (ilobit) memory chip (IMS 1400). Fig. 2 shows the following solder connections of the pins of the chip 1 with the Conductor tracks (contact points) of the connection pattern 35:

Memory address A - pin 11 on trace 41

Memory address A ₂ - pin 12 on trace 42

Memory address A- - pin 13 on trace 43

Memory address A _g - pin 14 on trace 44

Memory address A _g - pin 15 on trace 45

Memory address & - \ _Q ~ pin 16 on trace 46

Memory address A ^ ₂ "pin 17 on trace 47

Data output D _QUt - pin 18 on conductor run

Authorization for writing WE - pin 19 on conductor run

Ground V ₃₅ - pin 20 on conductor run

Chip approval CE - pin 21 on conductor track

Data input D _in - pin 22 on conductor run

z / in.

Memory address Memory address Memory address Memory address Memory address Memory address Memory address

Power (supply) Vcc - pin 30 on trace 64

^A 13 - Pen 23 at Ladder line 57 ^A 11 - Pen 24 at Ladder line 58 A ₉ - Pen 25th at Ladder line 59 ^A 7 - Pen 26th at Ladder line 60 ^A 5 - Pen 27 at Ladder line 61 ^A 3 - Pen 28 at Ladder line 62 - Pen 29 at Ladder line 63

4 also shows the following soldered connections between the pins of the chip 201 and the conductor tracks of the connection pattern 23 5:

Power (supply) Vcc - pin 211 on trace 241

Memory address A ₁ Memory address A ₃ Memory address A ₅ Memory address A ₇ Memory address A _g Memory address A-., Memory address A- ^ ~

Data input D. Chip enable CE Ground V _ss

_{Write enable} WE data output D QUt Pin 212 on conductor run 242 Pin 213 on conductor run 243 Pin 214 on conductor run 244 Pin 215 on conductor run 245 Pin 216 on conductor run 246 Pin 217 on conductor run 247 Pin 218 on conductor run 248

- Pin 219 on the ladder run

- Pin 220 on the conductor run

- Pin 221 on the conductor run

- Pin 222 on the conductor run

- Pin 223 on the conductor track

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Memory address A ₁₂ - pin 224 on track 258 Memory address A ₁₀ - pin 225 on track 259 Memory address Ag - pin 226 on track 260 Memory address Ag - pin 227 on track 261 Memory address A ₄ - pin 228 on track 262 Memory address A ₂ - pin 229 on Trace 263 memory address A - pin 230 on trace 264

. . The application of the invention to these memory chips is explained below with reference to FIG. 6:

The memory addresses A _{Q of} the chips 1 and 201 are interconnected via the collective contact hole 71.

The memory addresses A_ (chip 1) and A ₁ (chip 201) are interconnected via the contact hole 72.

The memory addresses A ^ (chip 1) and A ₃ (chip 201) are interconnected via the contact hole 73.

The memory addresses A _ß (chip 1) and A ₅ (chip 201) are interconnected via the contact hole 74.

The memory addresses Ao (chip 1) and A ₇ (chip 201) are interconnected via the contact hole 75.

The memory addresses A ₁ (chip 1) and A _g (chip 201) are interconnected via the contact hole 76.

The memory addresses A ₁₂ (chip 1) and A ₁₁ (chip 201) are interconnected via the contact hole 77.

The data output D _QUt (chip 1) is connected to the separate contact hole 88.

The memory address A ₁₃ (chip 201) is at the separate contact hole 87.

The small WE (chip 1) is with the separated contact hole 90 connected.

The data input terminal D. (chip 201) is on separate contact hole 89.

The ground terminal V (chip 1) is connected to the ground

clamp V_ (chip 201) over the common contact hole s s

78 interconnected.

The chip release clamp CE (chip 1) and the chip release clamp CE (chip 201) are via the contact hole

79 interconnected.

The data input terminal D. (chip 1) lies at the separate contact hole 91.

The write enable terminal WE (chip 201) is connected to the separated contact hole 92.

The memory address A ₁₃ (chip 1) is connected to the separate contact hole 93.

The data output terminal D, (chip 201 is connected to the gQ separated contact hole 94.

The memory addresses A- * (chip 1) and A ₁₂ (chip 201) are interconnected via the (common) contact hole 80.

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The memory addresses A ₉ (chip 1) and A ₁₀ (chip 201) are interconnected via the contact hole 81.

The memory addresses A ₇ (chip 1) and Ag (chip 201) are interconnected via the contact hole 82. "

The memory addresses A ₅ (chip 1) and A ₅ (chip 201) are interconnected via the contact hole 83.

The memory addresses A ₃ (chip 1) and A ₄ (chip 201) are interconnected via the contact hole 84.

The memory addresses A ₁ (chip 1) and A ₃ (chip 201) are interconnected via the contact hole 85.

The current (feed) terminals Vcc (Chip 1) and Vcc (Chip 201) are interconnected via the contact hole 86.

The above analysis demonstrates that the invention actually to memory chips is applicable set forth _o How eignei, the memory address pins of the memory chip in an ideal way for interconnection (By connecting) by means of collection contact holes. In addition, the power (feed) and ground pins as well as the chip release pins of this chip are connected together.

QQ Although the opposing arrangement of chips related with the interconnection of selected pins of these chips via a composite connection pattern for memory chips is particularly suitable, the doctrine of the invention is based on practically any chip can be used.

It goes without saying that the invention is in no way limited to the embodiment shown and described above form, but accessible to various changes and modifications.

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Claims (7)

PATENT CLAIMS: (1.) Circuit board for holding a first and a second chips in opposite position, the circuit board having a first and a second Side and the two chips each have a plurality of pins, characterized by a first electrically conductive connection pattern disposed on the first side (152) of the circuit board (35) with a multitude of electrical conductor tracks, by a second, electrically conductive connection pattern (235) with a plurality of electrical conductor tracks and arranged on the second side (154) of the circuit board
by at least one electroplated, electrically conductive contact hole which penetrates the circuit board and electrically connects a first conductor run of the first connection pattern (35) to a first conductor run of the second connection pattern (235), a first pin of the first chip (1) to the first conductor run of the first connection pattern (35) is electrically connected and a first pin of the second chip (201) is electrically connected to the first conductor line of the second Artfechlußmuster (235), so that the contact hole forming a common or collective contact hole the first pin of the first Chip electrically connects to the first pin of the second chip. 2. circuit board according to claim 1, characterized in that the second connection pattern is substantially the same as the first connection pattern corresponds to the latter and is arranged rotated by 180 ° opposite and that the second chip with identical to the first chip and rotated or offset (flipped) by 1.80 ° with respect to the latter is. 3. circuit board according to claim 2, characterized in that numerous through-galvanized or -metallized contact holes (vias) each conductor run of the first connection pattern with one of the conductor runs of the second connection pattern associate. 4. circuit board according to claim 3, characterized in that each pin of the first chip with one of the conductor tracks of the first connection pattern and each pin of the second chip with one of the conductor tracks of the second connection pattern is soldered. 5. circuit board according to claim 4, characterized in that selected pins of the first chip have common or Collective vias are electrically connected to selected pins of the second chip. 6. circuit board according to claim 5, characterized in that it has several circuit layers and that the individual Contact holes are selectively electrically connected to one or more circuit layers. 7. Circuit board according to claim 5, characterized in that the first chip is a first memory chip with a first memory address pin that the second chip is a second memory chip with a first memory address pin is that the first chip with the second chip is identical and that the first memory address pin of the first memory chip has a common or Samme1 contact hole with the first Memory address pin of the second memory chip is interconnected.