DE3328405A1 - Steuerorgane eines fehlertoleranten mehrrechnersystems - Google Patents

Steuerorgane eines fehlertoleranten mehrrechnersystems

Info

Publication number
DE3328405A1
DE3328405A1 DE19833328405 DE3328405A DE3328405A1 DE 3328405 A1 DE3328405 A1 DE 3328405A1 DE 19833328405 DE19833328405 DE 19833328405 DE 3328405 A DE3328405 A DE 3328405A DE 3328405 A1 DE3328405 A1 DE 3328405A1
Authority
DE
Germany
Prior art keywords
bic
bus
csb
interface circuit
proc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19833328405
Other languages
German (de)
English (en)
Other versions
DE3328405C2 (enrdf_load_stackoverflow
Inventor
Klaus Dipl.-Ing. 8000 München Jung
Rudi Dipl.-Phys. Dr. 8038 Gröbenzell Müller
Hermann Dipl.-Ing. Reichbauer
Helmut Dipl.-Ing. 8000 München Schneider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to DE19833328405 priority Critical patent/DE3328405A1/de
Publication of DE3328405A1 publication Critical patent/DE3328405A1/de
Application granted granted Critical
Publication of DE3328405C2 publication Critical patent/DE3328405C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G06F11/1645—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components and the comparison itself uses redundant hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
DE19833328405 1983-08-05 1983-08-05 Steuerorgane eines fehlertoleranten mehrrechnersystems Granted DE3328405A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19833328405 DE3328405A1 (de) 1983-08-05 1983-08-05 Steuerorgane eines fehlertoleranten mehrrechnersystems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19833328405 DE3328405A1 (de) 1983-08-05 1983-08-05 Steuerorgane eines fehlertoleranten mehrrechnersystems

Publications (2)

Publication Number Publication Date
DE3328405A1 true DE3328405A1 (de) 1985-02-21
DE3328405C2 DE3328405C2 (enrdf_load_stackoverflow) 1992-01-30

Family

ID=6205936

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19833328405 Granted DE3328405A1 (de) 1983-08-05 1983-08-05 Steuerorgane eines fehlertoleranten mehrrechnersystems

Country Status (1)

Country Link
DE (1) DE3328405A1 (enrdf_load_stackoverflow)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0286856A1 (de) * 1987-04-16 1988-10-19 BBC Brown Boveri AG Fehlertolerante Rechneranordnung
EP0291382A1 (fr) * 1987-05-15 1988-11-17 Thomson-Csf Système de commutation numérique
EP0306348A3 (en) * 1987-09-04 1990-08-08 Digital Equipment Corporation Dual rail processors with error checking on i/o reads
EP0306209A3 (en) * 1987-09-04 1990-09-26 Digital Equipment Corporation Dual rail processors with error checking at single rail interfaces
EP0315303A3 (en) * 1987-09-04 1990-09-26 Digital Equipment Corporation Duplicated fault-tolerant computer system with error checking
US5068780A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones
US5153881A (en) * 1989-08-01 1992-10-06 Digital Equipment Corporation Method of handling errors in software
US5185877A (en) * 1987-09-04 1993-02-09 Digital Equipment Corporation Protocol for transfer of DMA data
EP0479230A3 (en) * 1990-10-05 1993-03-17 Bull Hn Information Systems Inc. Recovery method and apparatus for a pipelined processing unit of a multiprocessor system
US5251227A (en) * 1989-08-01 1993-10-05 Digital Equipment Corporation Targeted resets in a data processor including a trace memory to store transactions
DE9312739U1 (de) * 1993-08-25 1993-10-07 Siemens AG, 80333 München Redundantes Automatisierungssystem
WO1994002896A1 (en) * 1992-07-17 1994-02-03 Integrated Micro Products Limited A fault-tolerant computer system
WO1994008292A1 (en) * 1992-09-30 1994-04-14 Siemens Telecomunicazioni S.P.A. Duplicate control and processing unit for telecommunications equipment
EP0755010A1 (fr) * 1995-07-19 1997-01-22 Sextant Avionique Dispositif d'interface entre un calculateur à architecture redondante et un moyen de communication
EP0780774A1 (en) * 1995-12-18 1997-06-25 International Business Machines Corporation Logical address bus architecture for multiple processor systems
US5784547A (en) * 1995-03-16 1998-07-21 Abb Patent Gmbh Method for fault-tolerant communication under strictly real-time conditions
WO2000014636A3 (de) * 1998-09-09 2000-07-06 Daimler Chrysler Ag Vorrichtung und verfahren zur kopplung von redundanten elektronischen schaltungen über redundante busse ohne fehlerfortpflanzung
WO2002063472A3 (de) * 2001-02-08 2003-07-17 Siemens Ag Verfahren und vorrichtung zur datenübertragung mit wählbaren verfügbarkeitsmoden
EP2207097A1 (de) * 2009-01-07 2010-07-14 Robert Bosch GmbH Verfahren und Vorrichtung zum Betreiben eines Steuergerätes
CN117215177A (zh) * 2023-11-09 2023-12-12 北京控制工程研究所 一种天地往返一体化控制系统及控制方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3606281B2 (ja) * 2002-06-07 2005-01-05 オムロン株式会社 プログラマブルコントローラ及びｃｐｕユニット並びに特殊機能モジュール及び二重化処理方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2113935A1 (de) * 1971-03-23 1972-10-05 Licentia Gmbh Anordnung fuer ein Mehrrechnersystem
US4245344A (en) * 1979-04-02 1981-01-13 Rockwell International Corporation Processing system with dual buses

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2113935A1 (de) * 1971-03-23 1972-10-05 Licentia Gmbh Anordnung fuer ein Mehrrechnersystem
US4245344A (en) * 1979-04-02 1981-01-13 Rockwell International Corporation Processing system with dual buses

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
DE-Buch: Struktur und Betrieb von Rechen- systemen, NTG-Fachberichte, Bd.80, 1982, S.94-104 *
US-Z: Electronics, April 7,1983, S.159-164 *
US-Z: Electronics, Januar 27,1983,S.94-97 *

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH675781A5 (enrdf_load_stackoverflow) * 1987-04-16 1990-10-31 Bbc Brown Boveri & Cie
EP0286856A1 (de) * 1987-04-16 1988-10-19 BBC Brown Boveri AG Fehlertolerante Rechneranordnung
EP0291382A1 (fr) * 1987-05-15 1988-11-17 Thomson-Csf Système de commutation numérique
FR2615341A1 (fr) * 1987-05-15 1988-11-18 Thomson Csf Systeme de commutation numerique
US4866700A (en) * 1987-05-15 1989-09-12 Thomson-Csf Digital switching system
US5249187A (en) * 1987-09-04 1993-09-28 Digital Equipment Corporation Dual rail processors with error checking on I/O reads
EP0306211A3 (en) * 1987-09-04 1990-09-26 Digital Equipment Corporation Synchronized twin computer system
EP0306209A3 (en) * 1987-09-04 1990-09-26 Digital Equipment Corporation Dual rail processors with error checking at single rail interfaces
US5185877A (en) * 1987-09-04 1993-02-09 Digital Equipment Corporation Protocol for transfer of DMA data
EP0306348A3 (en) * 1987-09-04 1990-08-08 Digital Equipment Corporation Dual rail processors with error checking on i/o reads
EP0315303A3 (en) * 1987-09-04 1990-09-26 Digital Equipment Corporation Duplicated fault-tolerant computer system with error checking
US5068780A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones
US5153881A (en) * 1989-08-01 1992-10-06 Digital Equipment Corporation Method of handling errors in software
EP0414379A3 (en) * 1989-08-01 1993-02-24 Digital Equipment Corporation Method of handling errors in software
US5251227A (en) * 1989-08-01 1993-10-05 Digital Equipment Corporation Targeted resets in a data processor including a trace memory to store transactions
EP0479230A3 (en) * 1990-10-05 1993-03-17 Bull Hn Information Systems Inc. Recovery method and apparatus for a pipelined processing unit of a multiprocessor system
WO1994002896A1 (en) * 1992-07-17 1994-02-03 Integrated Micro Products Limited A fault-tolerant computer system
WO1994008292A1 (en) * 1992-09-30 1994-04-14 Siemens Telecomunicazioni S.P.A. Duplicate control and processing unit for telecommunications equipment
DE9312739U1 (de) * 1993-08-25 1993-10-07 Siemens AG, 80333 München Redundantes Automatisierungssystem
US5784547A (en) * 1995-03-16 1998-07-21 Abb Patent Gmbh Method for fault-tolerant communication under strictly real-time conditions
EP0755010A1 (fr) * 1995-07-19 1997-01-22 Sextant Avionique Dispositif d'interface entre un calculateur à architecture redondante et un moyen de communication
FR2737029A1 (fr) * 1995-07-19 1997-01-24 Sextant Avionique Dispositif d'interface entre un calculateur a architecture redondante et un moyen de communication
US5778206A (en) * 1995-07-19 1998-07-07 Sextant Avionique Device for interfacing between a redundant-architecture computer and a means of communication
EP0780774A1 (en) * 1995-12-18 1997-06-25 International Business Machines Corporation Logical address bus architecture for multiple processor systems
WO2000014636A3 (de) * 1998-09-09 2000-07-06 Daimler Chrysler Ag Vorrichtung und verfahren zur kopplung von redundanten elektronischen schaltungen über redundante busse ohne fehlerfortpflanzung
WO2002063472A3 (de) * 2001-02-08 2003-07-17 Siemens Ag Verfahren und vorrichtung zur datenübertragung mit wählbaren verfügbarkeitsmoden
EP2207097A1 (de) * 2009-01-07 2010-07-14 Robert Bosch GmbH Verfahren und Vorrichtung zum Betreiben eines Steuergerätes
CN117215177A (zh) * 2023-11-09 2023-12-12 北京控制工程研究所 一种天地往返一体化控制系统及控制方法

Also Published As

Publication number Publication date
DE3328405C2 (enrdf_load_stackoverflow) 1992-01-30

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Legal Events

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OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: G06F 11/16

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee