DE3322734C2 - Lead frames for contacting semiconductor chips with integrated circuits - Google Patents

Lead frames for contacting semiconductor chips with integrated circuits

Info

Publication number
DE3322734C2
DE3322734C2 DE3322734A DE3322734A DE3322734C2 DE 3322734 C2 DE3322734 C2 DE 3322734C2 DE 3322734 A DE3322734 A DE 3322734A DE 3322734 A DE3322734 A DE 3322734A DE 3322734 C2 DE3322734 C2 DE 3322734C2
Authority
DE
Germany
Prior art keywords
conductor strips
potting compound
connecting webs
potting
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3322734A
Other languages
German (de)
Other versions
DE3322734A1 (en
Inventor
Klaus-Jürgen Herrmann
Paul 7100 Heilbronn Hochschorner
Heinz 7102 Weinsberg Krauss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Germany GmbH
Original Assignee
Telefunken Electronic 7100 Heilbronn GmbH
Telefunken Electronic GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefunken Electronic 7100 Heilbronn GmbH, Telefunken Electronic GmbH filed Critical Telefunken Electronic 7100 Heilbronn GmbH
Priority to DE3322734A priority Critical patent/DE3322734C2/en
Publication of DE3322734A1 publication Critical patent/DE3322734A1/en
Application granted granted Critical
Publication of DE3322734C2 publication Critical patent/DE3322734C2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Bei mit Anschlußfahnen versehenen Schaltkreisstreifen (Stanzstreifen) für integrierte Schaltkreise tritt das Problem auf, daß das Freischneiden der Anschlußfahnen infolge des Austretens von Vergußmasse aus dem Gehäuse beim Spritzvorgang Schwierigkeiten macht und zu einem vorzeitigen Verschleiß des Stanzwerkzeugs führt. Um diese Unzulänglichkeit auszuschalten, wird vorgeschlagen, den Schaltkreisstreifen an den Austrittsstellen der die einzelnen Leiterbahnen voneinander isolierenden Vergußmasse aus dem Gehäuse jeweils mit wenigstens einer das Ausfließen der Vergußmasse hemmenden Barriere zu versehen, so daß ein vergußmassefreier Stanz- und Biegebereich am Dichtsteg erhalten wird (Fig. 4).In the case of circuit strips (punched strips) for integrated circuits provided with connection lugs, the problem arises that the cutting free of the connection lugs during the injection molding process as a result of the potting compound escaping from the housing makes difficulties and leads to premature wear of the punching tool. In order to eliminate this inadequacy, it is proposed to provide the circuit strips at the exit points of the sealing compound, which isolates the individual conductor tracks from one another, with at least one barrier that prevents the sealing compound from flowing out, so that a punching and bending area free of sealing compound is obtained on the sealing web (Fig . 4).

Description

Die Erfindung bezieht sich auf einen Leiterrahmen nach dem Oberbegriff des Anspruches 1. Ein derartiger Leiterrahmen ist aus der US-PS 39 50 140 bekannt.The invention relates to a lead frame according to the preamble of claim 1. Such a lead frame Lead frame is known from US-PS 39 50 140.

Bei dem bekannten Leiterrahmen sind die Verbindungsstege als Barrieren für die Vergußmasse beim Vergießen des Halbleiterchips und der inneren Abschnitte der Leiterstreifen vorgesehen. Da die Verbindungsstege nach dem Vergießen durch Freischneiden entfernt werden, schneiden die dabei eingesetzten Schneidwerkzeuge zwangsläufig auch die vor der Barriere angestaute Vergußmasse — es sei denn, die Vergußmasse-Segmente zwischen der Gehäusewand des Halbleiterbauelements und dem dem Gehäuse zugewandten Rand der Verbindungsstege wird zuvor in einem separaten Arbeitsgang entfernt.In the known lead frame, the connecting webs are used as barriers for the potting compound Potting of the semiconductor chip and the inner portions of the conductor strips provided. As the connecting webs are removed by cutting free after potting, cut those used Cutting tools inevitably also the potting compound built up in front of the barrier - unless the potting compound segments between the housing wall of the semiconductor component and the wall facing the housing The edge of the connecting webs is removed beforehand in a separate operation.

Der Erfindung liegt deshalb die Aufgabe zugrunde, den bekannten Leiterrahmen so zu verändern, daß beim späteren Freischneiden der Leiterstreifen bzw. Anschlußbeine das Freischneidewerkzeug nicht gehärtete Vergußmasse schneiden muß oder die ausgehärtete Vergußmasse in dem angegebenen Bereich vor dem Freischneiden durch einen zusätzlichen Arbeitsschritt entfernt werden muß.The invention is therefore based on the object to change the known lead frame so that when later cutting free of the conductor strips or connecting legs the free cutting tool not hardened Must cut potting compound or the hardened potting compound in the specified area before Free cutting must be removed by an additional work step.

Diese Aufgabe ist erfindungsgemäß durch einen Leiterrahmen nach den Merkmalen des Anspruches 1 gelöst. Bei diesem Leiterrahmen wird ein vergußmasseThis object is achieved according to the invention by a lead frame according to the features of claim 1. A potting compound is used for this lead frame

freier Stanz- und Biegebereich am Dichtsteg erreichtFree punching and bending area reached on the sealing web

Eine zweckmäßige Weiterbildung der Erfindung ist in dem Unteranspruch 2 angegeben.An expedient further development of the invention is specified in dependent claim 2.

Der Stand der Technik gemäß der US-PS 39 50 140 und ein Ausführungsbeispiel der Erfindung wird im nachstehenden anhand der Figuren erläutert Es zeigtThe prior art according to US-PS 39 50 140 and an embodiment of the invention is in explained below with reference to the figures. It shows

F i g. 1 eine Draufsicht auf einen mit einem Halbleiterchip versehenen Leiterrahmen bekannter Ausführung. Im Bereich zwischen je zwei Anschlußfahnen befindet ίο sich außerhalb des Gehäuses (strichpunktierte Begrenzung) ausgeflossene Vergußmasse (punktiert),F i g. 1 shows a plan view of a leadframe of known design provided with a semiconductor chip. In the area between each two connection lugs ίο is outside the housing (dash-dotted border) poured sealing compound (dotted),

F i g. 2 den mit einem Gehäuse versehenen Leiterrahmen entsprechend F i g. 1 in perspektivischer Darstellung, F i g. 2 the lead frame provided with a housing according to FIG. 1 in a perspective view,

F i g. 3 das Bauelement in gebrauchsfertigem Zustand, F i g. 4 eine Draufsicht auf einen Leiterrahmen gemäß einem Ausführungsbeispiel der Erfindung,F i g. 3 the component in a ready-to-use condition, F i g. 4 shows a plan view of a lead frame according to an exemplary embodiment of the invention;

Fig.5 den von einem Gehäuse umschlossenen Schaltkreisstreifen entsprechend F i g. 4,
F i g. 6 das gebrauchsfertige Bauelement mit freigeschnittenen und in die endgültige Lage gebogenen Anschlußfahnen. 5 shows the circuit strip enclosed by a housing according to FIG. 4,
F i g. 6 the ready-to-use component with terminal lugs cut free and bent into the final position.

Wie aus F i g. 1 ersichtlich ist, ist auf Leiterrahmen 1 der Halbleiterchip 2 mit seinen Anschlüssen 3 und den diesen zugeordneten Leiterstreifen 4 aufgebracht, welche jeweils in Anschlußbeinen 5 übergehen. Beim Ausgießen der Zwischenräume 6 zwischen den einzelnen Leiterbahnen 4, das in einem-Arbeitsgang und in einer zweiteiügen Gießform mit dem Gießen des Gehäuses 7 (siehe auch F i g. 2) erfolgt, breitet sich infolge des Preßdrucks Vergußmasse (Epoxydharz, Silikonmasse oder dergl.) jeweils zwischen den oberen und unteren Teil der Gießform und zwischen benachbarten Leiterstreifen bzw. Anschlußbeinen 5 in einem dünnen, der'Dicke des Leiterrahmen entsprechenden Strang aus, bis dieser Strang auf den noch innerhalb der Gießform liegenden, als Barriere gegen den Austritt von Vergußmasse wirkenden Verbindungslinie 15 trifft.As shown in FIG. 1 can be seen is on ladder frame 1 applied to the semiconductor chip 2 with its connections 3 and the conductor strips 4 assigned to them, which merge into connecting legs 5 in each case. When pouring out the spaces 6 between the individual Conductor tracks 4, which in one operation and in a two-part casting mold with the casting of the housing 7 (see also Fig. 2) takes place, spreads as a result of the pressing pressure casting compound (epoxy resin, silicone compound or The like.) each between the upper and lower part of the mold and between adjacent conductor strips or connecting legs 5 in a thin strand corresponding to the thickness of the leadframe, until this Strand on the still lying within the casting mold, acting as a barrier against the escape of potting compound Connection line 15 meets.

Dabei entstehen Vergußmassesegmente 9 weiche das Freischneiden der Anschlußfahnen 5 entlang der gestrichelt angedeuteten Schnittkanten 10 behindern und die Lebensdauer des Freischneidwerkzeugs beträchtlich reduzieren. This creates casting compound segments 9 soft the cutting free of the terminal lugs 5 along the dashed line impede indicated cutting edges 10 and reduce the service life of the clearing tool considerably.

In F i g. 3 ist dieses Bauelement mit freigeschnittenen und abgebogenen Anschlußfahnen 4 dargestellt. In diesem Zustand ist das Bauelement gebrauchsfertig. Mit 11 sind hier Kühlfahnen bezeichnet.In Fig. 3 shows this component with terminal lugs 4 cut free and bent off. In this The component is ready for use. With 11 cooling vanes are referred to here.

Bei den Leiterrahmen Γ gemäß Fig.4 sind die Barrieren 12 als T-förmige Zungen ausgebildet. Diese Barrieren werden bei der Herstellung des Leiterrahmens Γ gleich mit eingestanzt bzw. eingeschnitten und danach in die Ausgangslage, das heißt in die Ursprungsebene, zurückgedrückt. Dabei werden zweckmäßigerweise erst die rechteckförmigen Ausnehmungen 13 ausgestanzt und danach die Einschnitte 14 angebracht.In the case of the ladder frames Γ according to FIG. 4, the barriers are 12 designed as T-shaped tongues. These barriers are used in the manufacture of the lead frame Γ punched or cut at the same time and then in the starting position, i.e. in the original plane, pushed back. The rectangular recesses 13 are expediently punched out first and then the incisions 14 made.

Durch derart ausgebildete Barrieren 12 an den denBy so formed barriers 12 to the

Freischnitt vorgesehenen Verbindungsstegen 14 wird erreicht, daß nach dem Gießen beim Freischneiden das dafür benutzten Werkzeug nicht mit der ausgehärteten Gießmasse in Berührung kommt.Free cut provided connecting webs 14 is achieved that after the casting during free cutting the The tool used for this does not come into contact with the hardened casting compound.

Ein fertiges Halbleiterbauelement unter Verwendung eines Leiterrahmens Γ entsprechend Fig.4 veranschaulicht F i g. 5, während F i g. 6 dasselbe Bauelement mit freigeschnittenen und abgebogenen Anschlußfahnen 5 zeigt. Der jeweils die Barriere bzw. Zunge 12 enthaltende Freischnittabfall ist hier separat dargestellt und mit 16 bezeichnet.
Die Aussparungen 13 an den Barrieren 12 könnenA finished semiconductor component using a lead frame Γ according to FIG. 4 is illustrated by FIG. 5, while F i g. 6 shows the same component with terminal lugs 5 cut free and bent. The cut-off waste containing the barrier or tongue 12 is shown separately here and denoted by 16.
The recesses 13 on the barriers 12 can

auch durch Ätzen hergestellt werden. Dies erweist sich dann als zweckmäßig, wenn auch der Leiterrahmen durch Ätzen hergestellt istcan also be made by etching. This turns out to be then as expedient if the lead frame is also made by etching

Hierzu 4 Blatt ZeichnungenFor this purpose 4 sheets of drawings

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Claims (2)

Patentansprüche:Patent claims: 1. Leiterrahmen (1, 1') aus einem ebenen Blechstreifen, zur Kontaktierung von Halbleiterchips (2) mit integrierten Schaltungen, wobei der Leiterrahmen Leiterstreifen, welche mit ihren inneren Enden die Halbleiterplättchen kontaktieren, und Verbindungsstege (15) aufweist, welche die Leiterstreifen (5) vor und beim Vergießen des Halbleiterplättchens (2) und der inneren Abschnitte der Leiterstreifen (5) mit einer aushärtbaren Vergußmasse zusammenhalten und von denen die den inneren Enden der Leiterstreifen (5) am nächsten gelegenen Verbindungsstege (15) mit ihren den inneren Enden der Leiterstreifen (5) zugewandten Rändern gerade außerhalb des aus gehärteter Vergußmasse bestehenden Gehäuses der fertigen Halbleiterbauelementes mit dem Leiterrahmen angeordnet sind und wobei diese Verbindungsstege (15) ferner so ausgebildet sind, daß sie beim Vergießen als Barriere für die Vergußmasse wirksam sind, indem sie das Ausfließen der noch nicht ausgehärteten Vergußmasse aus der beim Gießen verwendeten Form verhindern, dadurch gekennzeichnet, daß die Verbindungsstege (15) jeweils senkrecht zu deren den inneren Enden der Leiterstreifen (5) zugewandten Rändern und entlang der Ränder der äußeren Abschnitte der den Verbindungsstegen (15) benachbarten Leiterstreifen (5), welche bei dem fertigen Halbleiterbauelement die Anschlußbeine (5) sind, zwei Einschnitte (14) und im Anschluß daran in Richtung auf die äußeren Enden der Leiterstreifen (5) zwei Löcher (13) aufweisen, so daß eine T-förmige Zunge ab Barriere für die Vergußmasse ausgebildet ist.1. Lead frame (1, 1 ') made of a flat sheet metal strip, for contacting semiconductor chips (2) with integrated circuits, the leadframe having conductor strips with their inner ends contact the semiconductor die, and connecting webs (15), which the conductor strips (5) before and during potting of the semiconductor die (2) and the inner sections of the conductor strips (5) hold together with a hardenable potting compound and of which the inner ends of the conductor strips (5) the closest connecting webs (15) with their inner ends of the conductor strips (5) facing edges just outside of the hardened potting compound housing the finished semiconductor component are arranged with the leadframe and these connecting webs (15) are also designed so that they act as a barrier for the potting compound when potting are effective by preventing the not yet hardened potting compound from flowing out of the during pouring prevent the shape used, characterized in that the connecting webs (15) each perpendicular to their edges facing the inner ends of the conductor strips (5) and along them the edges of the outer sections of the conductor strips (5) adjacent to the connecting webs (15), which in the finished semiconductor component are the connecting legs (5), two incisions (14) and in the Connection to it in the direction of the outer ends of the conductor strips (5) have two holes (13), so that a T-shaped tongue is formed from the barrier for the potting compound. 2. Leiterrahmen nach Anspruch 1, dadurch gekennzeichnet, daß die Löcher (13) rechteckförmig sind.2. Lead frame according to claim 1, characterized in that the holes (13) are rectangular are.
DE3322734A 1983-06-24 1983-06-24 Lead frames for contacting semiconductor chips with integrated circuits Expired DE3322734C2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE3322734A DE3322734C2 (en) 1983-06-24 1983-06-24 Lead frames for contacting semiconductor chips with integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3322734A DE3322734C2 (en) 1983-06-24 1983-06-24 Lead frames for contacting semiconductor chips with integrated circuits

Publications (2)

Publication Number Publication Date
DE3322734A1 DE3322734A1 (en) 1985-01-10
DE3322734C2 true DE3322734C2 (en) 1985-09-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE3322734A Expired DE3322734C2 (en) 1983-06-24 1983-06-24 Lead frames for contacting semiconductor chips with integrated circuits

Country Status (1)

Country Link
DE (1) DE3322734C2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2612448A1 (en) * 1987-10-01 1988-09-23 Asm Fico Conductor frame for the flashless moulding of embedded metal elements, and method relating thereto
US8169069B2 (en) 2006-12-05 2012-05-01 Infineon Technologies Ag Integrated semiconductor outline package

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3950140A (en) * 1973-06-11 1976-04-13 Motorola, Inc. Combination strip frame for semiconductive device and gate for molding

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