DE3303662A1 - HIGH RESOLUTION TIMER - Google Patents

Description

SIEMENS AKTIENGESELLSCHAFT Our reference Berlin and Munich VPA 83 P 1 04 6 OE

High resolution timer
5

The invention relates to a high resolution timer using a counter provided by counting clocks delivered to an oscillator and the content of which is a measure of the time at which the counter ^ processing from a first, which includes the lower-order counting positions, the counting cycle counting counter part and from a second, the higher-valued counting positions comprehensive and with the most significant counting point output of the first counter

partly connected meter part exists. 15th

For process control or internal timing Processes require computer systems a timer, also called a real-time clock, high resolution. Even short intervals To be able to measure, measurements must be possible in quick succession. It causes problems to read out the time, without disturbing the timing of the timer.

Such timers usually consist of a counter, the counting clocks of a certain frequency supplied by an oscillator counts and their content is a measure for the expired Time is. The counting device can consist of several counter parts, with a first counter part the lower-order counting places, the higher-order counting places are contained in a second part of the counter and the most significant count output of the first part of the counter is connected to the input of the second counter part.

To timer high resolution to realize a counter can be used, which is ³ ^ low degree of integration of fast blocks. However, this leads to complex, expensive solutions. The use of cheap MOS microprocessors, for example, fails because of the high frequencies.

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zen caused by the high resolution requirements of computer systems are conditional.

The underlying task of the invention is to provide a high resolution timer using a counter in which the time is read out can without disturbing the operation of the timer and its implementation is nevertheless not expensive. This task is achieved in a timer of the type specified in that the first in a fast circuit technology implemented counter part consisting of a first counter for the low-order counting positions and an intermediate register exists, in which the content of the first counter is synchronous with the counter clock, but shifted in phase occurring takeover clock can be taken over, and that the second realized in a slower circuit technology Counter part consists of a microprocessor, with the internal counter and register a second counter for the Form higher-value counting points and the content of the when there is a timekeeping request from a consumer Intermediate register of the first counter part takes over and this content together with the content of the second counter gives the requesting consumer.

The first counter part can expediently be implemented in TTL technology, while the second counter part, that is to say the Microprocessor, realized in MOS technology.

The intermediate register in the first part of the counter thus takes over the content of the first in a phase-shifted manner to the counter clock Counter with the help of the transfer rate. There is a timekeeping requirement from a consumer before, then the transfer clock with the help of a bistable toggle switch, the is arranged between the oscillator and the first part of the counter, switched off briefly, and the content of the intermediate register

sters taken over into the microprocessor. After the contents of the intermediate register have been transferred to the microprocessor,

. gives the microprocessor

the bistable flip-flop is released again, so that the takeover clocks can act on the intermediate register again.

It is advantageous to have between the microprocessor and the Consumers to arrange a buffer memory in which the microprocessor in the event of a timekeeping request

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Counting result transmits, and from the consumer with a Readout cycle supplied by the consumer can take over the counting result.

In another exemplary embodiment, the intermediate register can be a first-in / first-out buffer memory. With With the help of an arrangement for switching the transfer clock through to the buffer memory, this is only then sent to the release input of the buffer memory is applied when the first counter indicates a carry or when a timing request from a consumer.

In this embodiment, the microprocessor is always on the content of the buffer memory and increases the content of the second counter by one unit when the one read out Counter content is 0.

Other developments of the invention emerge from the subclaims.

On the basis of exemplary embodiments that are shown in the figures are, the invention is further explained. Show it

Figure 1 is a block diagram of a first embodiment of the timer according to the invention, FIG. 2 the circuit diagram of the timer of FIG. 1,

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Figure 3 shows a second embodiment of the timer,

Figure 4 shows a third embodiment of the timer,

FIG. 5 shows a pulse diagram plotted against time t,

by following the different parts of the timer

Figure 4 occurring pulses are shown.

The block diagram of a timer shown in FIG. 1 contains an oscillator OS which generates a clock signal of 6 MHz for a microprocessor MP and a counting clock of 1 MHz for the counter. The counting device consists of a first counter part ZA1 and a second counter part, which is contained in the microprocessor MP. A bistable multivibrator FF is connected between the oscillator OS and the first counter part ZA1 and can be reset by a time-taking request REQ from a consumer or set by a signal from the microprocessor MP. From the count clock Si _V on a 1 MHz transfer clock $ 2 is namely obtained that is out of phase with the count clock. This transfer clock ^S 2 can be interrupted with the help of the bistable flip-flop'FF. The transfer clock S2 is also applied to the first counter part ZA1 and causes an intermediate register contained in the first counter part ZA1 to accept the content of the first counter also contained in the first counter part ZA1.

The content of the intermediate register in the first counter part ZA1 can be transferred to the microprocessor MP via a bus ZR. The output of the most significant count of the first Counter part ZA1 is applied to an input T1 of the microprocessor MP, from which it is connected to the input of the internal Counter or second counter part is applied in the microprocessor MP.

Finally, a buffer memory PF can be arranged between the consumer and the microprocessor MP.

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According to a timing request REQ, the content of the counting device is transmitted via a bus DBI and from the this counting result can be read out to the consumer with the aid of a readout pulse AT supplied by the consumer can. The counting result is transmitted via the DBA bus. ben. The consumer is informed via a control line DAR, that the data to be read is available.

The microprocessor MP is notified at the input INT if a timing request REQ is present in order to cause the microprocessor MP to read in the content of the first counter part ZA1. When this is done, he gives. Microprocessor MP at output P27 a signal that the bistable trigger circuit FF sets again and thus applies the transfer clock S2 again to the first counting device ZA1.

An exact implementation of the timer according to FIG. 1 is shown in FIG. 2. Here, first of all, the structure of the oscillator is shown OS shown. This contains an oscillating crystal SQ, which e.g. generates clock signals TS with a frequency of 6 MHz. These Clock signals are fed via an inverter to a counter Z1, which has the frequency output by the quartz oscillator SQ 6 MHz is converted into a frequency of 1 MHz. The counter clocks S1 are thus output at the output of the counter Z1. The clock signals TS or the inverted clock signals TS "are fed to the microprocessor MP, specifically to the inputs XTAL1 or XTAL2 of the microprocessor MP. A SAB 8748 module is selected as the MP microprocessor.

The transfer clocks S2 are obtained from the counting clocks S1 with the aid of a delay circuit VZ, which consists of NAND elements is constructed. The transfer clocks S2 occur synchronously with the counting clocks S1, but are opposite to these counting clocks S1 out of phase. The transfer clocks S2 can finally with the help of the NAND gate ND1 of the delay

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circuit VZ are switched off.

The takeover clocks S2 are switched off via the NAND element ND1 with the aid of the bistable multivibrator FF. Of the The set input of the flip-flop FF is connected to the output P27 of the microprocessor MP. At the reset. The input of the bistable multivibrator FF is a timing request signal REQ on. As long as no timing is requested, the flip-flop FF is set and thus the NAND element ND1 is released, so that the transfer clocks S2 are output at the output of the delay circuit VZ will. If, on the other hand, a time measurement request REQ occurs from a consumer, the bistable multivibrator is activated FF is reset and thus the NAND element ND1 is blocked. Thus, the occurrence of the transfer clocks S2 at the output of the Delay circuit VZ prevented. At the same time, a signal is applied to the INT input of the MP microprocessor, which informs the microprocessor MP that there is a timekeeping request from a consumer.

The counting clocks S1 and the transfer clocks S2 are fed to the first counter part ZA1. The first counter part is ZA1 realized in TTL technology and takes the lower-valued counting places on. In Figure 2 it consists of two parts Z2 and Z3. Each part Z2 or Z3 has four counting positions, so that the entire counter part ZA1 has eight counting positions. The components Z2 and Z3 can e.g. synchronous binary counters 74 LS 691 each containing an intermediate register. The modules Z2 and Z3 of the first counter part ZA1, both the counting clocks S1 and the transfer clocks S2 are supplied. The modules Z2 and Z3 are usually one Counters summarized. The carry given by block Z2 "Carry" is fed to the release input EN of the component Z3. The components Z2 and Z3 are on buses ZR with connected to microprocessor MP via which the Sah! content in

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the microprocessor MP can be transferred. The content of the intermediate register depends on the counter of the transfer clock S2 has been transferred to the microprocessor MP at the inputs P10 to P13 and P14 to Transfer P17. The output of the most significant counting point of the first counter part ZA1 is still at input T1 of the Microprocessor MP applied. The signals appearing at this input T1 become the internal counter of the microprocessor MP counted up. The internal counter of the microprocessor MP or the second part of the counter consists of the internal counter and internal registers of the microprocessor MP. The second part of the counter can e.g. consist of the internal counter and five registers exist. Then the internal or second counter part would have a width of 48 bits and the entire counter one Width of 56 bits.

The transfer of the content of the first counter part ZA1 in the Microprocessor MP can be triggered by a signal at output P21. This signal at output P21 will then occur when there is a REQ timing request or a signal at the TfTT input on the microprocessor.

The interconnection of the buffer memory PF with the microprocessor MP is shown in Figure 2. A WD 1510-01 module can be selected as the microprocessor. With the help of Signal at output P24, the microprocessor MP can determine the direction in which the data are transmitted. Should while data are transferred from the microprocessor MP into the buffer memory PF, this is sent to the buffer memory PF on Communicated to input DIR and then a release signal applied to input CSA. Then the data, i.e. the counter content, transferred to the buffer memory PF via the bus DBI will.

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via the DAR line, which is connected to output P25, the consumer is informed that the data, the counting result, is available in the buffer memory. The consumer can then call up the data via the bus DBA with the readout pulse AT, which is present at the release input CSB.

The other connections shown in Figure 2 between the individual modules are known and can be found in the data sheets for the relevant modules.

Assuming that the counting rate is 1 MHz, the resolution of the counting device is 1. usec. It is expedient Transfer cycle S2 occur 500 ns after the count cycle S 1 allow. The transfer clock S'1 then occurs at a point in time at which the counter in the first counter part is already has come to rest. Only now can the content of the counter be transferred to the intermediate register. The counter counts the counting clocks without being disturbed by the transfer of the contents of the counter into the intermediate register would. When a timekeeping request occurs, the transfer cycle S2 is blocked, but for a maximum of half Time between two overflows of the first part of the counter. Through this it is prevented that during the transfer of the contents of the first counter part in the microprocessor MP a second Counter part in the microprocessor MP increasing transfer on Input T1 is suppressed.

A further embodiment of the timer results from FIG. An oscillator OS generates a clock from both 6 MHz for a microprocessor MP as well as a counting clock S.1 for the counting device. The oscillator OS can accordingly Figure 2 be realized. The counting clock S1 is fed to a counter Z4, which together with the intermediate register ZW forms the first part of the counter. The intermediate register ZW can be implemented as a first-in / first-out memory and consist of the WD 1510-01 module.

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The content of the counter Z4 is then transferred to the intermediate register ZW when a count carry ZU occurs at the counter Z4 or a timing request REQ is pending. A carry ZU at the counter Z4 is on a negative edge of the bit 2 ^{7 of} the counter Z4 fe
there is eight counting positions.

Bits 2 of counter Z4 detected when counter Z4 is off

The carry signal ZU and the timing request signal REQ is used to control an arrangement for switching through the transfer clock S2 to the intermediate register ZW.

The arrangement for switching through the transfer clock S2 consists of monostable multivibrators M1 and M2, a counter 15, NOR elements NR1 to NR3 and an inverter IN.

The monostable multivibrator M2 generates a pulse P1 of e.g. 800 ns from the carry signal ZU from the counter Z4. This first pulse P1 is fed to the NOR element NR1 and from there to the NOR element NR2, whereby the transfer clock S2 is applied to the release input CSA of the intermediate register ZW. This means that the content of counter Z4 is transferred to the Intermediate register ZW accepted. At this point in time, the content of counter Z4 is binary 0 on all counting positions a timekeeping request REQ from a consumer, then the monostable multivibrator M1 generates a pulse P2 of e.g. 100 ns from the trailing edge of the assigned signal Length. The counter Z5 is reset with the pulse P2. The counter Z5 is then over by the next counting cycle S1 the NOR element NR3 is controlled at the counter input and thus the Counting point 2 binary 1. This means that pulse P3 appears at the output of counting point 2 °, which is sent to NOR via the NOR element NR1 Member NR2 is supplied, whereby the transfer clock S2 is again applied to the release input CSA of the intermediate register ZW will. This reads the content of the counter Z4 into the intermediate register ZW. With the next counting cycle S1 the counting point 2 'of the counter Z5 is set, which with the

NOR element NR3 is connected, which is also supplied with the counting clock S1 will. This prevents further counting clocks S1 from reaching counter Z5.

The content of the counter Z4 is only then in the intermediate register ZW transmitted when either a counter carry ZU or a timekeeping request REQ is present. Because only then is the transfer clock S2 applied to the intermediate register ZW. Since the output 2 of the counter Z5 also with is directly connected to the intermediate register ZW, for each counting result transferred to the intermediate register ZW from the counter Z4 also entered whether the reason for the takeover was a REQ timekeeping request.

The microprocessor MP is connected to the output of the intermediate register ZW via the bus ZR and reads continuously Signals at the release input CSB the contents of the intermediate register ZW as long as the intermediate register ZW is not empty is. The microprocessor MP recognizes an overflow ZU

20- at the counter reading 0 and increases the internal part of the counter, i.e. the second part of the counter, which contains the high-quality counting positions contains to one unit. Recognizes the microprocessor MP at the input TO from the content of the accepted result from the intermediate register ZW that a timing request REQ has led to the acceptance of the counter result, then causes the microprocessor MP the transfer of the counting result, so the summary of the counting result from Counter Z4 and from the internal counter, via the bus DB to the requesting one Consumer.

The timer according to FIG. 4 differs from FIG. 3 in that it is connected to the output of the monostable multivibrator M2 another counter Z6 is switched on. The output 2 ° of the counter Z6 is connected to a NOR element NR4, to which the counting clock S1 is also fed. The Aus

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The output of the NOR element NR4 is then applied to the counter input of the counter Z6. With the help of the output of the monostable multivibrator M2 emitted pulse P1, the counter Z6 is reset and then set again by the counter clock S 1.

Only now does the pulse P4 appear at the output of the counter Z6 synchronously with the counter clock Si, which enables the NOR element NR2 so that the next transfer clock S2 can reach the enable input CSA of the intermediate register ZW. By inserting the counter Z6, a synchronization of the pulse P4, which is triggered by the carry signal ZU, to the counting clock S1 is achieved. The rest of the circuit corresponds to that of Figure 3, except for the exception that are provided for forming a delay circuit VZ for generating the acceptance clock signal S2 from the counting pulse ^S 1 is still further inverter limbs.

The sequence in which the individual pulses appear in FIG. 4 is shown in FIG. 5. Here is the first Line of the counting clock S1 is shown. The counting cycle becomes Si With the help of the delay circuit VZ, the transfer clock $ 2 generated, the phase shifted by the time TO compared to the counting clock Si is. The third line shows the course of the pulse P4 at the output of the counter Z6. It is to see that after triggering by the carry signal ZU the edges of the pulse P4 at the time of the trailing edges of the counting cycle S1 occur. '-:

The fourth line of Figure 5 shows the course of the pulse P3 at the output of the counter Z5. Prerequisite for its occurrence is the concern of a timing request signal REQ. It can be seen that the edges of the pulse P3 also occur with the trailing edges of the counting clock Si.

The impulses P3 and P4 determine when the takeover cycle takes place S2 to the trigger input CsA of the intermediate regulator ^ i-

sters ZW is present. The course of the signal at the input cSA of the intermediate register ZW is shown in the last line of FIG shown. The triggering edges are the pulse edges shown with AF. These occur synchronously with the edges of the takeover signal S2 on.

An advantage of the embodiments of Figure 3 and Figure 4 compared to the embodiment of Figure 1 and Figure 2 is that the measurement repetition rate is considerable is bigger.

10 claims
5 figures

Claims (10)

Claims High resolution Q / timer using a Counting device that counts the counting clocks supplied by an oscillator and the content of which is a measure of time, in which the counting device consists of a first counter part that counts the counting cycle and includes the lower-order counters and from a second, comprising the higher-order counting positions, with the most significant counting position output of the first counter part connected counter part, characterized in that the first in a fast circuit technology implemented counter part (ZA1 or Z4, ZW) from a first counter (Z4) for the lower ones Counting places and an intermediate register (ZW) that the content of the first counter is dependent a takeover clock (S2) that occurs synchronously but out of phase with the counting clock (Si) can be taken over, and that the second part of the counter, implemented in slower circuit technology, consists of a microprocessor (MP), in which the internal counter and register form a second counter for the more significant counter digits and the when creating a timekeeping request (REQ) from a consumer takes over the content of the intermediate register of the first counter part and this content together with the content of the second meter to the requesting consumer. 2. Timer according to claim 1, characterized in that the first counter part (ZA1 or Z4, ZW) in TTL technology and the second part of the counter (MP) is implemented in MOS technology. 3. Timer according to claim 1 or 2, characterized in that g e k e η η draws that between oscillator (OS) and the first Counter part (ZA1 or Z4, ZW) a delay circuit: (VZ) -H- VPA 83 P 1 0 46 DE is arranged to generate the transfer clock (S2) from the counting clock (S1). 4. Timer according to claim 3, characterized in that g e k e η η draws that a bistable flip-flop (FF) is provided, which when there is a timing request (REQ) blocks the output of the delay circuit (VZ) and later enables the delay circuit after the timekeeping request has been processed by the microprocessor (MP). 5. Timer according to one of claims 1 to 4, characterized characterized in that a buffer memory (PF) is arranged between the microprocessor (MP) and the consumer, in which the microprocessor transmits the counting result when there is a timing request (REQ) and from which the Consumer with a readout cycle (AT) takes over the counting result. 6. Timer according to claim 1 or 2, characterized ge indicates that the intermediate register (ZW) consists of a first-in / first-out memory that the A delay circuit (VZ) is connected downstream of the oscillator (OS), which turns the counting clock (S1) into the transfer clock (S2) generated, and that an arrangement for switching through the transfer clock to the intermediate register (ZW), which sends the transfer clock (S2) to the release input (CSA) of the intermediate register applies when the first counter (Z4) indicates a carry (ZU) or when a time measurement request (REQ) is present. 7. Timer according to claim 6, marked net by the arrangement of a first monostable Toggle circuit (M2) to which the carry signal (ZU) of the first counter (Z4) is applied and which generates a first Pulse (P1) generated from a second monostable toggle -H- VPA 33 ρ 10 4 6 OE circuit (Μ1) to which. the timekeeping request (REQ) is pending and which generates a second pulse (P2) therefrom, from a third counter (Z5) to whose reset input the second pulse (P2) is applied, the counting input of which is connected to the oscillator (OS) and the 2 output of the third counter connected NOR element (NR3) is connected and its 2 output emits a third pulse (P3) and from a Logic circuit (NR1, NR2) to which the transfer clock (S2) and the first and third pulses (P1, P3) are applied and which sends a signal for the intermediate register (ZW) synchronously to the transfer clock for transferring the content of the first slave (Z4) generated when either a carry signal (ZU) or a timing request (REQ) is present. 8. Timer according to claim 7, characterized in that g e k e η η that between the first monostable Toggle circuit (M2) and the logic circuit (NR1.NR2) a fourth counter (Z6) is arranged, the reset input of which with the output of the first monostable multivibrator (M1) is connected, the counting input of which is connected to the oscillator (OS) and the 2 output of the fourth counter (Z6) connected NOR element (NR4) is connected and the pulse to be fed to the logic circuit at the 2 output (P4) generated. 9. timer according to claim 7 or 8, characterized ge indicates that the 2 output of the third counter (Z5) connects directly to the input for a memory location of the intermediate register (ZW) is connected. 10. Timer according to one of claims 6 to 9, characterized g e k e η η indicates that the microprocessor (MP) constantly reads out the counter contents written into the intermediate register (ZW) and the second if the counter contents are 0 Counter content increased by one unit.