DE3302744A1 - Clocked pulse generator - Google Patents

Abstract

A clocked pulse generator for generating pulses (Q), the presettable duration of which, lasting several clock pulse periods (Os), is largely determined by a presettable counter (Z) which counts clock pulses and which is started by the front edge of a first clock pulse. For the prior stepped fine setting of the pulse duration, which may be required, the counter (Z), after reaching its maximum count previously specified (by means of W1/R1), forwards its output signal (a) via a delay section (PV), which can be finely preset (digitally by means of W2/R2), to an output stage (D-FF2) which switches off and ends the pulse. <IMAGE>

Description

SIEMENS AKTIENGESELLSCHAFT '<* - "Our reference: Berlin and Munich VPA 83 ρ 10 3 1 OE

Clock controlled pulse generator.

The invention represents a further development of the particular specified in the preamble of claim 1 Pulse generator. Such pulse generators are familiar to the person skilled in the art, and there it is an arrangement acts in which between the beginning of the transmitted pulse and the end of the transmitted one Pulse, a (time) counter runs, the counter reading of which is the trailing edge of the transmitted pulse and thus the Impulse duration, at least largely, determines.

The invention has been preferred for testing magnetic bubble accumulators developed. However, it is also generally suitable for other applications, where the duration of relatively long-lasting impulses, e.g. also several microseconds long pulses, extremely precise, e.g. can be set to within a few nanoseconds in advance target.

The object of the invention is namely to determine the duration of the transmitted pulses extremely precisely in advance to be able to adjust, preferably to be able to adjust extremely finely as desired by means of digital commands.

·

This object is achieved by the combination of measures specified in the claim.

The invention is described in more detail with reference to the figure, which shows the block diagram of an embodiment in which the presetting of the pulse duration

Be 1 Ky / 01/24/83

- VPA 83 ρ 1 03 1 DE

digitally, for example in steps of 1 or 10 nanoseconds each. The steps are therefore shorter than they are possible, for example, with the usual TTL Schottky circuits, in which the shortest resolutions are generally approx. 40 nanoseconds, corresponding to 25 MHz.

In the example shown in the figure, a is relative Slow counter Z attached, which counts the number of clock pulses sent by the oscillator Os, which e.g. have a pulse repetition rate of 1 MHz, counts. This is, for example, a counter in TTL technology, Of course, other pulse repetition frequencies are also possible, e.g. 12.5 MHz.

If the start signal St is supplied, this start signal is synchronously with the leading edge of a clock pulse of the oscillator Os, in the monostable flip-flop D-FF1 accepted - this flip-flop is monostable because its output has a delay element VZ with is fed back to one of its inputs. This monostable flip-flop D-FF1 then sets the output stage D-FF2 into the ON state, so that from now on the Q / Q pulse to be emitted begins.

The counter Z now continues to count the number of clock pulses until its counter reading is the same as that previously in Register R1 with a write signal W1 stored, predetermined amount. Namely, in the comparator V becomes the respective counter reading of the counter Z is continuously compared with the value stored in register R1. With the help of this register R1, a first setting of the duration of the pulses Q / Q to be emitted is set to on Integer multiple of the period of the clock pulses of the oscillator Os is set. Here the

- f '* " ^VPA 83P 103 1 DE

The value ¥ 1 stored in register R1 is preferably selected to be slightly smaller than the exact desired value Corresponds to the duration of the pulse to be emitted Q / Q.

The difference between the exact desired value of the duration of the Q / Q pulse to be emitted and that of the value According to the invention, the duration corresponding to W1 is determined with the aid of the digital, finely presettable delay path PV set. This delay path PV delays namely that of the counter after reaching the counter reading ¥ 1 emitted, output signal a by a slight value, the size of which with the help of the delay path PV is determined. For this purpose, a value W2 is written into register R2, e.g. a three-digit binary-coded one Value for eight different delay values between 10 and 80 nanoseconds, with the output signal a after Finally, run through the delay path PV in accordance with the delay preset using V2 / R2 resets the output stage D-FF2 and thus defines the trailing edge of the Q / Q pulse to be emitted. at The delay line PV can, for example, be the commercially available 'programmable delay lines (programmable delay line), i.e. a component that normally has an input for the output signal a, as well as e.g. three SET inputs for the preset of the delay time stored in register R2 has defining value W2 and which contains e.g. RC elements in its interior that correspond to the SET inputs or according to the value W2 are inserted or bridged in the path, whereby fine presettings of the delay of the delay distance PV down to e.g. in steps of each 10 nanoseconds have been reached.

3302-74 '

- S-

- ι / - VPA 83 P f 0 3 ί DE

The fine adjustment of the exact duration of the pulse to be emitted is done in the invention in that in this clock-controlled pulse generator to generate the pulses Q / Q several clock pulse periods are counted by a presettable counter Z, this counter Z being started from the leading edge of a first clock pulse. This counter Z passes after reaching its predetermined maximum count W "1, its output signal a to a pulse terminating _f deactivating output stage D-FF2 on. To the previous-demand stepwise fine adjustment of the pulse duration does not conduct this counter Z its output signal a but directly but via a (digital) finely adjustable delay line PV to the output stage D-FF2.

χ

In addition, a gate G can be used between the output of the counter Z and the input of the delay line PV insert that allows the output signal a to be precisely synchronized with a clock pulse from the oscillator Os, in order to still eliminate slight scatter or tolerances in the duration of the output signal a, in any case largely.

1 claim '.- *

1 figure 'COPY

- blank page -

COPV

Claims (1)

Claim. Clock controlled pulse generator - for the generation of pulses (G) whose presettable duration, lasting several clock pulse periods (Os) , is largely determined by a presettable counter (Z) that counts clock pulses and is started by the leading edge of a first clock pulse, - by the counter (Z), after reaching its previously (using W1 / R1) specified highest counter reading, its output signal (a) to a terminating pulse disconnecting output stage (D-FF2) forwards, characterized in that - to the previous fine adjustment of the pulse duration as required - The counter (Z) its output signal (a) via a (by means of W2 / R2 digital) forwards the finely adjustable delay path (PV) to the output stage (D-FF2).