DE3279998D1 - Method for forming high density dielectric isolation - Google Patents

Method for forming high density dielectric isolation

Info

Publication number
DE3279998D1
DE3279998D1 DE8282106656T DE3279998T DE3279998D1 DE 3279998 D1 DE3279998 D1 DE 3279998D1 DE 8282106656 T DE8282106656 T DE 8282106656T DE 3279998 T DE3279998 T DE 3279998T DE 3279998 D1 DE3279998 D1 DE 3279998D1
Authority
DE
Germany
Prior art keywords
high density
dielectric isolation
forming high
density dielectric
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282106656T
Other languages
German (de)
English (en)
Inventor
Wei-Kan Chu
William Aaron Pliskin
Jacob Riseman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3279998D1 publication Critical patent/DE3279998D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
DE8282106656T 1981-07-27 1982-07-23 Method for forming high density dielectric isolation Expired DE3279998D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/287,466 US4544576A (en) 1981-07-27 1981-07-27 Deep dielectric isolation by fused glass

Publications (1)

Publication Number Publication Date
DE3279998D1 true DE3279998D1 (en) 1989-11-23

Family

ID=23103035

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282106656T Expired DE3279998D1 (en) 1981-07-27 1982-07-23 Method for forming high density dielectric isolation

Country Status (4)

Country Link
US (1) US4544576A (enExample)
EP (1) EP0071205B1 (enExample)
JP (1) JPS5818938A (enExample)
DE (1) DE3279998D1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021539A (ja) * 1983-07-15 1985-02-02 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
FR2566181B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre
JPS618941A (ja) * 1984-06-23 1986-01-16 Mitsubishi Electric Corp 半導体装置の製造方法
US4714520A (en) * 1985-07-25 1987-12-22 Advanced Micro Devices, Inc. Method for filling a trench in an integrated circuit structure without producing voids
JPS6265317A (ja) * 1985-09-17 1987-03-24 Mitsubishi Electric Corp 半導体単結晶膜形成のためのウエハ構造
US5462767A (en) * 1985-09-21 1995-10-31 Semiconductor Energy Laboratory Co., Ltd. CVD of conformal coatings over a depression using alkylmetal precursors
DE3534418A1 (de) * 1985-09-27 1987-04-02 Telefunken Electronic Gmbh Verfahren zum herstellen von vertiefungen in einem halbleiterbauelemente enthaltenden halbleiterkoerper
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
FR2620861B1 (fr) * 1987-09-22 1990-01-19 Schiltz Andre Procede de realisation d'isolement lateral a structure plane
FR2631488B1 (fr) * 1988-05-10 1990-07-27 Thomson Hybrides Microondes Circuit integre hyperfrequence de type planar, comportant au moins un composant mesa, et son procede de fabrication
US5416354A (en) * 1989-01-06 1995-05-16 Unitrode Corporation Inverted epitaxial process semiconductor devices
US5258334A (en) * 1993-01-15 1993-11-02 The U.S. Government As Represented By The Director, National Security Agency Process of preventing visual access to a semiconductor device by applying an opaque ceramic coating to integrated circuit devices
US5448111A (en) * 1993-09-20 1995-09-05 Fujitsu Limited Semiconductor device and method for fabricating the same
CA2131668C (en) * 1993-12-23 1999-03-02 Carol Galli Isolation structure using liquid phase oxide deposition
US5527609A (en) * 1994-04-20 1996-06-18 Toyo Boseki Kabushiki Kaisha Crimped polybenzazole staple fiber and manufacture thereof
US6114219A (en) * 1997-09-15 2000-09-05 Advanced Micro Devices, Inc. Method of manufacturing an isolation region in a semiconductor device using a flowable oxide-generating material
US6861334B2 (en) * 2001-06-21 2005-03-01 Asm International, N.V. Method of fabricating trench isolation structures for integrated circuits using atomic layer deposition
US7262477B2 (en) * 2002-04-30 2007-08-28 Kabushiki Kaisha Toshiba Semiconductor device
US20040016962A1 (en) * 2002-04-30 2004-01-29 Hideki Okumura Semiconductor device
JP2006128246A (ja) * 2004-10-27 2006-05-18 Toshiba Corp 半導体製造装置、液体容器および半導体装置の製造方法
KR100645211B1 (ko) * 2005-07-28 2006-11-10 동부일렉트로닉스 주식회사 플래시 메모리 셀의 플로팅 게이트 형성 방법
US9423253B2 (en) * 2011-10-31 2016-08-23 The Charles Stark Draper Laboratory, Inc. MEMS hemispherical resonator gyroscope
FR3079662B1 (fr) * 2018-03-30 2020-02-28 Soitec Substrat pour applications radiofrequences et procede de fabrication associe

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3212929A (en) * 1962-03-22 1965-10-19 Ibm Method of forming a glass film on an object
JPS4810981U (enExample) * 1971-06-24 1973-02-07
US4019248A (en) * 1974-06-04 1977-04-26 Texas Instruments Incorporated High voltage junction semiconductor device fabrication
US4039702A (en) * 1975-01-13 1977-08-02 Trw Inc. Method for settling a glass suspension using preferential polar adsorbtion
JPS51145276A (en) * 1975-06-10 1976-12-14 Mitsubishi Electric Corp Semiconductor device
JPS5255877A (en) * 1975-11-01 1977-05-07 Fujitsu Ltd Semiconductor device
JPS5336471A (en) * 1976-09-17 1978-04-04 Hitachi Ltd Manufacture of semiconductor device
DE2739762C2 (de) * 1977-09-03 1982-12-02 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Verfahren zur Passivierung von Halbleiterkörpern
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
EP0011418A1 (en) * 1978-11-20 1980-05-28 THE GENERAL ELECTRIC COMPANY, p.l.c. Manufacture of electroluminescent display devices
US4222792A (en) * 1979-09-10 1980-09-16 International Business Machines Corporation Planar deep oxide isolation process utilizing resin glass and E-beam exposure
JPS56160050A (en) * 1980-05-14 1981-12-09 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS5784138A (en) * 1980-11-13 1982-05-26 Toshiba Corp Manufacture of mesa semiconductor device
US4356211A (en) * 1980-12-19 1982-10-26 International Business Machines Corporation Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon
EP0060205B1 (en) * 1981-03-16 1986-10-15 FAIRCHILD CAMERA &amp; INSTRUMENT CORPORATION Low temperature melting binary glasses for leveling surfaces of integrated circuits containing isolation grooves

Also Published As

Publication number Publication date
EP0071205A3 (en) 1986-08-20
JPH0429228B2 (enExample) 1992-05-18
US4544576A (en) 1985-10-01
EP0071205A2 (en) 1983-02-09
EP0071205B1 (en) 1989-10-18
JPS5818938A (ja) 1983-02-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee