DE3278948D1 - A multiprocessor system with at least three-level memory hierarchies - Google Patents

A multiprocessor system with at least three-level memory hierarchies

Info

Publication number
DE3278948D1
DE3278948D1 DE8282109881T DE3278948T DE3278948D1 DE 3278948 D1 DE3278948 D1 DE 3278948D1 DE 8282109881 T DE8282109881 T DE 8282109881T DE 3278948 T DE3278948 T DE 3278948T DE 3278948 D1 DE3278948 D1 DE 3278948D1
Authority
DE
Germany
Prior art keywords
multiprocessor system
level memory
memory hierarchies
hierarchies
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282109881T
Other languages
German (de)
English (en)
Inventor
Robert Percy Fletcher
David Morris Stein
Irving Wladawsky-Berger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3278948D1 publication Critical patent/DE3278948D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
DE8282109881T 1981-12-31 1982-10-26 A multiprocessor system with at least three-level memory hierarchies Expired DE3278948D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/336,521 US4442487A (en) 1981-12-31 1981-12-31 Three level memory hierarchy using write and share flags

Publications (1)

Publication Number Publication Date
DE3278948D1 true DE3278948D1 (en) 1988-09-29

Family

ID=23316475

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282109881T Expired DE3278948D1 (en) 1981-12-31 1982-10-26 A multiprocessor system with at least three-level memory hierarchies

Country Status (5)

Country Link
US (1) US4442487A (US07166745-20070123-C00016.png)
EP (1) EP0083400B1 (US07166745-20070123-C00016.png)
JP (1) JPS58123151A (US07166745-20070123-C00016.png)
DE (1) DE3278948D1 (US07166745-20070123-C00016.png)
ES (1) ES8405533A1 (US07166745-20070123-C00016.png)

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Also Published As

Publication number Publication date
EP0083400A3 (en) 1986-06-04
EP0083400B1 (en) 1988-08-24
ES518678A0 (es) 1984-06-01
JPS58123151A (ja) 1983-07-22
JPS629942B2 (US07166745-20070123-C00016.png) 1987-03-03
US4442487A (en) 1984-04-10
EP0083400A2 (en) 1983-07-13
ES8405533A1 (es) 1984-06-01

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