DE3277991D1 - Data processing system with a plurality of peripheral devices - Google Patents

Data processing system with a plurality of peripheral devices

Info

Publication number
DE3277991D1
DE3277991D1 DE8282100835T DE3277991T DE3277991D1 DE 3277991 D1 DE3277991 D1 DE 3277991D1 DE 8282100835 T DE8282100835 T DE 8282100835T DE 3277991 T DE3277991 T DE 3277991T DE 3277991 D1 DE3277991 D1 DE 3277991D1
Authority
DE
Germany
Prior art keywords
data processing
processing system
peripheral devices
peripheral
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282100835T
Other languages
English (en)
Inventor
Wayne John Bauer
William Carl Dodt
Charles Ronald Kirkpatrick
Ted Anthony Rehage
Francis Leroy Robinson
William King Taylor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3277991D1 publication Critical patent/DE3277991D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
DE8282100835T 1981-03-06 1982-02-05 Data processing system with a plurality of peripheral devices Expired DE3277991D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/241,323 US4423480A (en) 1981-03-06 1981-03-06 Buffered peripheral system with priority queue and preparation for signal transfer in overlapped operations

Publications (1)

Publication Number Publication Date
DE3277991D1 true DE3277991D1 (en) 1988-02-18

Family

ID=22910227

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282100835T Expired DE3277991D1 (en) 1981-03-06 1982-02-05 Data processing system with a plurality of peripheral devices

Country Status (5)

Country Link
US (1) US4423480A (de)
EP (1) EP0059842B1 (de)
JP (1) JPS57159324A (de)
CA (1) CA1172379A (de)
DE (1) DE3277991D1 (de)

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WO1991014985A1 (fr) * 1990-03-19 1991-10-03 Fujitsu Limited Systeme de traitement de programme d'interruption
US5333301A (en) * 1990-12-14 1994-07-26 International Business Machines Corporation Data transfer bus system and method serving multiple parallel asynchronous units
JPH05257851A (ja) * 1991-12-30 1993-10-08 Apple Computer Inc データの転送の順序を制御させる装置
US5848297A (en) * 1991-12-30 1998-12-08 Apple Computer, Inc. Control apparatus for maintaining order and accomplishing priority promotion in a computer interconnect
US5887196A (en) * 1991-12-30 1999-03-23 Apple Computer, Inc. System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer
US5640599A (en) * 1991-12-30 1997-06-17 Apple Computer, Inc. Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed
US5388237A (en) * 1991-12-30 1995-02-07 Sun Microsystems, Inc. Method of and apparatus for interleaving multiple-channel DMA operations
US5410677A (en) * 1991-12-30 1995-04-25 Apple Computer, Inc. Apparatus for translating data formats starting at an arbitrary byte position
US5392397A (en) * 1992-03-30 1995-02-21 International Business Machines Corporation Command execution system for using first and second commands to reserve and store second command related status information in memory portion respectively
US5373401A (en) * 1993-06-18 1994-12-13 International Business Machines Corporation Data storage system having multimodal interblock gap detection utilizing a predicted occurance time window
US5363252A (en) * 1993-06-30 1994-11-08 International Business Machines Corporation Method and system for track skew tolerant acquistion burst sequence validation in a data storage system
JP2972501B2 (ja) 1993-09-20 1999-11-08 富士通株式会社 Ｉ／ｏサブシステム及びｉ／ｏサブシステムにおける排他制御方法
US5561823A (en) * 1994-03-14 1996-10-01 Conner Peripherals, Inc. Monitor system for determining the available capacity of a READ buffer and a WRITE buffer in a disk drive system
FR2740240B1 (fr) * 1995-10-20 1997-11-21 Gemplus Card Int Lecteur de carte a puce
US5872938A (en) * 1996-06-28 1999-02-16 International Business Machines Corp. Service priority queue implemented with ordered sub-queues and sub-queue pointers pointing to last entries in respective sub-queues
US7272298B1 (en) 1998-05-06 2007-09-18 Burst.Com, Inc. System and method for time-shifted program viewing
US8577205B2 (en) 1998-07-30 2013-11-05 Tivo Inc. Digital video recording system
US6233389B1 (en) 1998-07-30 2001-05-15 Tivo, Inc. Multimedia time warping system
US7558472B2 (en) 2000-08-22 2009-07-07 Tivo Inc. Multimedia signal processing system
US8380041B2 (en) 1998-07-30 2013-02-19 Tivo Inc. Transportable digital video recorder system
JP2000048549A (ja) * 1998-08-03 2000-02-18 Fujitsu Ltd テープ装置
US7013305B2 (en) 2001-10-01 2006-03-14 International Business Machines Corporation Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange
US6898654B1 (en) 1999-07-29 2005-05-24 Microsoft Corporation Method and system for managing bandwidth on a master-slave bus
US6735720B1 (en) * 2000-05-31 2004-05-11 Microsoft Corporation Method and system for recovering a failed device on a master-slave bus
US20030074522A1 (en) * 2001-10-15 2003-04-17 Dahman Kirby Grant Data management system, apparatus, and method to use buffered file marks
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US4310882A (en) * 1978-12-28 1982-01-12 International Business Machines Corporation DAS Device command execution sequence

Also Published As

Publication number Publication date
CA1172379A (en) 1984-08-07
EP0059842A3 (en) 1984-11-28
US4423480A (en) 1983-12-27
EP0059842B1 (de) 1988-01-13
EP0059842A2 (de) 1982-09-15
JPS631631B2 (de) 1988-01-13
JPS57159324A (en) 1982-10-01

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