DE3229251A1 - Test circuit for a circuit arrangement to receive and forward data signals which occur at relatively high speed in a data switching network - Google Patents

Abstract

In a switching device (K) which can be connected to a data switching network to receive data signals occurring on high-speed feeding lines (NKan1 to NKanx) and to forward these data signals via high-speed serving lines (NKab1 to NKabx), a testing device (PT) is provided to check the transmission paths within the switching device, which testing device, at the instigation of the associated data switching system, is able to send a number of test signals to a high-speed serving line under test and to receive the same number of test signals occurring on a high-speed feeding line under test in order to carry out an error check. A permanent memory location (Zz) of a through-connection memory (DS) of the switching device (K) is allocated to the aforementioned testing device (PT), into which location the address of the high-speed serving line under test can be written. The address of the testing device (PT) can be written into the memory space, of the through-connection memory, associated with the high-speed feeding line under test. Test loops are furthermore provided via data selectors (DWan1 to DWanx) to feed the test signals transmitted by the testing device (PT) back to the latter. <IMAGE>

Description

Test circuit for a circuit arrangement for recording

and forwarding that occurs at a relatively high speed Data signals in a data switching network (addition to P 31 07 089.2> The main patent (P31 07 089.2) relates to a circuit arrangement for recording with a relatively high Speed of data signals occurring on high-speed feeder lines and forwarding these data signals over high-speed trunk lines in a data switching network comprising at least one time division multiple data switching system, in which each time division multiple data processing system has a separate switching device is associated, via which the said data signals are conveyed and the associated controllable by a control device of your time division multiple data exchange system is, over which in the course of the respective data signal connection mlu is relatively lower Speed occurring signaling information are conveyed, with the coupling device has a through-connection memory with the high-speed feeder lines Has individually assigned storage locations into which the control device the associated time division data switching system each have an address of one high-speed trunk line eligible for data signal pickup restrictive, and where in the course of brokering ßiit the high speed occurring data signals only that of the respective high-speed feeder line allocated storage space of the through-connection memory controlled and made available the address contained in the relevant memory location the for a high-speed trunk line in question is activated.

The switching takes place in the circuit arrangement described above of the data signals occurring on high-speed feeder lines via the separate coupling device without monitoring by the associated time division data switching system. In order to ensure error-free transmission, the transmission paths are to be checked routinely within the separate coupling device.

It is now the object of the present invention to provide the circuit arrangement to further develop according to the main patent so that one of the controlling time division data exchange system largely independent checking of the transmission paths within the switching device is possible.

The object indicated above is achieved with a circuit arrangement of the type mentioned according to the invention in that the coupling device is a test device controllable by the associated time-division data exchange system has, which is based on a control of the relevant time division data switching system a number of test signals in the form of selected data signals to one to be tested first high-speed customer line and the same number of occurring on a first high-speed feeder line to be tested Test signals for the implementation of an error check is able to record that the A fixed memory location of the through-connection memory is assigned to the test device, to the address of the first high-speed subscriber line to be tested It can be inscribed that the address of the test device is in that of the first to be tested High speed feeder line associated storage space of the through-connection memory of the associated: ger time division data exchange system can be inscribed here and that in the coupling device between the individual 40ch-speed trunk lines and the individual high-speed feeder lines and test loops via data switches so effectively controllable from the associated time-division data exchange system are that the test equipment to the first high-speed subscriber line to be tested output test signals from the test device via the first high-speed feeder line to be tested can be picked up again.

The invention has the advantage that the associated cell multiple data exchange The liver does not check the transmission paths within the coupling device is additionally charged. The data exchange only gives a control signal to activate the test device to the coupling device.

After a check has taken place, the coupling device the result of this test communicated to the data switching system, Appropriate Refinements of the circuit arrangement according to the invention emerge from the Subclaims.

The invention is explained in detail below with reference to drawings explained in more detail.

1 shows a possible embodiment in a block diagram ler separate coupling device according to the invention, Fig. 2 shows the possible Construction of a circuit used to carry out error checking arrangement a test device according to FIG. 1, FIG. 3 shows a basic circuit diagram to which will be discussed in the course of the explanation of the invention.

In Fig. 1 is a possible form of implementation of a coupling device K shown in which at relatively high speed on high speed feeder lines occurring data signals can be switched. The coupling device K contains a Connection control circuit EACK and a connection circuit SAGK. The connection control circuit With regard to the structure of the input coder ECW, EACK has a register Reg and the terminals Oa, Od, with respect to the output encoder ACW with the terminals Ia, Id and with regard to the through-connection memory DS with the feeder cells Zz and the connections Ea, Es, Aa identical to the connection control circuit with the same designation according to Fig. 2 of the main patent. The connection control circuit EACK in FIG additionally a test device PT. This testing device, which is a testing transmitter PS for outputting test signals and a test receiver PE for receiving test signals is via the line arrangement Lc from the associated time division multiple data exchange system EDS controllable. The test transmitter PS is made up of several individual lines Line arrangement connected to inputs of the input encoder ECW. The test receiver PE is also made up of several individual lines with its data inputs existing line arrangement connected to outputs of the output encoder ACW. This test receiver is on the output side via a line arrangement with the associated Time multiple data exchange system EDS connected. ' The connection circuit SAGK contains the same circuit elements as the connecting switch with the same designation tion according to Fig. 2 of the main patent. Of these circuit elements are in Fig. 1 only the multiplexer Mul and the demultiplexer Dem are shown. In addition, the Connection circuit SAGK in Fig. 1 of the associated time division data switching system EDS @@@ switchable data switches DWan1 to DW'anx, their switchover through Control signals takes place, which are transmitted on the line arrangement Lc. These Data switches each have two inputs. There is one at each entrance High-speed feeder line (e.g.

B. & Kan1) and at the other entrance is a high-speed customer line (e.g. NKab1) connected. On the output side, each of these data switches is with each connected to an input of the multiplexer flul.

FIG. 2 shows a possible form of implementation of the one indicated in FIG. 1 Test receiver PE shown. This test receiver contains a decoding circuit Dec, the input side by a line arrangement with the output encoder ACW (Fig. 1) is connected. The decoding circuit Dec a predetermined number of test signals in the form of selected, transmitted in parallel Data signals supplied. The decoding circuit Dec has one of the predetermined numbers the number of outputs corresponding to the test signals, of which when they arrive one of the specified test signals is only assigned to the test signal in question Output emits a control signal. In the embodiment considered here four outputs (1 to 4) are provided, i.e. there are a total of four test signals rated. Each of these outputs is connected in series with an evaluation level connected to individual evaluation levels (BO to B3). For example, the exit 1 of the decoding circuit with the evaluation level B ¢, output 2 with the evaluation level - ', the output 3 with evaluation level B2 and output 4 associated with evaluation level 33. In addition, the decoding circuit Dec is with connected to another output O to the evaluation level BO. From this exit a signal to activate the evaluation stage BO is emitted if after the activation of the test receiver PE a first test signal from the decoding circuit is recorded.

Each of the mentioned evaluation levels (BO to B3) contains a comparator arrangement (e.g. VO), the input side with one of the outputs 1 to 4 of the decoding circuit Dec is connected and receives a signal for activation. For the first (BO) of the series-connected evaluation levels BO to B3, this is activated the associated comparator arrangement serving signal at output 0 of the decoding circuit provided. Such a signal is used for the other evaluation levels (B1 to B3) provided by the assessment level preceding the respective assessment level.

One output of each comparator arrangement (e.g. Vo) has an input connected to a flip-flop (e.g. KO), which then only has a specific, the active switch emits a signal that may serve its subsequent evaluation level, when the comparator arrangement connected to it on the input side and activated (VO) receives a control signal supplied from the decoding circuit Dec.

In the case of the individual flip-flops (KO to K3) it can be, for example are clock-controlled flip-flops, each of which has a clock signal at a clock input CL is supplied. This clock signal CL may be from a central clock generator the coupling device K are made available.

From a further output of each comparator arrangement (e.g. vo) in the absence of a control signal to be emitted by the decoding circuit, an error display signal delivered to a logic element C1.

Each of the comparator arrangements just considered (VO to V3) can for example, as shown in FIG. 2 for the comparator arrangement VO, two AND-Clieder G2 and G3 each have two inputs. One entrance each the AND gate is connected to one of the outputs 1 to 4 of the decoding circuit Dec.

The AND gate G3 is one of the input signals inverting input. The respective other input of the AND gates has an already mentioned signal for activating the relevant comparator arrangement supplied. The output of the AND element G2 is connected to one input of the relevant Wergleicher arrangement downstream flip-flop connected. The output of the AND gate G3 is with a Connected input of the already zanten logic element Gt.

The link element Cl just mentioned is a series circuit from an OR element and an AND element. The OR element has four inputs each with the output of an AND gate corresponding to the AND gate G3 the comparator arrangements VO to V3 are connected. The output of this OR gate is connected to an input of the downstream AND element. Another The input of this AND element is one of the central clock generator already mentioned above delivered clock signal CL supplied.

After the circuit arrangements shown in FIGS. 1 and 2 have been abandoned has now been explained, the modes of operation of these circuit arrangements will now be discussed with reference to FIG. 3. In Fig. 3 is in strong simplified form of the case that the high-speed tap line NKab7 and the high-speed feeder line NKanl included in a test are. To initiate this test, the associated data exchange system is first used EDS ago a special control command via the line arrangement Lc to the connection circuit Transfer the SACK.

Due to this special control command, in the connection circuit SACK the data switch DWanI is controlled in such a way that on the high-speed customer line NKabl occurring data signals are fed to the multiplexer Mul via this data switch (Fig. 1).

This is followed by the associated data exchange EDS issued two further control commands to the connection control circuit EACK. With a first control command, one of the high-speed feeder lines is activated Feeder cell Zz assigned to NKanl (Zz (NKan1) in Fig. 3) the address of the testing device PT registered. This test device PT is, for example, the address "O" permanently assigned. With the second control command, one of the The feeder cell assigned to the test device PT contains the address of the high-speed customer line NKabl registered. This feeder cell is denoted by Zz (0) in FIG. 3. This The second switching command also activates the test transmitter PS and the test receiver PE of the test facility PT.

After activating the test device PT, the test transmitter gives PS in this embodiment four test signals at constant time intervals away. The test signals represent selected data signals that are in parallel Form to be forwarded. The test transmitter PS can for this purpose, for example, one of the associated data exchange EDS can be activated Counter arrangement have, at constant time intervals, certain counter signals on their Output. In accordance with these counter signals, memory cells can be dn in sequence a memory in which the test signals to be output are stored are.

A test signal emitted by the test transmitter PS is combined with the address designating the test device PT ("0") to the input encoder ECW (Fig. 1) supplied.

This address is then assigned to the test device PT Feeder cell Zz (O) in the through-connection memory DS controlled (connecting line 1 in Fig. 3) and the address of the selected high-speed trunk line stored therein read out. In the present case, it is the high-speed customer line NKab This read-out address (connecting line 2 in FIG. 3) is then together with the early signal (Yerbindu.gsr 3 in Fig. 3) is fed to the output encoder ACW. The output encoder ACW then conducts this test signal together with the associated address to the connection circuit SAGK on. The test signal passed on in this way is finally through the demultiplexer Den delivered to the high-speed customer line NKab1 and fed to the multiplexer Mi via the data switch DWan1. That now from that Multiplexer Nul recorded test signal is then forwarded to the input encoder EC we ^.

After accepting a previously received via the data switch DWan1 The test signal in the input encoder ECW is based on the address of the high-speed feeder line NKan1 the associated feeder cell Zz (NKan1) is controlled (connecting line 4 in Fig. 3) and the address of the test device PT ("O") stored therein. sen. This read out address (connecting line 5 in Fig. 3) is then put together again with the test signal currently in the input encoder ECW (connecting lines 6 in Fig. 3) forwarded to the output encoder ACW. The output encoder ACW then gives the test signal just recorded due to the attached address "O" to the test receiver PE of the test facility PT.

The processes just presented are repeated with each of them Test transmitter PS output test signal. Only the case was considered above, that only one high-speed trunk line and one high-speed feeder line are included in the examination. However, further tests can be included in such a test High-speed trunk lines and high-speed feeder lines be included.

This is done in such a way that a chain of these further High-speed trunk lines and high-speed feeder lines by writing in the addresses of the respective high-speed trunk lines in the assigned high-speed feeder lines previously used Feeder cells of the through-connection memory DS takes place and that in the last High-speed feeder line of the high-speed customer lines considered in this way and the feeder cell associated with high-speed feeder lines is that of the test facility PT associated address is written. It is, for example, through such a chain possible all lines that are not included in a data signal connection are to be checked in a test process.

The operation of the test receiver PE will now be described below explained with reference to FIG. As mentioned earlier, the test receiver PE the test signals emitted by the test transmitter PS from the output encoder ACW forwarded. When the first arrives Check signal after activation of the test device PT is a signal from the decoding circuit Dec at output @ to activate the comparator arrangement @@ of the evaluation level BO This signal becomes ^ ~ n a logic 1 level at the output "0t1 of the decoder circuit Formed Dec. The AND gates G2 and G3 are the Comparator arrangement switched effective. Now occurs after decoding the first Test signal at output 1 of the decoder circuit Dec has a logic 1 level, so occurs at the output of the AND gate G2 also a logic 1 level. Because of this Level gives the downstream flip-flop KO the evaluation level BC after arrival of the next clock pulse CL at its output a Losisch 1 level. Through this the comparator arrangement V1 of the evaluation stage B1 is activated. To This clock pulse is the comparator arrangement V0 by a logic 0 level on Output 0 of the decoding circuit Dec switched ineffective. Such a clock pulse CL is not emitted by the already mentioned clock generator until after a test signal has been fed to the decoding circuit Dec. Now step after the Receipt of the next test signal at the output 2 of the decoding circuit Dec a logic 1 level on, then the flip-flop K1 associated with the comparator arrangement V1 is in turn with it the next clock pulse CL at its output a logic 1 level. With this Pulse, the KO flip-flop is reset at the same time (logic O level at the exit).

The processes just explained are repeated accordingly Way, until finally a logic 1 level is emitted by the flip-flop K3 When this level is emitted, the test process in the test receiver PE is complete. The test receiver PE derives from the level emitted by the flip-flop K3 encoded message and transfers it to the associated data exchange system EDS as confirmation of the orderly process of the test process.

Above only the case was considered that originally from the test signals outputted to the test transmitter PS are transmitted without errors, i.e. that the test signals recorded in the intended sequence by the test receiver PE will. If, on the other hand, a corruption occurs due to a faulty transmission path of a test signal originally emitted by the test transmitter PS, the at this point in time in the test receiver PE activated evaluation level no control signal in the form of a logic 1 level is supplied from the decoding circuit Dec. This means that the relevant comparator arrangement is present at the output of the AND element G3 and thus a logic 1 level is constantly present at the input of the logic element G1. This logic 1 level is at the time of the presence of a clock signal CL from delivered to the output of the logic element G1. From this logic level conducts the test receiver PE sends a coded message and transmits it as an error display signal the associated data exchange system EDS.

Regarding the processes presented above, it should be noted here that that with the activation of the test device PT in the associated data exchange EDS time monitoring can be carried out. Does the test receiver give PE during this time monitoring does not send a message to the data exchange EDS, so will the test process assessed by the data exchange system as faulty.

4 claims 3 figures

Claims (4)

Claims test circuit for a circuit arrangement for recording from relatively high speed to high speed feeder lines (NKan1 to NKanx) on incoming data signals and forwarding of these data signals over high-speed trunk lines (NKab1 to NKabx) in at least one a time division data exchange (EDS) comprehensive data switching network, in which each of the time division multiple data switching systems has a separate switching device (K) is associated, via which the data signals mentioned are conveyed and the to this from a control device (UEAS) of your time division multiple data exchange (EDS) is controllable, via which in the course of the respective data signal connection with Signaling information occurring at a relatively low speed is conveyed are, the coupling device (K) a through-switching memory (DS) with the High-speed feeder lines (NKan1 to NKanx) individually assigned Storage locations z) into which the control device (UEAS) of the associated Time division data switching system (EDS) each one address (ADR) one for a high-speed trunk line in question (e.g. NKabl) can be enrolled, and in the course of the placement of with the high Speed occurring data signals only that of the respective high-speed feeder line (e.g. NKanl) assigned memory location (Zz) of the switching memory (DS) controlled and by providing the address contained in the relevant memory location (ADR) the high-speed subscriber line in question for data signal recording (e.g. NKab1) is activated, according to patent .. .. ... (P 107 089.2), d a d u r c h g e -k e n n z e i c h n e t that the coupling device (K) is one of the associated time division data exchange system (EDS) controllable Test device (PT) which responds to a control of the relevant time division data switching system a number of test signals in the form of selected data signals to one to be tested first high-speed customer line (e.g. NKab1) is able to deliver and the the same number of on a first high-speed tributary line to be tested (e.g. NKan1) occurring data signals for carrying out an error check able to record that the test device (PT) a fixed memory location (Zz) des Through-switching memory (DS) is assigned, in which the address of the first to be checked High-speed trunk line (NKabl) is inscribable that the address of the test facility (PT) in that of the first high-speed feeder line to be tested (an1) associated memory location (Zz) of the through-connection memory (DS) from the associated Time multiple data exchange (EDS) can be registered and that in the Coupling device (K) between the individual high-speed customer lines and the individual high-speed feeder lines test loops via data switches (DWanl to DWanx) from the associated time division data exchange system (EDS) are so effectively controllable forth that the from the test device (PT) to the to testing first high-speed pickup line (NKab1) issued test signals from the test facility (PT) via the first high-speed feeder line to be tested (NKan1) can be resumed. 2. Test circuit according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that more high-speed trunk lines and high-speed feeder lines be included in the above-mentioned test that a chain of these further High-speed acceptance mer lines and high-speed feeder lines by writing in the addresses of the respective high-speed trunk lines in the assigned high-speed feeder lines previously used Storage locations and that in the direct high-speed feeder line of the high-speed trunk lines and high-speed feeders thus taken into account Feeder cell assigned to lines the address associated with the test facility (PT) is enrolled. 3. Test circuit according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the test device (PT) has a predetermined number of individual, Test signals occurring at constant intervals in a specific sequence is able to output that the test device (PE) has a decoding circuit evaluating the test signals (Dec) with a number of corresponding to the predetermined number of test signals Has outputs, of which Ci the arrival of one of the predetermined test signals in each case only the output assigned to the relevant test signal issues a control signal, that each of these outputs with an evaluation stage of a series connection of individual Assessment levels (BO to B3) are connected, one of which at a given point in time only the evaluation level assigned to the test signal expected at this point in time (e.g. B1) is activated, which when a control signal occurs on the with the output of the decoding circuit (Dec) connected to it, the evaluation stage following it (B2) effectively switches and which in the absence of a corresponding control signal an error display signal emits r and that from an output of the last evaluation stage (R! In the mentioned series connection of the evaluation levels (B0 to B5) only in that case an output signal indicating a positive test result can be emitted, that the output of an error indication signal has not occurred. 4. Test circuit according to claim 3, d a d u r c h g e -k e n n z e i c h n e t that each of the evaluation stages (80 to B3) has a comparator arrangement (e.g. V1), which on the input side is connected to an output of the decoding circuit (Dec) is connected and receives a signal to activate them, which for the first (Bo) of the series-connected evaluation levels (B0 to B3) from the Decoding circuit (Dec) and for the other evaluation levels (B7 to B3) from the the assessment level preceding the respective assessment level is provided, that an output of each comparator arrangement (e.g. V1) with an input of a flip-flop (e.g. K1) is connected, which only then has a certain, the activation of a emits its signal, which may serve the subsequent evaluation stage, if the with it initially connected, effectively switched comparator arrangement (Vi) a control signal received from the decoding circuit (Dec), and that from a further output each comparator arrangement (vi) in the absence of a corresponding control signal an error indication signal is output.