DE3216040A1 - CIRCUIT ARRANGEMENT FOR MUTUAL SYNCHRONIZATION OF PCM BUNCHES - Google Patents

Description

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11237 / H / Elf

ITALTEL

Societä Italiana Telecomunicazioni s.p.a. Malland (Italy)

Circuit arrangement for the mutual synchronization of PCM bundles

The invention relates to a circuit arrangement for mutually aligning or synchronizing a number η of similar PCM bundles corresponds to the generic term des Claim 1.

One proposed in German patent application P 32 02 971.3 Telephone switching center consists of several

with
reren modules' each have a switching unit tr ix, to whose input a fixed number of PCM bundles is connected, which come from other modules at different distances and are thus identical ("coherent"), but delayed differently from bundle to bundle. Before the switching of the digital * words distributed in the time channels of the PCM bundles, an alignment or mutual synchronization of the bundles is necessary so that the digital words of the same time channel of all bundles are always available at the input of the matrix. Synchronization is usually carried out

with one of the number of eggs to be synchronized • Bundle corresponding number of elastic stores, each elastic memory is generally assigned a phase coupling circuit / which has a clock pulse train the frequency of the PCM bundle with which the PCM signals are written to the respective memory. The memory are then read simultaneously under control by the clock pulses of the switching node. This method is Because of the large number of elastic memories and the same number of phase coupling circuits, depending on the number of PCM bundles very expensive.

The invention is based on the object of a circuit arrangement to create that is simpler than the known synchronizing circuits and yet reliable Allows identification of the bits of the PCM bundle.

This object is achieved by the circuit arrangement characterized in claim 1.

To avoid constant changes in decision-making on the part of of the first functional unit of the circuit arrangement described here is expediently a time hysteresis according to the invention provided, according to which a decision made in each case is retained as long as the shift the PCM signals with respect to the clock signal does not exceed a specified value or range. Consequently The first functional unit sends the second functional unit PCM signals, the phase changes (jitter disturbances) of the input signals are insensitive as long as these changes remain within a predetermined band.

The invention is explained in more detail using an exemplary embodiment. In the drawing show:

FIG. 1 shows the block diagram of the first functional unit;

FIG. 2 vibration forms occurring in the functional unit according to FIG. 1; and

FIG. 3 shows the block diagram of the second functional unit.

According to FIG. 1, the eight PCM bundles RRCN _Q ... RRCN _{7 are} connected with the same bit frequency of, for example, 2 M bit / s to the input of a first functional unit PHADJ, which delay each signal of the PCM bundles RRCN by a fraction of a bit can, in order to make output signals of the bundle RRCN ₀ ... RRCN- available, the edges of which (signal transitions) are removed from the rising edges of the clock signal DCLK of the telecommunication node under consideration. This is important because, following the circuits described here, the bits of the PCM bundle RRCN are to be checked to discriminate their respective binary value on the rising edges of the clock signal DCLK. If the signal edges of the PCM bundle RRCN are close to the falling edges of the clock signal DCLK, there are favorable conditions for recognizing the received bits, since these are checked in the middle of the bits. If, on the other hand, the edges of the PCM signals are "close" to the rising edges of the clock signal DCLK, a normal test is hardly possible because it would take place in the area of the bit edges and, for example, in the event of jitter from the transmission lines some bits would be skipped during the test, but other bits would be tested twice. So that the signals of the PCM bundle RRCN are sent on with edges far from the rising edges of the clock signal DCLK, the circuit arrangement according to the invention supplies signals of the PCM bundle RRCN that are unchanged or delayed by half a period (ues clock signal), depending on whether the The edges of the PCM signals are close to the falling or rising edges of the clock signal DCLK.

To avoid continual changes in decision-making on the part of the circuits performing the test described a time hysteresis is provided, which consists in the respective decision (whether the signal is delayed or not) as longitudinally as the shifting of the pulses of the PCM bundle with respect to the pulses of the clock signal DCLK does not exceed a specified value or range. For the time hysteresis, the edges of the PCM signals are compared with two different "time windows": If the PCM signal previously passed unchanged the subsequent check is carried out with regard to a "wide" time window around the falling edge of the clock signal DCLK around. The previous decision is therefore retained as long as the edges of the PCM signals in this time window. If, on the other hand, a PCM signal delayed by half a period was passed on beforehand, the subsequent test with respect to a narrow time window around the falling edges of the clock signal CDLK made, so changed the previous decision, if the edges of the PCM signals coincide with this time window. A jitter disturbance subject to hysteresis the signals of the PCM bundle CCNR at the output of the functional unit PHADJ thus speak to the phase of the input signals not on if the fault does not exceed a specified value or range.

The mentioned time windows are controlled by a time window circuit PM formed, which receives the pulses of the clock signal DCLK shown in diagram a) of FIG. 2 and in the Is able to use a first signal as a "wide" time window in the form of a pulse on each falling edge of the clock signal DCLK and to generate a second signal as a "narrow" time window with the same edges of the clock signal DCLK, as in

Diagranun b) and c) are each shown with a dashed line. According to the illustration, the pulses can be centered in such a way that the middle of the two time windows lies at least approximately at the negative edges of the clock signal. With a period of the clock signal DCLK of P = 400 ns, a duration T. = 300 ns can be selected for the wide time window and the duration T- = 100 ns for the narrow time window ο.

The signals of the PCM bundle RRCN _Q ... RRCN- arrive at the inputs of a delay circuit SM, which is able to deliver the same signals delayed by T / 2 at the output, as well as a test circuit TM to determine the coincidence of the mentioned time windows the planks (signal changes) of the signals of the PCM bundle RRCN,

According to a preferred embodiment, there is the delay circuit SM consists of an arrangement of 8 bistable D-type circuits (D flip-flops) connected to the data input A corresponding PCM bundle RRCN and the signal DCLK at the clock input (i.e. the inverted clock signal DCLK) receive.

The test circuit TM can contain a first multiplexer MX- which receives the signals PRNRq, FRNR .. and FRNR ₂ at the data input, which enable the sequential delivery of the signals of the bundle RRCN. The signals FRNR express a code or numerical value which is increased step by step after a time interval equal to the frame duration (eg 125 \ is) of the PCM signals. The PCM signals of the bundle RRCN ₁ (diagram d) appearing at any point in time at the output of the multiplexer MX _{1 reach a differentiating circuit DR 1} , at the output of which a pulse is generated on every edge of its input signals, as can be seen from diagram e) . The output pulses of the differentiating circuit

DR ₁ get to a gate circuit P ₁ , which is blocked by the output signal of a monostable multivibrator MN, which is generated for a fixed time interval in response to the receipt of a pulse DFRX appearing at the beginning of each frame. As a result, the pulses generated by the differentiating _{circuit DR 1 are not allowed to pass by the gate circuit P 1 for} so long that the transistors of the circuit determined by the increase in the numerical value of the signals FRNR can be viewed as deleted. The pulses coming from the output of the gate circuit P ₁ reach the clock input of a D-type flip-flop FF, which receives one of the signals generated by the time window circuit PM at the data input.

The output signals of the test circuit TM are stored by a control circuit QR, which serves to send the time window signals FL or FS on the part of the test circuit TM and to generate enable signals for a transmission or output circuit QN. The output circuit QN contains 8 pairs of transmission elements TR _... TR ~ ,, of which in each case one element is a corresponding one of the PCM signals present at the input of the delay circuit SM. Bundle RRCN and the other member receives the corresponding signal delayed by the circuit SM. The control circuit QR contains a memory MM ₁ with random access (RAM) with 8 memory cells addressed by the code or numerical value of the signals FRNR. The memory MM ₁ stores the binary value for each PCM bundle which is present at the output of the flip-flop FF when the gate circuit P ₁ emits a pulse. In addition to the circuit QN, the outputs of the memory MM ₁ are also led to a second multiplexer MX ₂ , which receives the signals FRNR at the address input. The output of the multiplexer MX ₂ enables a second and

a third gate circuit P- or P ₂ , which receive the signal FL or the signal FS of the time window circuit PM at the respective other input, the qualification input of the one gate circuit P _{2 being} negated.

When the system ₁ bits are written with the binary value 0, so that the output pulse of the multiplexer MX _2, the gate P aufsteuert _2, which lets through the wide window in the form of the signal FL in the memory MM. If, for example, the code value of the signal FRNR addresses the PCM bundle RRCN _Q and its signals have the phase shown in diagram d), the differentiating circuit DR ₁ generates the pulses shown in diagram e) which match the wide window in the form of signal FL so that a pulse with the binary value 0 appears at the output of the bistable multivibrator FF, which is stored in the _{cell of the memory MM 1 assigned to the relevant PCM bundle.} This pulse also enables the transmission element TR-, which sends the _{signals of the PCM bundle RRCN Q present at the input of the delay circuit SM.} Since the edges of these signals lie in the time window in the form of the signal FL, the rising edge of the clock signals DCLK is in the middle position of the received bits, which proves to be beneficial for their checking or identification.

When the number expressed by the signal FRNR increases, it addresses the next following cell of the memory MM ₁ in which a pulse with the binary value Ö is stored and which enables _{the gate circuit P 2.} As a result, the signal FL is present at the input of the flip-flop FF. If the signals of the PCM bundle RRCN ₁ expand the phase shown in diagram f), the differentiating _{circuit DR 1} delivers the pulses shown in diagram g), which with the

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Signal FL do not match, so that the flip-flop FF now generates a pulse with the binary value "1". This' pulse is stored in the memory MM and enables the transmission element TR ₁ , which receives and sends the signals of the PCM bundle RRCN _{1 delayed by the delay circuit SM.} According to FIG. 2, the rising edges of the clock signal DCLK lie directly next to the edges of the signal shown in diagram f), while, as desired, they are in the middle range of the bits of the same. but according to diagram h) delayed signal lie.

If, after calling or counting the other PCM systems, the numerical value of the signals FRNR again corresponds to the PCM bundle RRCN ₀ , the memory MM ₁ generates a pulse with the binary value 0, which _{enables the gate circuit P 2} to compare the signal L with to let through the output pulses of the differentiating circuit DR _1. If the output pulses of the differentiating circuit match the wide time window, another pulse with the binary value 0 is stored. If the numerical value of the signals FRNR corresponds to PCM bundle No.1, the memory MM ₁ supplies a pulse with the binary value "1" , which enables the gate circuit P ₃ , so that in this case the flip-flop _{circuit FF carries out the time comparison of the output pulses of the differentiating circuit DR 1} with the narrow time windows, ie the signals FS. If the differentiated output pulses do not coincide with these time windows, a pulse with the binary value "1" is stored _{in the memory MM 1 and, accordingly, the transmission element TR 1} transmits the signals from the circuit SM.,

of
delayed signalsTpcM bundle RRCN ₁ forwarded

The delayed signals of the PCM bundle RRCN ₁ are forwarded until they are shifted with respect to the

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Clock signals DCLK assumes a value at which the signal edges match the window signals FS, as in
Diagram i) is shown. When this occurs, a pulse with the binary value "0" appears at the output of the memory MM ₁ , which enables the transmission element R- to output the am
Input of the delay circuit SM to send _{signals of the PCM bundle RRCK 1 present.}

In the case of time windows with the specified duration of the signals FL and FS, the forwarded PCM signals CCNR do not react
for jitter interference in the input signals of the PCM bundle RRCN, if the interference is shorter than 100 ns. This value

namely corresponds to the maximum shift that the PCM signals can experience in relation to the clock signals DCLK,
before a decision change takes place on the part of the test circuit TM.

FIG. 3 shows the circuit details of a second functional unit Refer to BTADJ for introducing a delay of whole numbers of bits on each of the PCM signals CCNR is used to effect their frame synchronization.

The signals CCNR «... CCNR ^ come from the output of the first
Functional unit PHADJ for the input of a multiplexer MX-.
in a synchronization circuit SS, which is used to generate a pulse based on the determination or message (pulse DFRX) of the time of the start of the frame of each PCM signal CCNR

serves. The multiplexer MXo is controlled at the address input by the numerical value of the signals FRNR mentioned, the increase of which causes the sequential delivery of the signals CCNR. _{A shift register RS 1} with 8 memory cells is connected to the output of the multiplexer MX-, which are connected to a decoder DC, which is to emit a pulse when in
the shift register RS _{1 has} the characteristic binary form of the sync word. The output pulse of the

Decoder DC controls the input of a gate element P _{4 which carries out the logical multiplication and which receives the output pulse of the differentiating circuit DR 2} generated on every negative edge of the clock signal DCLK at a second input and the output signal of an identification circuit CR at a third input, which receives the output signal of an identification circuit CR corresponding to a time interval the duration of the first time channel of the frame is active.

If the synchronous word is determined in the course of the first time _{channel selected by the multiplexer MX 3} , the PCM system selected, a pulse appears at the output of the gate element P 'to enable a circuit ST to calculate the delays that the signal CCNR selected _{by the multiplexer MX 3.} of the PCM system in question in relation to the time of the start of the frame determined by the pulse DFRX. This circuit ST supplies a binary form at the output which corresponds to that number of bits by which the signal CCNR. must be delayed so that its delay corresponds to the specified maximum delay. If, for example, synchronization is to be achieved by delaying the CCNR signals by 8 bits and the PCM system selected by the multiplexer MX Signal CCNR ^ must be delayed in order to achieve a delay of a total of δ bits.

The calculation circuit ST includes a counter CN which receives the clock signals DCLK and the three most significant thereof Outputs are fed to a register RG, which is used to store the at its input when the gate element is activated P. existing bits is determined. Thus, the time between the time determined by the pulse DFRX and the Time of receipt of the synchronous word counted number of pulses of the clock signal DCLK stored. The completion

The stored number is set to 8 by the values taken from the inverted outputs of the RG register Bits.

The three the additional. Bits expressing delay are stored by a memory circuit OM in each cell of three memories ".-Ü2" ^ 3 ^and ^ ^ M 4, which are enabled by the output pulse of the gate element P. to write at the address determined by the signals PRNR. The relevant, corresponding (i-th) outputs of the memories MM ₃ , MM ₃ and MM are combined in groups and _{fed to the address input of a multiplexer MX 4} ... MX _{11 of} a delay circuit NM, as can be seen in detail in the drawing. As shown, their data inputs are connected to the parallel outputs of shift registers RS, ·· .RS «. The latter each receive a corresponding signal CCNR, which is stored in time with the signals DCLK. If, for example, the shift registers RS -... RS ₉ each have 8 memory cells and each cell delays the signal supplied by the previous cell by one bit, the relevant multiplexer is set by the signals present at the address input so that it takes the content of that register cell which delays the signal of the corresponding PCM bundle RRCN by the value determined by the circuit SS. If, for example, the signal CCNR- has to be delayed by 3 bits in order to complete its delay to 8 bits, the multiplexer MX ₁₁ will output the signal present at the third input of the register RG _g . Signals RXCN thus appear at the outputs of the multiplexers MX .... MX ₁₁ , which all have the same delay and are therefore aligned with one another, ie, synchronized, in the required manner.

Claims (8)

Patent attorney · ° f-p ' ^ete · -v. Bezold 11237 / H / Elf Dini ° " ^{ΡθίθΓ Schötz} BREV / DB 486 _A ma! ⁸ ' ^Wo ' * 0ang Heusfer Italian note No.21477 A / 81 ^βMQr > Chen86, Poetfach 660260 from April 30, 1981 , ITALTEL Societd Italiana Telecomunicazioni s.p.a .. Milan (Italy) Circuit arrangement for the mutual synchronization of PCM bundles Patent claims: (\ J) Circuit arrangement for mutual synchronization. a number η of similar PCM bundles, which with different delays from bundle to bundle to a telecommunication nodes such as, in particular, a telephone switching matrix, where a clock signal with a given period T for Is available, characterized that a first functional unit (PHADJ) cyclically the phase of the signals of each of the η PCM bundles (RRCN) with the phase the clock signal (DCLK) of the telecommunication node compares and ^ the PCM signals are delayed by fractions of bits when the deviation between the falling edges of the clock signal (DCLK) and the level of the PCM signals falls below a specified value, and that at the output of the first functional unit (PHADJ) a second puncture unit (EiTADJ) is connected, which is the delay of the signals received by you (CCNR) of the PCM bundle to match one in a predetermined Delay value lying in the range is extended by an integer number of bits. 2.) Circuit arrangement according to claim 1, characterized in that the first functional unit (PHADJ) contains the following circuits: A time window circuit (PM) for generating a first signal (FL) and a second signal (FS), the. each define a time window of duration T ₁ <T or duration T- <T ₁ within each period T of the clock signal (DCLK); a delay circuit (SM) for delaying the signals of the η PCM bundles (RRCNq ... RRCN ₇ ) by a fixed value T ₃ <T; a test circuit (TM) that sequentially checks whether the Edges of the signals of each of the η PCM bundles (RRCN) in the first and / or the second time window (signals FL or FS) and a pulse is generated if this is not the case the case is;
25th a control circuit (QR) that for each of the η PCM bundles (RRCN) the presence or absence of the output pulse the test circuit (TM) stores and, depending on the presence of this pulse, the transmission of the signal (FL or FS) enables the first or the second time window in the memory cell assigned to the respective PCM bundle; I '' and an output circuit (QN) that the second functional unit (BTADJ) depending on the absence or presence of the output pulse of the test circuit (TM) in the corresponding memory cell of the control circuit (QR) -3- neither sends the signals of the PCM bundle (RRCN _Q .. .RRCN ₇ ) present at the input or the output of the delay ^{circuit (S 1 M).} 3.) Circuit arrangement according to claim 1 or 2, characterized in that the second functional unit ¹ 1 (BTADJ) contains the following circuits: A synchronization circuit (SS) for sequentially calling up the PCM signals (CCNR) supplied by the output circuit (QN) of the first functional unit (PHADJ) and to the Generation of an output pulse when the Presence of the synchronous word in the assigned time channel; a calculation circuit (ST), which the number of pulses of the clock signal (DCLK) between the receipt of a pulse (DFRX) corresponding to the time of the start of the frame and the appearance of the output pulse of the synchronization circuit (SS) counts and generates a code signal which the expresses the calculated number to be added to the delay to the predetermined value; a memory circuit (OM) for storing the values supplied by the calculation circuit (ST) for each of the η PCM bundles Number; and a circuit (NM) for delaying the signals (CCNRq ... CCNR ₇ ) of the PCM bundles from the output of the first functional unit (PHADJ) by the value stored in the memory circuit (OM) of the second functional unit (BTADJ). 4.) Circuit arrangement according to claim 2, characterized in that the test circuit (TM) contains the following: A (first) multiplexer (MX ..) whose data inputs are supplied with the signals (RRCN ₀ ... RRCN ₇ ) of the η PCM bundle, while its address input is controlled by signals (FRNR) which express a number, which I is increased after an interval equal to the duration of a frame; one at the output of this multiplexer is connected (first) differentiator circuit (MX ₁₎ (DR _1); a monostable multivibrator (MN) that has its output activated in response to the receipt of the pulse (DFRX) corresponding to the beginning of the frame for a predetermined time; a (first) gate circuit (P ₁ ) which is able to pass the output pulses of the differentiating circuit (DR) when the output signal of the one-shot multivibrator (MN) disappears; and with its clock input to the output of the gate circuit connected flip-flop (P ₁₎ (FF) from the D-type, whose data input the c supplied by the control circuit (QR) ₂ time window signals (FL, FS) receives. 5.) Circuit arrangement according to claim 2 or 4, characterized characterized in that the control circuit (QR) contains the following: A (first) memory (MM ₁ ) with a number η of cells which can be addressed by a signal (FRNR) which expresses a number which is increased after an interval equal to the duration of a frame; ^; a (second) multiplexer (MX2) at the address input the signal expressing this number (FRNR) and on the data input receives the output signals of the memory (MM ₁ ); two gate circuits (P ₂ , P ₃ ), whose respective first input is supplied with the first or the second time window signal (FL or FS) and which are connected to their respective second input by one of the (second) multiplexer (MX ₃ ) generated capability signal are controlled. 6.) Circuit arrangement according to claim 3, characterized in that the synchronizing circuit (SS) contains: A (third) multiplexer (MX3) whose data input the PCM signals (CCNR) are fed from the output of the first functional unit (PHADJ), and its address input through a signal (FRNR) is controlled, which is a number incremented after an interval equal to the duration of a frame expresses; a (first) shift register (RS ..) which is connected to the output of the Multiplexer (MXg) is connected; a decoder (DC) connected to the outputs of the shift register (RS _1); an identification circuit (CR) which has an output signal generated for the duration of a time slot after the appearance of the pulse (DFRX) corresponding to the start of the frame; 3Q a (second) differentiating circuit (DR ₂ ) which receives the pulses of the clock signal (DCLK) at its input; and a gate element (P ₄ ) forming the logical product, the inputs of which are connected to the outputs of the decoder (DC), the differentiating _{circuit (DR 2} ) or the identification circuit (CR). are tet. 7.) Circuit arrangement according to claim 6, characterized characterized in that the calculation circuit (ST) contains a counter (CN) whose counting input is through the pulses of the clock signal (DCLK) are fed and its reset input by the one corresponding to the start of the frame Pulse (DFRX) is controlled, as well as a register (RG) that stores the numerical value contained in the counter (CN), if the output signal of the gate element (P,) forming the logical product is present, and the binary value of these stored numerical value expressing bits inverted. 8.) Circuit arrangement according to one of claims 3 to 7, characterized in that the delay circuit (NM) of the second functional unit (BTADJ) contains a group of η shift registers (RS "... RS _g ), von.denen each of the signals ( CCNR) of a corresponding PCM bundle receives, as well as a group of η multiplexers (MX ... .MX ₁ ..), each of which is controlled at the address input by one of the calculated numbers stored in the memory circuit (X) M) and receives the output signals of a corresponding one of the shift registers (RS «... RSg) at the data input. 9,) Circuit arrangement according to claim 2, characterized in that the middle of the two time windows (Signals FL, FS) is at least approximately at the negative edge of the clock signal (DCLK).