DE2607848C2 - Method and apparatus for storing a two-valued digital signal - Google Patents

Description

is measured, where / is the average number of informative groups of a signal to be stored and s is the number of signal elements per group.

4. Memory device according to claim 3, characterized in that it contains a counting and comparison circuit (40) which emits a first control signal as soon as during writing, for detecting and evaluating the number (b) of the groups written in the signal memory (6) the condition

B / s - b = 0

is fulfilled, and that the write circuit (25, 27, 20) can be influenced by the first control signal so that all groups of the signal arriving after that regardless of their information content such as redundant groups are saved.

5. Memory device according to claim 4, characterized in that it has a counting and evaluation circuit for detecting and evaluating the number (b) of groups written into the signal memory (6) and the number (m) aWer of binary values written into the control memory (7) (40), which emits a second output signal as soon as the condition is met during writing

M - m = B / s - b

is fulfilled, and that the write circuit (26,27, 20) can be influenced by the second control signal so that all groups of the signal arriving after that regardless of their information content such as informative groups are saved.

6. Memory device according to one of claims 3 to 5, characterized in that the signal memory (6) and the control store (7) are designed as sliding stores.

The invention relates to the storage of a two-valued digital signal in which in random temporal distribution signal elements with a binary value occur in a significantly smaller number than those with the other binary value.

Because of this frequency distribution, such a signal is redundant. There is therefore the possibility to derive a signal with less redundancy from this by means of suitable coding, for further processing such as B. to base the transmission or the buffering of the coded signal and then recover the original signal by decoding. There are already different ones for this Process or facilities become known.

For example, a method known from DT-PS 12 96 182 consists in the fact that the data to be transmitted The signal to be stored is divided into groups, each with a greater number of signal elements (bits) and the groups are treated in two ways according to their information content: Troops in which the first and second binary values occur are assigned a "1" in Transferred from original form; in groups in which only the second binary value occurs, the ι Number of immediately successive equal troops counted and in their place with advance a "0" carry a group "*, which specifies the specified number as a binary number.

The coding and decoding circuits required to carry out the known method are relatively complicated. In addition, there is a reduction in redundancy only with regard to such sections of the signal, in which only signal elements with the second binary value are present, but not in the case of the bleaching circuit also with regard to such, likewise redundant sections in which only the first binary value occurs.

The invention is based on the object of a method for storing a two-valued digital To create a work with the properties mentioned at the beginning, a lesser one to implement it technical effort is required and in which the desired reduction in redundancy with regard to both binary values occur to the same extent.

In the method according to the invention, too, the 7U compressing signal is initially in groups of each divided by the same number of signal elements. To solve the problem, however, takes place Further treatment of the groups according to their information content in a different way, namely accordingly the characterizing features of the patent claim

according device for storing and cyclically repeated output of a signal with a predetermined Number of groups; and

F i g. FIG. 5 shows in a flow chart the sequence of the writing process in the embodiment of FIG

'Based on the F i g. 1 and 3 are initially the coding Writing process of the method according to the invention

explained. ,.

The in Fig. 3 shown binary signal is, as on known, in groups of signal elements (bits) divided, of which in the drawing those with 1. to 14 ·. designated groups are shown. According to FIG. 1, the first process step consists in each of the next group to check for the occurrence of at least one signal element whose binary value is different from that of the previous signal element differs, bine Such a group is hereinafter referred to as an informative group, a group without such a signal element as called redundant group. . .

If there is an informative group, it will be in the as a signal memory is written to the first memory and is also used as a control memory a "1" is written in the second memory designated. If the group in question is not informative (but redundant), only a "0" is written in the control memory. After that, the next group

checked etc. ,

According to the definition given above are therefore not

only the 1st, 4th, 7th and 13th group, but also the 9th, IU.

and 14 group informative groups; in fact

because the binary value also applies to the latter

of a signal element (namely the first in each case here

Signal element) from that of the previous one

Signal element (namely the last signal element de.

previous group).

Likewise, taking into account the definition given not only the 2nd, 3rd .. 8th .. 11th and 12th group redundant Groups, but also the 5th and 6th group, their

iruchs 1. uruppcii, suuucm _au >. ·· v .... ^. _

The 40 all signal elements by the application of the invention the binary value "1" have • - ■ • --ι j "_ u _n A -, ^ _ ,," λ nptrmirnlere occurs according to Figs 3 and I d i.

The simplification of the coding and decoding circuit that can be achieved by the method is explained, among other things from the fact that it works with two memories used in different ways, namely in such a way that these Memory both during the writing process and during the reading process as an essential part of the coding and / or coding process. Decoding circuit are effective.

The invention also relates to a memory device for performing the method, whose

■ .Ii. _. » ,. «Or * l ^ r> -, £» n riot ·

Accordingly, according to FIGS. 1 and 3, the coding storage of the 14 groups takes place in such a way that that the 1st, 4th, 7th, 9th, 10th, 13th and 14th groups are written to the signal memory and also to Assignment to these groups in the control memory each time a »1« is written. Against it will instead of the 2nd, 3rd, 5th, 6th, 8th, 11th and 12th groups only a "0" is written into the control memory. From Figure 3 it can be seen that the information of the

device for carrying out the procedure, whose nu:> rig.j ^ _{1 tu} ".. * ■,

Features and further refinements in the context of the signal shown in FIG. 50 now in the form of 7 groups

^u "^ ' ^A °" """" encoded in "rf" n in the size memory and 14 bits in the control memory

Invention are characterized in claim 2 or the further subclaims.

The invention is explained in more detail below with reference to the drawing.

Fig. 1 shows in a flow chart the sequence of the coding write process when storing a digital signal according to the inventive method, and

2 shows the sequence of the

decoding read;

F i g. 3 illustrates in a diagram the encoding write process using an example, wherein the first line the temporal course of a signal, the second line the corresponding content of the second Memory (control memory) and the third line the corresponding content of the first memory (signal memory) indicates;

P i σ 4 represents an embodiment of an inventive

aargesiemcii oigums uum, · .. _

encoded in the signal memory and 14 bits in the control memory is.

The procedural steps in decoding reading result from FIG. 2 in connection with F i g. 3. Off

F i g. 2 it can be seen that the reading process is controlled by the successive binary values in the control store will. If the binary value of the next control bit is "1", the next group to be output will be obtained by taking it from the latch

is read. If, on the other hand, the binary word of the next control bit is a "0", then the next group to be output is obtained by outputting s bits (in the exemplary embodiment 8 bits) with the previous value, i.e. with the same binary value as the last one

('S has signal element of the group previously output.

Using the Fig. 3 it is easy to see that on this Way from those contained in the two stores

Information recovered from the original signal:

Since the control memory contains a »1« in the assignment to the 1st group, the 1st group becomes the State RAM read. In assignment to the second and third group, the signal memory contains a »0« each, which is why these two groups are obtained by outputting 8 bits each with the binary value "0", etc.

F i g. 4 relates to an embodiment of a means for storing and cyclically repeating Outputting a signal with a predetermined number of signal elements or consisting of such elements Groups. It is assumed that the signal is synchronized with a bit clock. Such Signals are present, for example, in electronic image scanning.

In addition to the bit clock, via input 1, the memory device is fed a group clock via input 2, the period of which - corresponding to a number of s = 8 bits per group - comprises 8 pulses of the bit clock. A Schicib start signal corresponding to a "1" is fed via input 3. 4 denotes the signal input and 5 denotes the output for the cyclically repeated stored signal.

The signal memory 6 and the Stcucrspcicher 7 are as Sehiebcspcicher formed, at the output (right) of the binary value of each in the last stage located Signalclements occurs or is removable. The number M of storage locations in the sleuersave 7 corresponds to the intended total number of groups of the signal, while the number ßdcr storage locations of the signal memory 6 approximately according to the relationship

ti = s * l / M

is sized. Here / is the average number of informative groups of one to be saved Signal which in the case of a two-valued image scanning signal im is generally much smaller than the total number of groups.

The input of the signal memory 6 can be accessed via an OR element 8 and two AND elements 9 and 10, either with the signal line 12 coming from an input register 11 (operating state "write") or with its own output 5 (operating state and "read") get connected. The input of the control memory * 7 can be connected via an OR element 13 and two AND elements 14 and IS either to the writing part 16 ("write") or to the output of the memory ("read").

The switchover from "writing" to "reading" and vice versa is carried out by an AES flip-flop 17, Complementary outputs via line 18 "write" with AND gates 9 and 14 and via the Line 19 "read" with the AND gates 10 and 13 are connected. The one input of the flip-flop 17 is connected to input 3 so that one there incoming Schrclbunfungsslgnal the flip-flop 11 in which brings the switch position causing the "Write" operating state. The provision accordingly The operating mode and "reading" will be described further below.

Register 11 is also a viewing memory. It has s - 8 memory locations and is used for the preliminary storage of each incoming group of signal elements of the signal given by the Flitgung. Its clock input is connected to the bit clock (input 1).

The bit clock can also reach the clock input of the signal memory 6 via an AND element 20, if at the other input of the AND element 20 a "1" is present. This is then in the »Write« operating state the case when the write control line 16 - under the conditions explained below - a "1" leads. The group entered into register 11 is

ίο then while it is bit-wise out of the register is pushed out and replaced by the next group, with the same clock from the signal memory 6 accepted. If, on the other hand, the write control line 16 carries a “0”, the AND element 20 is blocked. At the Signal memory 6 does not act and the group shifted out of register U is therefore not taken over.

To check the groups that enter the register 11 one after the other whether they are informative or redundant groups, in the exemplary embodiment a test circuit consisting of an exclusive OR element is used 21 and a fiS flip-flop 22. The two inputs of the exclusive OR gate 21 are connected to the input of the first and the input of the

a? second stage of the register 11 connected. At the exit of the element 21 therefore occurs in each case an "I" when the binary values of the at the named inputs adjacent, successive signal clcmc could deviate from each other, and a "0" if they to match. The signal of the exclusive OR gate 21 sets the output 23 of the flip-flop 22 to "1" via one input. The limitation of this Statuses on the time range of the group in question are made by flip-flop 22 in each case is retracted by the next pulse of the group lactate effective at the other input.

To make the following easier to understand, think of the one between the sounding points 23 and 24 lying Verknilpfungsglieder 25 and 26 first

4 »by a simple connection. the The output of the flip-flop 22 would then be direct to the preparation input of the AM-'lip-flop 27 connected.

The tackling of the flip-flop 27 is linked to your group clock. This flip-flop has the task of taking over the state of the flip-flop 22 at the end of the respective (inippe / u and changing it for the next period of the (iruppciiliikls uti its connected to the write control line lh

Keep exit ready.

The task of the flip-flop 28 is to allow the group tuki to become effective at the clock input of the control memory 7, delayed each time by a bi-clock pulse, so that a change in the signal state to dci

Writing 16 still in the same period ir

the memory is taken over. To this

The purpose is to clock the flip-flop 28 with the Bit clock connected. The part of the Speiehcrcinrichumt described so far

fto the FI g. 4 has accordingly with regard to the writing process ci following mode of action:

From input 4 the to be saved, already mi the bit clock synchronized signal is stored bit by bit in the register II. If to any

f'5 point in time within a perlode η of the group event between successive signal elements de input signal a change of the binary word stuttfin det. is via the Exclusive-OR-Gllcd 21 for di

the remaining duration of this period the flip-flop 22 is set. Its state is taken over by the flip-flop 27 at the beginning of the period η · + - 1 and for its duration, so that the write control line 16 carries a "1" during this next period. As already explained above, this "1" causes the relevant group to be transferred from the register 11 to the signal memory 6 via the AND element 20 this inscribed. This process thus corresponds to the left branch of the flowchart in FIG. 1 and the storage, for example, of the 4th group in FIG. 3.

If, on the other hand, during the observed, one is Group of the input signal corresponding period of the group clock no change of the binary value takes place between successive signal elements, the output of the group clock retains reset flip-flops 22 have their "0", which the flip-flop 27 for the duration of the next period of the Group signal is accepted and thus also on the write control line 16, at the input of the control memory 7 and at one input of the AND element 20 is applied. This "0" becomes with the delayed group Taki transferred to the control memory 7 in association with the relevant group. The group itself will however, not taken over from register 11 by the signal memory 6 because it is blocked because of the AND gate 20 is no shift clock is effective. The write process for the relevant redundant group thus corresponds to the right branch of FIG. 1 and storing, for example, the 2nd or 5th group according to FIG. 3.

To complete the .is storage facility 1- i g. 4 and in a further embodiment of the invention between the circuit points 2J and 24 an AND gate 25 and an OR gate 26 inserted, the control of the writing vurging via the second input in the manner shown in FIG. 5.) o can be. This influence takes place through the output signals of a ZiIhI and comparison circuit

40, and their special configuration in the exemplary embodiment will first be described.

The ZiIhI and comparison circuit 40 of FIG . 4. \ F, contains a first counter called the fr counter

41, a / wide counter 42 called a / »counter and a comparator 4.3, which compares the output values of the two counters mentioned below, ν

The b-counter 41 is used to record and evaluate the number of groups of the signal to be stored that are written into the signal memory 6. The corresponding signal is fed to it by an AND element 44, the input of which is connected to the output of the flip-flop 28 (delayed group clock) and to the write control line 16. The group tnkt thus only arrives at the i> counter 4t when the write control line carries a "1", which is also the condition for writing a group into the (10 signal memory 6. The number b , however, becomes not additively, but subtractively. Before each new write operation, i.e. at the beginning of each signal to be stored, the fc counter is triggered by the writing request signal arriving at input 3 in such a way that it is connected to the number B / s is loaded.

B / s corresponds to the number of groups stored in the signal memory b. The value B / s - b , which corresponds to the still available “group capacity” of the signal memory 6, is accordingly formed in the b-counter 41. It is fed to one input of the comparator 43. At a further output, the δ counter 41 sends a “1” as a control signal “write lock” to an inverter 29 connected upstream of the AND element 25 as soon as

B / s - b = 0

has become. From this point in time, the output of the AND element 25 is independent of the switching state of the flip-flop 22 a "0", which is also sent to the write control line 16 with the next group clock is applied.

The m-counter 42 is used to record and evaluate the number / 7) of all binary values written into the control memory. For this purpose, its entrance is connected to the group tent. At the beginning of each write operation, the counter is normalized by the write start signal in such a way that it is loaded with the number M, corresponding to the total number of storage locations in the control memory 7. The value M - m is formed in the / »counter 42, which corresponds to the number of memory locations still available in the control memory 7. It is fed to the other input of the comparator 43. At a further output, the n; counter 42 outputs a "1" to the flip-flop 17 as soon as M -m = 0 . As a result, the flip-flop reaches its sound position causing the “reading” operating state, in which an “I” is applied to the line 19. This operating state will be explained in more detail below.

When B / s - b = M - m , the comparator "43 sends a" 1 "as the control signal" Diuierschroibcn "to the / wide input of the OR element 26. From this point in time the output of the OR element is independent of the switching state of the flip-flop 22 and the / 'counter 41 a "1", which is also applied to the Sehreibsieuerleitung 16 with the next group clock,

In a modification of the working method already described in the "Write" operating state, the complete memory device is shown in FIG. 4, under Taking into account the output signals of the counting and comparing circuit 40, the following operating mishap while writing:

A Sehreibunl'angssignnl arriving at input 3 loads the / 'counter 41 with the initial value H / s. the Hi counter 42 with the initial value M and brings you ¹ · IΊιρ-1'lop 17 to the "write" corresponding "Suluillicllung". From this point in time, the first step based on FIG. I and J in principle and with the aid of FIG. 4, the normal writing process already explained in detail instead:

When an informative group arrives in register 11, the exclusive OR element 21 and the flip-flop 22 via the AND gate 23 and the OR gate 26 and the input of the flip-flop 27 unites "I" given, with the result that during the whole ci In the next period of the group clock, the Schroib control line 16 carries an "I", the group concerned In dct Sigmtlspeichcr 6 is taken over and In dci Control memory 7 a "1" is stored. Ii assignment to a redundant group leads to dii Script control line 16 has a "0", and only this becomes In Control memory 7 saved.

If a slgnul with an above average large number b of informative groups /

/ (Kl (M / M

is stored, the signal memory 6 will already be full if the control memory 7 still has a number of free memory locations due to the explained dimensioning of the number of memory locations B in the signal memory 6 and M in the control memory 7. In the interest of the simplest possible read circuit for the cyclical output of the signal, provision is made for both memories to be full at the end of the signal. This is achieved with the help of the output signal of the b-counter 41:

As soon as B / s - b = 0, the b counter sends a "1" to the inverter 29 as the signal "write lock", so that at the output of the AND element 25 and then via the OR element 26 and the Flip-flop 27 also has a “0” on write control line 16. All groups that arrive thereafter are therefore stored as redundant groups, regardless of their information content, according to FIG. 5, until the control memory 7 is filled with zeros. In the cases of particular interest, the associated format clipping of the signal is not disruptive. As soon as M - m = 0, ie the control store 7 is also full, the m counter 42 sends a signal to the flip-flop 17, which switches it to "read". The AND gates 9 and 14 are blocked so that writing is no longer possible.

If, on the other hand, a signal is to be stored in which the number b of the informative groups is below the average, the control memory 7 would be full (Λ7 - m = 0) and the signal memory 6 still had a number of empty spaces at the time of the end of the signal. c have. This is avoided with the aid of an output signal from the comparator 43:

As soon as the number of free memory locations (B / s - b) of the signal memory 6, based on groups, and (Λ / - m) of the control memory 7 has become the same, the comparator 43 outputs a "1" as the "Continuous writing" signal. to the OR gate 26, so that a "1" is constantly present at its output and then via the flip-flop 27 on the write control line 16.

All groups of the signal arriving from this point in time are therefore stored in the signal memory like informative groups, regardless of their information content according to FIG. 5. At M - m - 0 the flip-flop 17 is automatically switched back to "read".

In the "Read" operating state, the inputs of the two memories 6 and 7 are via the AND gates 10 and 15 connected to the respective output. The content of the control memory 7 is still with the Clock input effective group clock shifted evenly and cyclically. At the clock input of the signal memory on the other hand, the bit clock is only present via the AND element 20 when the output (= input) of the Control memory 7 an "I" occurs. The relevant group is then at the output 5 of the signal memory 6 tapped. If it is z. B. is the I. group of Fig. 3, is the last, at the output of the Signal element occurring in the signal memory is a »0«. In this state, the signal memory 6 remains during the next and the next but one period of the group clock, i.e. for the duration of s bits, there then according to Figure 3 at the output of the control memory 7 corresponding to the 2nd and 3rd group of the signal a "0" is displayed and is therefore not available in the signal memory 7

} o clock signal takes effect.

The reading process according to the invention according to FIG. 7 is thus achieved in the simplest manner in that: the bit clock for the signal memory 6 is via there; AND gate 20 corresponding to the output signal de;

vs control memory 7 is released or locked.

Hlatl drawings

Claims (3)

Patent claims: 1. Method of storing a two-valued digital signal in which in random time Distribution of signal elements with one binary value occur in significantly fewer numbers than Signal elements with the other binary value, with the signal in groups of the same number is divided by signal elements (bits) and the Groups according to their information content in to be treated further in two ways, g e -characterized by the features that a) if there is a group with at least one signal element whose binary value differs from that of the previous signal element, this group (informative group) is written into a first memory (signal memory) and also, in association with this group, into a second memory (control memory ) a "!" is inscribed, b) if there is a group without such a signal element, in assignment to this (redundant) Group, only a "0" is written into the second memory, and c) when reading, according to the successive binary values in the second memory, either the next group located in the first memory is output or a Group is output whose signal elements have the binary value of the last Have signal element of the previously output group. 2. Storage device for performing the method according to claim I _1, characterized in that it contains the following parts: a) a test circuit (21, 22) for testing successive groups of the signal, each consisting of the same number (s) of signal elements (bits), corresponding to a group clock corresponding to this number, for the occurrence of at least one signal element whose binary value differs from that of the previous signal element deviates, b) a first memory (signal memory) (6) into which the signal is written in groups can be, c) a second memory (control memory) (7), in the assignment to the individual groups a »1« or a »0« can be written into the signal, d) a write circuit (9, 14, 20, 27), which from the output signal of the test circuit (21, 22) is controlled in such a way that if an informative group is present, they will be registered in the signal memory (6) and the writing of a "1" in the control memory (7) and if there is a redundant group, a »0« is written into the control memory (6) causes, and (10 e) a reading circuit (10, 15, 20) which is controlled by the binary values that are consecutively retrieved in the control store (7) according to the group cycle of the reading process so that the next group in the signal store (6) is output on the basis of a "1" , and due to a "0" a group is output whose signal values all have the binary value of the last signal element of the previously output group. 3. Storage device according to claim 2, for storing and cyclically repeated outputting of a signal with a predetermined number of signal elements or groups consisting of such, characterized in that the number (M) of storage locations in the control memory (7) corresponds to the intended total number of groups of the signal, while the number (finder memory locations of the signal memory (6) approximately according to the relationship β = s- l / M