GB1568292A - Method and a device for storing a binary digital signal - Google Patents

Description

(54) A METHOD AND A DEVICE FOR STORING A BINARY DIGITAL SIGNAL (71) We, LICENTIA PATENT VERWAL TUNGS G.mb.H., of 1 T;heodor-Stern"Kai, 6 Frankfurti Iain 70, Federal Republic of Germany, a German body corporate, do hereby declare the invention. for which we pray that a patent may be granted to us, and the method by which it is to be per formed, to be particularly described in and by the following statement: The invention relates to storage of a binary digital signal in which signal elements which are of uncontrolled time distribution and have one binary value occurring in a sub stantially "smaller number than those having the other binary value.

This type of signal is redundant because ef this frequency distribution. Therefore there is the opportunity to derive a signal having a small redundancy by means of sMit- ae coding, to base further processing, for example transmission or intermediate store age, on the coded signal and to regain the original signal by means of decoding. Tlius different methods or devices have become known.

For example, a method known from Ger man Patent Specification No. 12 96 182 lies in the fact that the signal which is to be transmitted or stored is subdivided into groups of the same number of signal ele ments (bits) and the groups are further pro cessed according to their information con tent in two ways: groups in which the first and second binary value occur are trans mitted in the original form by prefixing a "1"; in groups in which only the second binary value occurs the number of immedi ately successive equal groups is counted and a group is transmitted at its position by pre fixing a "0", which group states the said number as a binary number.

The coding and decoding circuits re quire for carrying out the known methods -relatively complicated. Moreover, the reduction in redundancy only takes place with respect to those portions of the signal In which. over several groups, those signal elements with the second binary value are present exclusively but, in the same circuit.

not with respect to those portions which are also redundant, in which the first binary value occurs exclusively.

The invention seeks to provide a method of storage of a binary digital signal having the properties stated at the outset, a small technical outlay being necessary for carrying this out and in which the sought after reduction in redundancy occurs to the same extent with regard to both binary values.

According to a first aspect of tbe invention, there is provided a method of storing a binary signal comprising dividing the signal into groups, each containing a plurality of bits, storing the individual groups in a signal store only when the group has a bit which varies from the bit preceding it form- ing an informative group and storing in a control store a first representative value for those groups stored in the signal store and a second representative value for groups, being redundant groups, not stored in the signal store.

Preferably when reading out from the store, in accordance with the successive values in the control store, either the next group located in the signal store is emitted or a group is emitted, all of the signal elements of which have the binary value of the last signal element of the previously emitted group.

The simplification in the coding and decoding circuit which may be achieved by use of the method in accordance with the invention is made clear among other things from the fact that it operates with two stores used in a different manner and in fact such that these stores are effective both during the writing process and during the reading process as a substantial part of the coding and decoding circuit.

According to a second aspect of the invention, there is provided a device for storing a binary signal comprising means for dividing the signal into groups, a test circuit for determining the groups which have a bit varying from the bit preceding it and for supplying a first value when the varying bit is found in the group thus forming an informative group and a second value when the varying bit is not found, in the group thus forming a redundant group, a signal store for storing the informative groups and a control store for storing the first and second values.

Preferably a write circuit is provided controlled by the output signal of the test circuit such that when the first value is present it causes the associated group to be registered in the signal store and it causes registration of a "1" in the control store and when the second value is present it causes registration of a "0" in the control store and a read circuit is provided which is controlled by the successive binary values in the control store which have been called up according to a group clock pulse of a read process such that when "1" is called up from the control store, the next group located in the first store is emitted and when a "0" is called up from the store a group is emitted, all of the signal values of which have the binary value of the last signal element of the previously emitted group.

The invention will now be described in greater detail, bq way of example, with reference to the drawings, in which: Figure 1 shows in a flow diagram the path of the coding writing process during storage of a digital signal according to the method in accordance with the invention; Figure 2 shows, in a flow diagram, the path of the decoding reading process; Figure 3 makes the coding writing process clear in a diagram together with an example wherein the first line shows the time curve of a signal, the second line shows the corresponding content of the second store (control store) and the third line shows the corresponding content of the first store (signal store);; Figure 4 represents an embodiment of a device in accordance with the invention for storage and cyclical repeated transmission of a signal having a predetermined number of groups; and Figure 5 showy in a flow diagram. the path of the writing process in the embodiment of Figure 4.

Initially the coding writing process of the method in accordance with the invention is described together with Figures 1 and 3.

The binary signal shown in Figure 3 is subdivided as is known per se into groups of s signal elements (bits) in each case, and of these, the groups designated 1 to 14 are shown in the drawing. In accordance with Figure 1 the first method step comprises checking the next group respectively for the occurrence of at least one signal element, the binary value of which deviates from that of the preceding signal element. This type of group is designated as an informative group in the following, a group without this type of signal element is designated as a redundant group.

If an informative group is present, then it is registered in the first store designated a signal store and, moreover, a "1" is written into the second store, designated as the control store. If the relevant group is not informative (but redundant), then a "0" is written into the control store only. The next group is checked accordingly, and so on.

According to the above-stated definition not only are groups 1., 4., 7. and 13. informative groups but also groups 9., 10. and 14 and in fact this is because in the lastmentioned the binary value of a signal element (i.e. of the respective first signal element) deviates from that of the preceding signal element (i.e. the last signal element of the preceding group).

Similarly while taking account of the given definition not only are groups 2., 3., 8., 11.

and 12. redundant groups but also groups 5. and 6. all of the signal elements of which have the binary value"1".

As a result in accordance with Figures 1 and 3 the coding storage of the 14 groups takes place in this manner: groups 1., 4., 7., 9., 10., 13 and 14. are written into the signal store and moreover a "1" is registered in the control store respectively in assignment to these groups. On the other hand instead of groups 2., 3., 5., 6., 8., 11. and 12 only a "0" is registered in the control store.

From Figure 3 it may be seen that the information of the shown signal is coded in the form of 7 groups in the signal store and 14 bits in the control store.

The method steps during decoding reading are evident from Figure 2 in conjunction with Figure 3. From Figure 2 it may be seen that the read process is controlled by means of successive binary values in the control store. If the binary value of the next control bit is a "1" then the next group to be transmitted is obtained by reading from the signal store. If the binary value of the next control bit on the other hand is a "0" then the next group to be transmitted is obtained by transmitting s bits (in the embodiment 8 bits) with the previous valency, thus with the same binary value which the last signal element of the previously transmitted group has.

Together with Figure 3 it is easily seen that in this manner the original signal is regained from the information contained in the two stores: As, in assignment to the 1st group, the control store contains a "1" then the 1st group is read from the signal store. In assignment to the second and 3rd group.

tlie signal store'contains a "0" respectively for which reason these two groups are ob tamed by transmitting 8 bits having the binary value "0" respectively and so on.

Figure 4 relates to an embodiment of a device for storage and cyclically repeated ttansmission of a signal having a predetermined number of signal elements or comprising groups consisting thereof. It is stipu ted that it is a question of a signal synchronized with a bit clock pulse. These signals are present for example in electronic image scanning.

Besides the bit clock pulse via input 1, a group clock pulse is supplied via input 2 to the storage device, the period of which corresponding to a number of s=8 bits per groupencompasses 8 pulses of the bit clock pulse. A signal for the beginning of writing and corresponding to "1" is supplied via input 3. The signal input is designated 4 and the output for the cyclically repeated stored signal is designated 5.

The signal store 6 and the control store 7 are constructed as shift stores, at the output (on the right) of which the binary value of the signal element, located in the last stage, occurs or may be derived. The number M of storage places in the control store 7 corresponds to the total number of groups of the signal provided, while the number B of storage places of the signal store 6 is di mentioned approximately according to the relationship B=s.I.

where I is the average number of informa tive groups of a signal to be stored, said number being generally substantially smaller in a binary image scanning signal than the total number of groups and s represents the number of signal elements per group.

The input of the signal store 6 may be connected via an OR-element 8 and two AND-elements 9 and 10 as desired to the signal line 12 coming from an input register 11 (operating condition "writing") or to its own output 5 (operating condition "read").

The input of the control store 7 is capable of connection to the writing control line 16 ("write") or to the output of the store ("read") via an OR-element 13 and two AND*elements 14 and 15 as desired.

Switching over from "write" to "read" and vice versa "takes place by means of a RS trigger stage 17, the complementary outputs of which are connected via the line 18 "write" to the AND-elements 9 and 14 and via the line 19 "read" to the AND-elements 10 and 15. One input of the trigger stage 17 is connected to the input 3 so that an in coming signal for the beginning of writing brines the trigger stage 11 into the switching position causing the operating condition "write". Resetting in accordance with the operating conditions "read" will be" des- cribed below.

The register 11 is also a shift store. It has s=8 storage places and serves for preliminary storage of each incoming group of signal elements of the signal supplied by the input 4. Its clock pulse input is connected to the bit clock pulse (input 1).

The bit clock pulse may reach the clock pulse input of the signal store 6 via an AND-element 20 if a "1" is present at the other input of the AND-element 20. This is the case under the operating conditions "write" if the control line 16 for writing -under preconditions described below- passes a "1". The group which has gone" in to the register 11 is taken over by the signal store 6 at the same clock pulse while it is shifted out in bits from the register and is replaced by the next group. If on the other hand the control line 16 for writing passes a "0" then the AND-element 20 is blocked.

There is no shift clock pulse at the signal store 6 and the group shifted out of the register 11 is not taken over.

A test circuit which comprises an exclusive OR-element 21 and a RS trigger circuit 22, serves in the embodiment to test the groups incoming into the register 11 successively as to whether it is a question of informative or redundant groups. The two inputs of the exclusive OR-element 21 are connected to the input of the first and the input of the second stage of the register 11.

A "1" occurs at the output of the element 21 when the binary values of the successive signal elements present at the said inputs deviate and a "0" occurs if they coincide.

The signal of the exclusive OR-element 21 sets the output 23 of the trigger stage 22 to "1" by means of one input. Limitation of the condition to the time range of the relevant group takes place by resetting the trigger stage 22 by means of the next pulse of the group clock pulse effective at the other input.

For easier understanding of the following, the linking elements 25 and 26 between the circuit points 23 and 24 should be thought to be replaced initially by a simple connecting line. The output of the trigger stage 22 would then be directly connected to the preparation input of the D-trigger stage 27.

The clock pulse input of the trigger stage 27 is connected to the group clock pulse.

This trigger stage has the object of taking over the condition of the trigger stage 22 at the end of the relevant group and to make it ready for the duration of the next re spective period of the group clock pulse at its output which is connected to the control line 16 for writing.

The trigger stage 28 has the object of making the group clock pulse which is de-- layed respectively by a bit clock pulse period effective at the clock pulse input of the control store 7, so that a change in the signal condition on the control line 16 for writing is taken over into the control store in the same period. For this purpose, the clock pulse input of the trigger stage 28 is connected to the bit clock pulse.

The part of the storage device of Figure 4 previously described has the following modd of operation with respect to the writing pro cress: The signal to be stored which is already synchronized with the bit clock pulse is stored in the register 1 1. in bits from the input 4. If at any point in time within a period n of the group clock pulse between successive signal elements of the input signal there is a change in the binary value, then the trigger stage 22 is set for the remaining duration of this period via the exclusive OR-element 21. Its condition is taken over at.the beginning of the period n+l and is taken over for -its duration by the trigger stage 27 so that during this next period the control line 16 for writing passes a "1".Via the -AND-element 20-this "1" on the one hand, as already described, causes the takeover of the relevant group from the register 11 into the signal store 6. On the other hand it is also applied to the input of the control store 7 and is registered'therein with the due layed group clock pulse. This process corresponds to the left-hand branch of the flow diagram of Figure 1 and storage for example of the 4th group in Figure 3.

If on the other hand, during the period of the group clock pulse which is under consideration and which corresponds to a group of the input signal, there is no change in the binary value between successive signal elements, then the output of the trigger stage 22 which- is reset by the group clock "pulse retains its "0", which is taken over by- tlie trigger stage 27 for the duration of the next period of the group signal and thus is ap plied to the control line 16 for writing at the input of the control store 7 and at one input of the AND-element 20. This "0" is taken over into the control store 7 with the delayed group clock pulse assigned to the relevant group.However the group itself is not taken over from register 11 by the signal store 6 as there is no shift doe""k "pulse effective there becauseof the blocked AND-element 20.

The writing process for the relevant re dundant group thus corresponds to the right hand branch of Figure 1 and to storage for example of the 2nd or the 5th group ac cording to Figure 3.

In order to complete the storage device of Figure 4 and in further developnient of the invention, an AND-element 25 as weil as an OR-element 26 are insertedt between the switching points 23 and 24 via the second input of which control of the writing process may be influenced in the manner shown in Figure 5. This influence takes place by means of output signals of a counting and comparison circuit 40 and its special refinement will be described hereafter.

The counting and comparison circuit 40 of Figure 4 contains a first counter 41 designated as a b-counter, a second counter 42 designated as a counter, and a comparator 43 which compares together output values,. stated below, of the two counters.

The b-counter 41 serves to detect and evaluate the number b of groups of the sigiial to be stored which have been registered in the signal store 6. The appropriate signal is supplied to it by an AND-element 44 the input of which is connected to the output of the trigger. stage 28 (delayed group clock pulse) and to the control line 16 for writing.

The group clock pulse only reaches the bcounter 41 if the control line for writing passes a "1" which is also the condition for registering a group in- the signal store 6.

Tbe number b is not counted additively however but subtractively. Before each new writing process, i.e. at the beginning of each signal to be stored, the- b-counter is normed by the signal for the beginning of'writing incoming at input 3: in the following man ner: it is charged with the number B/s.

B/s corresponds to the number of groups which may be stored in the signal store 6.

The value (B/s-b) is accordingly formed in the b-counter 41 said value corresponding to the 'group capacity'?-of the signal store 6 which is still available. It is supplied to one input of. the comparator 43. The bcounter 41 passes a "1" to an inverter 29 connected at the input side of the AND-element 25 as a control signal "barrier to writing" at a further input, as soon as B/s-b=0 has become the case. The output of the AND-element 25 passes a "0" from this point in time onwards independent of- the switching condition of the trigger stage 22, which "0" is applied at the control line 16 for writing with the next group clock pulse.

The nt-counter 42 serves to detect and evaluate the number m of all binary values registered in the control store. Its input is thus connected to the group clock pulse.

The counter is wormed at the beginning of each writing process by the signal for the beginning of writing in the following manner: it is charged with the number M, cor responding to the total number of storage places in the control store 7. The value (M-m) is formed in them-counter 42, which corresponds to the respective number of storage places still available in the con trol store 7. It is supplied to the other input of the comparator 43.At a further output tb. counter 42 passes a "1" to the trigger slage 17, as soon as M-m=0. As a result the trigger stage passes into its switching position, causing the operating conditions "read", in which switching position a "1" is applied to the line 19. These operating conditions are described in greater detail below.

If B/s-b=M-m then the comparator 43 passes a "1" to the second input of the OR-element 26 as a control signal "continue writing". From this point in time onwards, the output of the OR-element passes a "1" independently of the switching conditions of the trigger stage 22 and of the bcounter 41, said "1" being applied to the line 16 for controlling writing with the next group clock pulse.

In modification of the mode of operation already described under the operating conditions "write", there is the following operation behaviour during writing for the complete storage device of Figure 4, taking the output signals of the counting and comparison circuit 40 into consideration: A signal for the beginning of writing incoming at input 3 charges the b-counter 41 with the initial value B/s, the m-counter 42 with,' the initial value M and brings the trigger stage 17 into the switching position corresponding to the operating conditions ""write". From this point in time onwards, the normal writing process- - described- basically by way of Figures 1 and, 3 and described in detail by way of Figure 4 takes place:: When an informative group arrives in the register 11 a "1" is passed buy means of the exclusive OR4ement 2:1 and the rigger age 22, via the - AND-element 25- and the 0-element 26 to the input of the trigger stage 27, this having the result that, during the entire next period of the group clock pulse, the line 16 for controlling writing passes a "1", the relevant group is taken over into the signal store 6 and a "1", is stored in the control store 7.In assignment to a redundant,oup, the line 16 for controlling writing passes a "Q" and only, this is stored in the control store 7. If a signal is to be stored with an above average number" -h of informative groups tben, because of the described dimensions of the number of storage places B in the s-Li, store 6 and M -in the control store 7, the signal store 6 will already be full when the control store - 7 still has a number of free storage places In the interests of the simplest read circuit for the cyclic transmission of the signal however, .p"royiion is, made for both stores to be full at the end of the signal. This is achieved with the aid of the output signal of the counter 41: In fact as soon as B/s-b=0 the bcounter passes a "1" to the inverter 29 as a signal "stop to writing" so that a "0" is applied to the output of the AND-element 25 and thereafter, via the OR-element 26 and the trigger stage 27, also to the line 16 for controlling writing. All subsequently incoming groups are therefore stored independently of their information content in accordance with Figure 5 as redundant groups until the control store 7 is filled up with noughts. In particularly interesting applications, the involved clipping of the format of the signal is not disruptive.As soon as M-m=0, i.e. the control store 7 is full, the m-counter 42 gives a signal to the trigger stage 17 which switches this to "read".

Thus the AND-elements 9 and 14 are blocked so that writing in is no longer -pos- sible.

If on the other hand a signal is to be stored in which the number b of informative groups is below average then at the time of the end of the signal, the control store 7 would be full (M-m=0) and the signal store 6 would still have a number of empty places. This is avoided with the aid of an output signal of the comparator 43:' As soon as the number of still free ster age places (B/s-b) of the signal store 6, relating to groups, and -(M-m) of the', con- trol store 7 has became the same size, then the comparator 43 passes a "1" to the ORelement 26 as a signal "continue to write", so that a "1" is always applied to its output and to the line 16 for controlling writing via the trigger stage 27.All groups of the signal incoming from this point in time onwards are thus stored in the signal store independently of their information content in accordance with Figure 5 as informative groups. When -M-m=0 the trigger stage 17 is again switched over automatically to "read".

-Under the operating conditions "read", the inputs of the two stores 6 and 7 are connected via the ASP-elements-10 or 15 to the respective output. The content of the control store 7 its shifted cyclically and in a uniform manner with the group clock pulse which is still effective at the clock pulse input. The bit - clock pulse -is then applied to the clock pulse input of the signal store on.

the other hand via the -AND-element 20 if,' there, is a "1"- at the output (=input)':of the control store 7. The relevant group may be taken off at the output 5 of-the signal store 6. If for example it is a question of the 1st group of Figure-3, then its last signal element occurring, at the- output -of- the signal store is "0".Under these conditions the signal - store 6 remains during the next and the next but- one period of the group clock puls therefore for the duration of s bits, as then according to Figure 3 a "0" is present at the output of the control store 7 in accordance with the 2nd and 3rd group of the signal and thus there is no clock pulse signal effective at the signal store 7.

The read process according -to Figure 2 in accordance with the invention is thus achieved in the simplest manner by relXg or blocking the bit clock pulse for the signal store 6 via the AND-element 20 ac- cording to the output signal of the control store 7.

WHAT WE CLAIM IS:- 1. A method of storing a binary signal comprising dividing the signal into groups, each containing a plurality of bits, storing" the individual groups in a signal store only when the group has a bit which varies from the bit preceding it forming an informatíve group and storing in a control store a first representative value for these groups stored in the signal store and a second representative value for groups, being redundant ttups, not stored iii the signal store.

2. A method as claimed in claim 1, Wherein when reading out from the store, ifl accordance wlth the successive values in the control store, either the next group located in the signal store is emitted or a group Is emitted. all of the signal elements of which have the binary value of the last signal element of the previously emitted group.

3. A device for storing a binafy signal comprising means for dividing the signal into groups, a test circuit for determining the groups which have a bit varying from the bit preceding it and fot supplying a first value when the varying bit is found in the thus thus firming an informative group and a value when the varying bit is not found in tht group thus forming a re dundant group, a signal store for storing the informative groups and a control store fof storing the first and second values.

4. A device ds claimed in claim 3, wherein a write circuit is provided controlled by the output signal of the test circuit sllch that then the first value is present it causes the associated group to be registered in the signal store and it causes rEgistration of a "1" in the control store and when the second value is present it causes registration of a "O" in the control store and wherein a fead circuit is provided which is con trolled by the successive binary values in the control store which have been called up cording to a group clock pulse of a read process such that when "1" is called up from the control store the next group located in the first store is emitted and when a '09 iS called tXp from the control storC a group is emitted, all of the signal values of which have the binary value of the last signal element of the previously emitted group, 5 A device as claimed in claim 4 for storage and cyclically- repeated transmission of a signal having a predetermined number of signal- elements or groups of signal elements, wherein the number of the storage places of the control store corresponds to the provided total number of groups of the signal, while the number of the storage places of the signal store is dimensioned according to the relationship B=s.I wherein B represents the number of storage places of said signal store, I represents the average number of informative groups of a signal to be stored, s represents the number of signal elements per group.

6. A storage device as claimed in claim 5, wherein a counting and comparison cir cuit are provided for the purpose of detect ing and evaluating the number of groups registered in the signal store, which emits a first control signal, as soon as the follow- ing condition is fulfilled during writing: B/s-b=0 where b is the number of groups registered in the signal store the writing circuit being so influenced by the first control signal that all subsequent incoming groups of the signal are stored independently of their informa- tion content as redundant groups.

7. A storage device as claimed in claim 4 or 5, wherein a counting and evaluating circuit b provided for detecting and ewlus ating the number of groups registered in the signal store and the number of all binary values registered in the control store, the circuit transmitting a second output signal as soon as the condition M-m=B/s-b where M represents the number of storage places in the control store m represents the number of groups registered in the control store and b represents the number of groups registered in the signal store, is fulfilled during writing, the writing circuit being so influenced by the second control signal that all subsequentl5t incoming groups' of the signal are stored independently of their in formation content as intormative groups.

8. A storage device as claimed in any one of claims 3 to t wherein the signal store and the control store are cOnstructed as shift stores.

. A method of storing a ioinaty signal

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (1)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   accordance with the 2nd and 3rd group of the signal and thus there is no clock pulse signal effective at the signal store 7.

   The read process according -to Figure 2 in accordance with the invention is thus achieved in the simplest manner by relXg or blocking the bit clock pulse for the signal store 6 via the AND-element 20 ac- cording to the output signal of the control store 7.

   WHAT WE CLAIM IS:-

   1. A method of storing a binary signal comprising dividing the signal into groups, each containing a plurality of bits, storing" the individual groups in a signal store only when the group has a bit which varies from the bit preceding it forming an informatíve group and storing in a control store a first representative value for these groups stored in the signal store and a second representative value for groups, being redundant ttups, not stored iii the signal store.

   2. A method as claimed in claim 1, Wherein when reading out from the store, ifl accordance wlth the successive values in the control store, either the next group located in the signal store is emitted or a group Is emitted. all of the signal elements of which have the binary value of the last signal element of the previously emitted group.

   3. A device for storing a binafy signal comprising means for dividing the signal into groups, a test circuit for determining the groups which have a bit varying from the bit preceding it and fot supplying a first value when the varying bit is found in the thus thus firming an informative group and a value when the varying bit is not found in tht group thus forming a re dundant group, a signal store for storing the informative groups and a control store fof storing the first and second values.

   4. A device ds claimed in claim 3, wherein a write circuit is provided controlled by the output signal of the test circuit sllch that then the first value is present it causes the associated group to be registered in the signal store and it causes rEgistration of a "1" in the control store and when the second value is present it causes registration of a "O" in the control store and wherein a fead circuit is provided which is con trolled by the successive binary values in the control store which have been called up cording to a group clock pulse of a read process such that when "1" is called up from the control store the next group located in the first store is emitted and when a '09 iS called tXp from the control storC a group is emitted, all of the signal values of which have the binary value of the last signal element of the previously emitted group, 5 A device as claimed in claim 4 for storage and cyclically- repeated transmission of a signal having a predetermined number of signal- elements or groups of signal elements, wherein the number of the storage places of the control store corresponds to the provided total number of groups of the signal, while the number of the storage places of the signal store is dimensioned according to the relationship B=s.I wherein B represents the number of storage places of said signal store, I represents the average number of informative groups of a signal to be stored, s represents the number of signal elements per group.

   6. A storage device as claimed in claim 5, wherein a counting and comparison cir cuit are provided for the purpose of detect ing and evaluating the number of groups registered in the signal store, which emits a first control signal, as soon as the follow- ing condition is fulfilled during writing: B/s-b=0 where b is the number of groups registered in the signal store the writing circuit being so influenced by the first control signal that all subsequent incoming groups of the signal are stored independently of their informa- tion content as redundant groups.

   7. A storage device as claimed in claim 4 or 5, wherein a counting and evaluating circuit b provided for detecting and ewlus ating the number of groups registered in the signal store and the number of all binary values registered in the control store, the circuit transmitting a second output signal as soon as the condition M-m=B/s-b where M represents the number of storage places in the control store m represents the number of groups registered in the control store and b represents the number of groups registered in the signal store, is fulfilled during writing, the writing circuit being so influenced by the second control signal that all subsequentl5t incoming groups' of the signal are stored independently of their in formation content as intormative groups.

   8. A storage device as claimed in any one of claims 3 to t wherein the signal store and the control store are cOnstructed as shift stores.

   . A method of storing a ioinaty signal

   substantially as described herein with reference to the drawings.

   10. A device for storing a binary signal substantially as described herein with refer alice to the drawings.