PT74815B - Circuit arrangement designed to align one to the other a plurality of pcm bundles that reach a communication node - Google Patents

Circuit arrangement designed to align one to the other a plurality of pcm bundles that reach a communication node

Info

Publication number
PT74815B
PT74815B PT74815A PT7481582A PT74815B PT 74815 B PT74815 B PT 74815B PT 74815 A PT74815 A PT 74815A PT 7481582 A PT7481582 A PT 7481582A PT 74815 B PT74815 B PT 74815B
Authority
PT
Portugal
Prior art keywords
pcm
bundles
align
reach
circuit arrangement
Prior art date
Application number
PT74815A
Other languages
Portuguese (pt)
Other versions
PT74815A (en
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Spa filed Critical Italtel Spa
Publication of PT74815A publication Critical patent/PT74815A/en
Publication of PT74815B publication Critical patent/PT74815B/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
PT74815A 1981-04-30 1982-04-28 Circuit arrangement designed to align one to the other a plurality of pcm bundles that reach a communication node PT74815B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8121477A IT8121477A0 (en) 1981-04-30 1981-04-30 CIRCUIT ARRANGEMENT SUITABLE TO ALIGN TOGETHER A PLURALITY OF COHERENT PCM BANDS THAT REACH A COMMUNICATION NODE.

Publications (2)

Publication Number Publication Date
PT74815A PT74815A (en) 1982-05-01
PT74815B true PT74815B (en) 1983-11-30

Family

ID=11182405

Family Applications (1)

Application Number Title Priority Date Filing Date
PT74815A PT74815B (en) 1981-04-30 1982-04-28 Circuit arrangement designed to align one to the other a plurality of pcm bundles that reach a communication node

Country Status (9)

Country Link
BR (1) BR8202163A (en)
DE (1) DE3216040A1 (en)
ES (1) ES511762A0 (en)
FR (1) FR2505108A1 (en)
GB (1) GB2102251A (en)
GR (1) GR76041B (en)
IT (1) IT8121477A0 (en)
PT (1) PT74815B (en)
YU (1) YU90982A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2601534B1 (en) * 1986-07-10 1993-07-30 Cit Alcatel METHOD AND DEVICE FOR PHASE TIMING OF SYNCHRONOUS DIGITAL TRAINS
CA2050650A1 (en) * 1990-11-28 1992-05-29 Shahrukh S. Merchant Phase aligner

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE789775A (en) * 1971-10-06 1973-04-06 Siemens Ag MUTUAL SYNCHRONIZATION OF THE CENTRAL RATE OSCILLATORS OF A PCM TELECOMMUNICATIONS SYSTEM WITH MULTIPLEXING IN TIME
DE2247666C2 (en) * 1972-09-28 1975-02-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Circuit arrangement for the mutual synchronization of the exchange clock oscillators provided in the exchanges of a PCM time division multiplex telecommunications network
DE2641547C2 (en) * 1976-09-15 1980-11-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Procedure for taking over PCM information
DE2936938A1 (en) * 1979-09-12 1981-04-02 Siemens AG, 1000 Berlin und 8000 München CIRCUIT ARRANGEMENT FOR COMPENSATING THE PHASE DIFFERENCES BETWEEN THE DISTANCE CLOCK ON A PCM TIME MULTIPLEX LINE CONNECTING TO A PCM SWITCHING CENTER AND THE OFFICIAL STOCK OF THIS SWITCHING CENTER

Also Published As

Publication number Publication date
GR76041B (en) 1984-08-03
PT74815A (en) 1982-05-01
YU90982A (en) 1985-03-20
GB2102251A (en) 1983-01-26
FR2505108A1 (en) 1982-11-05
IT8121477A0 (en) 1981-04-30
ES8304391A1 (en) 1983-03-16
ES511762A0 (en) 1983-03-16
DE3216040A1 (en) 1982-11-25
BR8202163A (en) 1983-03-29

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