DE3209737C2 - Circuit arrangement for regulating an alternating voltage that can be output by a transformer - Google Patents

Abstract

In the control circuit according to the invention, a specific winding tap (12-1 to 12-30) of a transformer (12) is activated as a function of a setpoint / actual value comparison that has been carried out. The actual value and the target value are fed to a microprocessor (6, 7, 8) in digital form. Depending on the result of the target / actual value comparison, the microprocessor takes from a read-only memory (9) assigned to it information that corresponds to a specific control value for controlling a specific winding tap. A zero crossing detector (13) determines the zero crossings of the load current. Each time after a zero crossing is determined, the control value is determined by the microprocessor. After the next zero crossing has been determined, an electronic switch (15-1 to 15-30) assigned to the specific winding tap is ignited after the previously ignited electronic switch assigned to the previously activated winding tap has been blocked.

Description

The present invention relates to a circuit arrangement for regulating one of a transformer output alternating voltage according to the preamble of claim 1.

In a circuit arrangement known from DE-OS 29 36 010 for regulating a voltage stabilizer, the target / actual comparison is carried out by a comparator circuit. If the target value is greater than the actual value, a binary up / down counter is incremented on the other hand, if the target value is less than the actual value, the binary up / down counter is decremented.A decoder is used to control and ignite one of 15 triacs, depending on the current count. Each triac is between a secondary-side voltage tap of the transformer of the voltage stabilizer and the load arranged in the secondary circuit is switched. A pulse generator with a clock frequency of 100 Hz is provided for controlling the decoder and clocking the up / down counter, so that a triac is ignited every 100 msec. A major disadvantage of such a circuit is that the manipulated variable can only be changed by one step from half-wave to half-wave. This means that the control speed is limited. Another disadvantage of the known solution is that when the _| Actual value by rectifying the transformed load voltage, large dead and delay times]

occur which further limit the control speed. There is also another disadvantage of such a known circuit arrangement that the control of the transistors always takes place when the voltage is zero because there is no phase shift

so exercise is taken into account. It follows that with a | Phase shift the control can be shifted by 90 °. A maximum ^ Interference levels of around 130-14OdB and high frequencies! Disruptions in the network result. Since the ignition of the individual triacs are not synchronized with the zero crossing of the load current, there is a further one The disadvantage of the known solution is the possibility that two turns are briefly connected to the load can be. The resulting turn j?

circuit can lead to the destruction of the stabilizer i if it is not dimensioned for the existing short-circuit currents \ me

DE-AS 23 08 319 is an electronic one! Mains voltage stabilizer known, in which ir

6 ¹ S depending on the size of the mains voltage ar a power transformer in various Höh "\ taps angesteuen via electronic switches. Dr.;, An analog / digital converter is provided

hen, which generates a digital signal from the mains voltage. This signal is used to control a certain tap via a step switch. A disadvantage of such a stabilizer is that that a relatively large, electronic effort is required. For example, must for every possible Signal of the analog / digital converter in the step switch a fixed wiring or / 'compare be provided. But this also means that the design of such a tap changer in Depending on the number of taps present and the selected voltage range is extremely complicated.

The object of the present invention is to provide a circuit arrangement for regulating a Specify alternating voltage that can be output by a transformer, which has a high control speed and which is comparatively simple in structure

This object is achieved by the features characterized in claim 1. . A major advantage d'jr present invention consists in the fact that in addition to the high control speed achieved, the formation of winding shorts that are harmful to the Schakungsan-, order, as in the mentioned DE-OS 29 36010 can occur, s': her is avoided

Advantageously, in the present invention, the formation of shorted turns can also occur at a phase shifted capacitive and inductive load can be avoided.

Another major advantage of the present invention is that compared to from the 'DE-AS 23 08 319 known solution much less Circuit effort is required

An advantage of the invention can also be seen in the fact that when using a hybrid technology for the electronic switches, i. e. so in one application a large number of such switches on one chip, the wiring is much easier because the Switches are integrated on a ceramic support

Another advantage of the invention is that the switchover takes place in such a way that, after a setpoint / actual value comparison, that winding tap is automatically activated at the next zero crossing is controlled, which generates the required, correct voltage value at the load Switching does not therefore take place, as in the aforementioned DE-OS 29 36 010, via intermediate stages or intermediate values.

In the following the invention and its configuration in connection with the figures explained in more detail. It shows

Q ^: g. 1 shows the block diagram of the circuit arrangement according to the invention;

F i g. 2 the structure of an output stage;

Fig. I a representation to explain the Regsllaufes.und

4 is a block diagram to illustrate the Ver & chaitung of the Soü-Wert-Schaiiung and the A / D converter connected downstream of the actual value circuit, the microprocessor, the read-only memory, which is used for the control program contains the input / output units and other circuit elements.

In FIG. 1 is the transformer to be regulated with 12 Preferably, this transformer 12 is an autotransformer which a number of winding taps on the output side For example, the transformer 12 on the output side thirty winding taps 12-1 to 12-30. Each of these winding taps 12-1 to 12-30 is with an electronic switch 15-1 bis <) 15-30 connected, the line path between the respective winding tapping 12-1 to 12-30 and a load 14 interrupts or produces In the electroni see switches 15-1 to 15-30 are preferably thyristors, their control electrodes

κι zu- regulation of the load 14 applied The output voltage of the transformer 12 can be controlled by an ignition device 11.

An actual value circuit is used to control the control electrodes by the ignition device 11

ι j 2 the actual value of the voltage applied to the load 14 determined This determined value is applied to an input 41 of an A / D converter 4 desired 'Joll value to another input 31 Another A / D converter 3 applied The digitized values of the setpoint and the actual value are each at predetermined times via a data bus 16 to a central processor unit 6 one Microprocessor 6 to 9 supplied The function of the Microprocessor 6 through 9 will be related later with the Fig.4 explained in more detail about the Data bus 16 to the microprocessor 6 to 9 supplied digital values are in the central processing unit 6 is stored via an address bus 17 through

jo the central processor unit 6 a read-only memory 9, which is preferably an EPROM memory addressed The command addressed thereby, which contains the information about the winding tap to be controlled 12-1 to 12-30, is from the fixed value memory 9 transferred to the central processor unit 6 via the data bus 16 by means of suitable control signals from the decoder 5 controlled by the central processor unit 6, one of two input / output units 7, 8 is activated, the calculated, digital Supplies manipulated variable to an output stage 10 serving for control, via which further described below in connection with the ignition device If the control of the respective Thyristor depending on the calculated

Control value takes place

'Through a current zero crossing detector 13 wet <t <; n via a leading to the central processor unit 6 Line 131 of the power section and the microprocessor 6 to 9 are synchronized

The timely output of the ignition signals to the thyristors is accomplished by the two parallel input / output units 7 and 8 of the microprocessor 6 to 9. It is shown in FIG. 2 each output (A 0 to A 7 and BO to Bl or B 1 to BT) of the two Input S '/ output units 7, 8 each via one Power drivers of a control stage 10 (FIG. 1) or 44 to 47 (FIG. 2) and an amplifier module 48 to 51 are connected to the ignition stage 11 (FIG. 1). For controlling the power drivers of the Control stage 44 to 47, for example, the output BO of one input / output unit 7 is used. By using the control stage 44 to 47, it is advantageously possible to get the information for the ignition of the next thyristor already before the next current zero crossing to the outputs of the two input S '/ output units 7, 8, since the individual drivers of the control stage 44 to 47 after output of the

previous Ziindimpufses with a predetermined ignition pulse duration of about 5 to 7 ms have assumed a high-resistance state again. This has the advantage, as will be explained in more detail below, that after the current zero crossing has been recognized, the interrupt service routine is operated directly with the control by connecting line B 0 of the two input A output units 7 and 8 to » low «is pulled. If, on the other hand, the program part for loading the output register were processed between the detection of the current zero crossing and the output of the ignition signal, this software delay would result in a larger phase control of the load voltage. The delay time from the detection of the current zero crossing to the switching on of a thyristor is about 100 us. The control angle is therefore 1.8 °.

As can be seen from FIG. 2, with a control range of 180 V to 250 V, the outputs A 0 to A 7 and B 1 to B 7 of the one input / output unit 7 and the outputs Λ 0 to Λ 7 and BO to B 7 of the other input / output unit 8 distributed over the thirty outputs of amplifier modules 48 to 52. The first output AO of one input / output unit 7 corresponds to the minimum voltage. Each subsequent output of the two input / output units 7 and 8 corresponds to an intermediate value. The last output B7 of the other input / output unit 8 corresponds to the maximum voltage.

In the ignition device 11, a thyristor is controlled by one from the network galvanically separated module, the input of which with 'your output of the amplifier module 48 to 52 is connected and its output to the control electrode of the electronic switch 15-1 to 15-30 connected is

In essence, the present invention is based on that, as follows in connection with the F i g. 3a to 3c is explained in more detail, after the detection of a zero crossing from the determined The actual value and the determined target value e-follows soft thyristor soii to be ignited. Included the information contained in the read-only memory 9 is used for the calculation However, the thyristor only takes place after the next zero crossing following the zero crossing was determined. This avoids voltage jumps such as would occur when an ignition occurs of a thyristor take place during a half-wave would. More precisely, the microprocessor calculates 6 to 9 during a half-wave from the actual and Setpoint value and from the information of the read-only memory 9 that is available to him, the one to be ignited Thyristor or the winding tap to be switched on l'2-ί to 12-30, keeps the calculated result until ready for the next zero point and ensures that the new Thyristor is ignited at zero crossing. This then takes place during the following half-wave next calculation.

This process is described in connection with FIGS. 3a to 3c explained in more detail below. It is assumed that a half-cycle begins at the point in time / "(FIG. 3a) and one of the thyristors is triggered on the basis of the results calculated during the previous half-cycle. This thyristor is triggered by the fact that after the current zero crossing has been detected at time t " (FIG. 3a), the current zero-crossing detector 13 generates, for example, a" low "pulse (FIG. 3b) . An input 61 ( FIG. 4: JNT) of the central processor unit 6 is controlled by this pulse. Then, by activating the interrupt service routine JSR, the drivers of the control stage 44 to 47 (FIG. 2) are controlled the outputs of the two input / output units 7

ίο and 8 pending information forwarded what the Ignition of a thyristor leads After the content of the Ε register has become zero, the Reading in the actual and target value and the calculation, which thyristor is to be ignited next

ts (Fig.3c). The Ε register is used as a counter to take into account the delay time of the actual value provision. After the manipulated variable has been changed, the value 10 is preferably entered in the Ε register used as a counter. If, when the Ε register is requested to output the ignition pulse, the content is greater than zero, a new manipulated variable is calculated and the content of the E register is decremented is switched to ensure that the DC voltage of the actual value, which is proportional to the rms value of the load voltage, has settled
In the following, as shown in FIG. 3c it can be seen a holding pattern for realizing the firing pulse duration performed Subsequently, the driver of the Aiifsteuerungsstufe 44 to 47 back into the

. high-resistance state which switches off the ignition. Thereupon the information for the output of the next ignition pulse is transferred to the two input / output units 7 and 8. The following "Halt" command lets the central processor unit 6 execute an unlimited sequence of idle commands until the current crosses zero The "Iow" signal generated at time 7 " _{n +} i (FIGS. 3a, 3b) activates the interrupt service routine (ISR) again and initiates the ignition of the selected Thyrisiüfs

In connection with the F i g. 4, the operation of the circuit arrangement according to the invention is explained in detail, as this has already been carried out in the following, is a current zero passage through the current zero crossing detector 13 to the input 61 of the Zentralpro zes sor unit 6des Mikroprozessors6 to 9 a signal INT applied in the detection of the s has the consequence that a signal is applied to the two input / output units 7 and 8 and to the decoder 5 via the output 62 ( FIG. 4: JOR). By switching on the two input / output units 7 and 8, the manipulated variable currently applied to them is given to the output stage. The read-only memory 9 is then switched on via the logic 91 through the signals (WD) and (MREQ) through a signal “low” at its input CS

ω the addressed byte via the data bus 17 to Central processor unit 6 transferred.

The output of the manipulated variable and the reading out of the analog values are carried out by the commands »OUT « and »IN«, which activate an IORQ line.

The address bits A 2 and A 3 (lines 53, 54) are used to distinguish with the decoder 5 whether an input CE is activated (lines 51, 52) or whether one of the

two A / D converters 3, 4 are to be addressed (line 55).

The address bit A 0 is used to distinguish between the two input / output units 7 and 8 (line 92). The state of the address bit Ai on a line 93 indicates whether a control word or data word is output to a parallel module.

The two A / D converters 3, 4 work according to the level encryption principle ^ A conversion process begins when an input CS via the line 55 is activated. During the conversion the Äl / SV output of the converter becomes active.

The SSI / SK-outputs of both transducers are pft so Shortc each other by a further logic 42, that when an incipient transformation of the WAIT EMG & the central processor unit 6 ng via line 43 to the state "low" is drawn. The central processor unit 6 then executes WAIT cycles until the ÄLiSy input is pulled back to the “high” state , which ends the conversion, the WAIT input assumes the “high” state and the data transfer from the A / D converter to the central processor unit 6 via the data bus 16 is initiated.

For this purpose 4 sheets of drawings

Claims (5)

Patent claims: 1. Circuit arrangement for regulating an alternating voltage that can be emitted by a transformer (i2) with an actual value circuit (2) serving to determine the current flowing through a load (14), with a setpoint value circuit (1) for setting the desired target value of the voltage applied to the load (14), with the actual value circuit (2) and the target value circuit (1) each downstream analog-digital converter (4, 3), with a current - Zero crossing detector (13), and with a comparison circuit, through whose output signal via a control circuit (10, 11) containing an ignition device (11) and an associated electronic switch (15-1 to 15-30) one of the winding taps (12-1 ' s 12-30) of the transformer (12) is controllable, characterized in that a microprocessor (6 to 9) consists of a central processor unit (6), at least one input / output unit ^; (7, 8), and a read-only memory (9) for storing control value information for selecting one of the electronic switches (15-1 to 15-30) is provided so that the read-only memory (9) stores the result of the Unit (6) performed setpoint / actual value comparison, assigned control value information on request of the central processor unit (6) to the outputs (AO to A 7, BO to BT) of the input / output unit (7,8) provides that the control circuit (10, 11) which can be controlled by the microprocessor (6 to 9) also has a control stage (10) each with between an output (A 0 to AT, BO to BT) of the input / output unit (7, 8) and one of the electronic switches (15-1 to 15-30) contains switched drivers, and that the drivers can be controlled by the central processor unit (6) when the current crosses zero in such a way that the outputs (A 0 to A 7, BO to Bl) of the input / output unit (7, 8) after the previous current zero crossing e r determined and now pending control value information can be forwarded after opening the previously ignited shutter (15-1 to 15-30) 2. Circuit arrangement according to claim 1, characterized in that a logic (91) is provided through which to turn on the read-only memory (9) with simultaneous output of signals (RD) and (MREQ) from the central processor unit (6) the inputs of the logic (91) to an input (t3?) of the read-only memory (9) a switch-on signal is supplied from the output of the logic (91). 3. Circuit arrangement according to claim 1 or 2, characterized in that the determination of the actual value in the analog-to-digital converter (4) and the determination of the desired value in the analog-to-digital converter (3) can be carried out that for initiation of a conversion process whose inputs (CS) can be activated and that the converter signals present during a conversion process from their outputs (BUSY) through a further logic (42) whose output is connected to an input (WAlT) of the central processor unit (6) , are linkable. 4. Circuit arrangement according to one of claims 1 to 3, characterized in that a Decoder (5) is provided, which depends on I information flowing between the central processing unit (6) and the read-only memory (9) switches both analog-to-digital converters (4 and 3) on and off. 5. Circuit arrangement according to claim 4, characterized in that the decoder (5) is dependent on j speed of between the central processing unit (6) | and information flowing to the read-only memory (9) functions selectively controls the input / output unit (7,8)