DE3202945A1 - Process and arrangement for generating data pulses and, if appropriate, clock-window pulses for a separator circuit for separating the data pulses from accompanying pulses when reading from magnetic-tape or disc storage devices, in particular from floppy-disc storage devices - Google Patents

Abstract

All the read pulses (E-DAT) of the storage device are regenerated (A-DAT) and arranged in a timing code formed by derived time control signals (T0 to T3) and are passed onto evaluation after a delay. The time control signals (T0 to T3) control the position of the associated window pulse (DF or TF) by changing the counting cycle of a window clock counter (Z-FB), so that a predetermined minimum interval is always maintained between the leading edge of each regenerated data pulse and the leading or trailing edge of the accompanying window pulse, which expands the tolerance range of the evaluation. Additional correction dependent on continuously performed speed measurements (G-DAT) expands the tolerance range of the evaluation, so that overall there is a greater error immunity even under extreme boundary conditions, for example in MFM coding. An additional correction signal (KOR), derived from the speed measurement, reduces the extent of the correction-induced phase shifts in the case of relatively great intervals (for example 4TF) of the read pulses if the latter can follow one another at different intervals (for example 2TF, 3TF, 4TF). <IMAGE>

Description

Method and arrangement for generating data and

if necessary clock window pulses for a separator circuit for Separation of the data pulses from accompanying pulses when reading from magnetic tape or disk storage, especially from floppy disks.

The invention relates to a method and an arrangement for generating of data and possibly clock window pulses for a separator circuit for Separation of the data pulses from accompanying pulses when reading from magnetic tape or disk storage, in particular from floppy disk memories, using a pulse generator, a free-running counter that counts the clock pulses supplied by the pulse generator predetermined clock period successively the length of the data and possibly Cycle window by switching a flip-flop when reaching the end of the counter determined and using a control circuit for adjusting the respective Window center on the data pulse by shifting the relative window position as a result of correction of the counter reading each time a data pulse arrives depending on the relative position of the data pulses in the associated window.

When reading data from a magnetic memory, the data pulses appear alongside additional read pulses as a result of additionally provided clock pulses or of additional river changes. Therefore, the data pulses are clearly different from the rest To be able to differentiate between reading pulses are so-called data window pulses generated, which control the evaluation of the data pulses. For several known reasons - Speed fluctuations of the storage system, physically caused phase jumps (peak-shift) - it is necessary to keep the data window pulses constantly with the data pulses to synchronize so that they do not fall apart in such a way that an evaluation the data pulse is no longer possible.

In this context, digital solutions are already available for Magnetic tape storage known, e.g. DE-OS 20 13 880 and DE-AS 22 21 455, in which using a free-running counter with the frequency of the data pulses coordinated counting volume and corresponding counting frequency, its start and end value is continuously changed due to the determined phase difference, in each case at An evaluation pulse is emitted by the counter when the specified end value is reached will.

Other solutions that relate in particular to floppy disk storage and the two possible recording methods in FM and MFM coding carry, are the essay "Encoding / Decoding Techniques Double Floppy Disc Capacity" -, Computer Design, February 1980, pages 127 to 135 can be found a free-running counter, based on an initial value that can be changed by counting pulses incrementally advanced and alternately each time the counter has reached its end position switched from the data window to the clock window and vice versa, whereby by change of the respective counter start value depending on the respective position of the data pulses the center of the window is readjusted in relation to the expected data pulse will - page 132, section "Data- Separation ".

The previous digital solutions do not achieve the resolution of comparable analog solutions. Your error rate is therefore extreme because of the Boundary conditions, especially with MFM coding, are much greater. on the other hand the usual analog PLL circuits (phase lock loop) are much more complex and require an individual adjustment.

The object of the invention is therefore to find a solution that is digital works, but still does justice to the set tasks and can be used universally is.

This task is carried out with respect to the method mentioned at the beginning the features mentioned in the characterizing part of claim 1 solved.

After that, in deviation from the known solutions, all incoming Read pulses regenerated synchronously with the clock pulses for the counter and not immediately, but forwarded for evaluation after a delay. This makes it easy to that in connection with the generated timing signals the position of the read pulse in the window still evaluated in the associated window, the window corrected accordingly and a clear assignment between reading pulse and window in compliance with predetermined minimum distances to the flanks of the window can be made. As a result, almost the entire window width can be used for the evaluation.

The claims are based on this solution principle 2 to 8 refer to further developments of the invention. These consist, among other things, of an improvement the control behavior through additional measurement of the speed of the storage system based on the memory clock pulses of recorded synchronization fields, by correcting the counter reading from the determined speed range is dependent, and in the additional derivation of a correction signal for regulation the phase in the case of larger speed deviations, if larger distances between the read pulses occur which are caused by the coding.

Other developments relate to the additional use the window clock counter to generate the write pulses and to derive a additional error signal when exceeding or falling below the permissible limit speeds of the storage system, as well as the switchability of the clock period of the basic clock, depending on the possible different operating modes. In addition, concern claims 9 to 14 an arrangement for performing the method according to the invention.

Details of the invention are given below with reference to one in the drawing illustrated embodiment explained in more detail. In detail: FIG. 1A the circuit diagram of an arrangement according to the invention, FIG. 1B, FIG. 2 shows a timing diagram to explain the arrangement according to FIG. 1A, FIG. 3A time diagrams for explanation of the correction and signal, FIG. 3B, FIG. 4A shows a time diagram for deriving the self and FIG. 4B, limit values resulting in changes in the speed of the storage system, FIG 5 a control curve for the counter correction to compensate for phase fluctuations, FIG. 6 shows a combined correction table and FIG. 7 shows a block diagram for the correction network the arrangement according to FIG 1A.

The circuit arrangement shown in FIG. 1A and FIG. 1B continues together from the basic circuit shown in FIG. 1A and from that shown in FIG. 1B Additional circuit for performing the speed measurement.

The core of the basic circuit according to FIG. 1A is, as is also the case with the known ones Solutions, the window clock counter Z-FB, which is triggered by clock pulses T of a switching device US is incremented step by step and cyclically.

This switching device US is from the basic clock pulses IG-T a pulse generator, not shown, and consists essentially of a switchable frequency divider, which depends on the operating mode signal MODE, e.g. to differentiate between the two coding options FM and MFM for floppy disk memories, delivers the required clock pulses T with the desired clock period.

With the outputs of the window clock counter Z-FB is a register REG for the intermediate storage of the counter reading Zalt required for the counter correction coupled that via its outputs and a correction network K-NET with the charging inputs of the window clock counter b Z-FB is connected, so that from the moment Counter reading Zalt a corrected counter reading Zneu is determined and entered in the window clock counter Z-FB can be entered.

At the counter output D of the window clock counter Z-FB is a trailing edge controlled Flip-flop FF1 connected, which is alternately set and reset and thus supplies the required window pulses DF / TF for the data and clock windows. the Duration TF, e.g. 1 Fs with MFM coding, this window pulse is activated when the Counter Z-FB by the product of the number of counting levels (e.g. 16) and the duration the clock period (e.g. 62.5 ns) of the clock T is determined. By intervening in the counting cycle the duration of the window pulses can thus be shortened or lengthened.

This arrangement described so far is made possible by the shift register S-REG controlled in conjunction with the upstream SY-FF synchronizing flip-flop.

The SY-FF flip-flop takes over the read pulses supplied by the memory E-DAT and loads the input stage A of the shift register S-REG with the leading edge of the following clock pulse T if it is a read operation and therefore the signal SYN, which characterizes the write operation, is equal to zero. The shift register S-REG consists of a total of four stages A to D, each one of the timing signals TO to T3 and the regenerated read pulses in synchronism with the last time control signal T3 Deliver A-DAT for further evaluation, with the timing signal T1 the Input trigger stage SY-FF reset, the window cycle counter Z-FB stopped and the register REG is loaded with the count reached Zalt. Farther the time control signal T3 then becomes the one supplied by the K-NET correction network and if necessary corrected counter reading Znew is loaded into the window clock counter Z-FB and counting continues.

So it is initially only in the presence of a read pulse E-DAT on Input of the trigger stage SY-FF intervened in the counting process of the window clock counter Z-FB, Otherwise, however, the counter runs freely and supplies window pulses DF / TF more constantly Duration. This also applies to the write process when the signal SYN = 1, so that the counter can also be used to derive write pulses S-T by using the trailing edges of the output signal of the counting stage D of the window clock counter Z-FB a monostable Trigger flip-flop MF1 to generate the write pulses that are transmitted by the signal SYN released gates U are forwarded.

2 shows the associated pulse time diagram. Depending on the clock pulses T will be according to the present.

of a read pulse E-DAT taken over into the flip-flop SY-FF in succession the timing signals TO to T3 generated, the two clock periods of the clock T and overlap halfway. Synchronous with the timing signal T3 the output pulse A-DAT is also generated, which therefore has a certain duration and is delayed compared to the input pulse E-DAT. In the example chosen this delay is between three and four clock periods. Is accordingly each time, because of the temporary counting stop, also the counter reading of the window clock counter Z-FB to change so that the associated window pulse DF resp.

TF is retained in the desired relation to the output pulse A-DAT.

Like the counter readings of the window clock counter plotted in line Z-FB Z-FB show, the counter will, for example, after reaching the counter reading 7 with the timing signal T1 stopped. With the following leading edge of the clock T, so at the beginning of the timing signal T2, is the instantaneous Counter reading Zalt transferred to register REG, increased by four clock periods as new counter reading Zneu is loaded again into the window clock counter ZFB and with the first Leading edge of the clock pulses T after the end of the time control signal T3 the counting process continued again.

Despite this change in the counter reading by increasing the constant The duration of the respective window pulse is not a value of four clock steps changed how the comparison of the lines Z-FB and DF / TF with reference to the second data window shown DF shows. On the other hand, it is guaranteed that that the leading edge of each regenerated pulse A-DAT is due to the synchronization with the pulses T a fixed minimum distance to the leading or trailing edge of the respective associated window pulse DF or TF.

3St the last counter reading before the counter stop Zalt = O, then the Counting continued with counter reading Znew = 4. Minus the read pulse width of two clock periods there is still a gap of two clock periods to the front edge of the window. If the last counter reading Zalt is in the range of the counter values 12 and 15, the count is with a count Znew in the range of the count values 0 to 3 continued, and since the reloading always starts with the leading edge of the following Clock pulse T occurs, lies between the leading edge of the read pulse and A-DAT the trailing edge of the associated window pulse always a distance of one clock period.

The additional circuit part according to FIG 1B is used to additional Determination of the storage speed.

It is assumed that before each address and data field of the memory, a synchronization field is provided, for example Provides 48 read pulses with constant spacing. Therefore, if the clock pulses T are counted between the individual read pulses of the synchronization field or between the first and a nth reading pulse, then it can be determined in a simple manner on the basis of the Determine the counting result, whether the permissible speed has been observed or not, and derive a correction for the long-term fluctuations from this.

For this purpose, the arrangement according to FIG IB has two counters, from which the first Z-SF reads the synchronizing field, e.g. corresponding to the counting capacity from 0 to 15, and the second counter Z-G counts the clock pulses T, For example, 2 ~ 16 clock pulses T per read signal period for a total of 15 Reading pulse periods 480 counting pulses and taking into account the maximum permissible Speed change of e.g. + 6% a valid counting range between approx.

451 and 509 counting pulses for the second counter Z-G results, so that a total of nine counting levels A to I are required for binary counting. At the end In a measuring phase, the register REG-G connected downstream takes over the counter reading as a measurement result which is converted into suitable correction data K-DAT by means of the decoder DEC2 is converted. At the same time, it can be checked whether the permissible speed is complied with by the storage system or not. In the latter case it will be Error signal G-FEHL generated.

This means that with read pulses with different distances, only the read pulses with the same spacing as the synchronization field usually delivers, are evaluated, is a at the input of the correction circuit Counter Z-F provided with a downstream decoder DEC1, which is used for the correct distance range, e.g. the second window pulse DF / TF after a window pulse with occurring Read pulse A-DAT, an enable signal F2 generated and the AND gate U for the regenerated Read pulse A-DAT enables.

The impulses to be counted derived in this way are not immediate the counter Z-SF fed, but it is first with the trailing edge of the first Pulse of each sequence the flip-flop FF3 is set, which then the downstream AND gate U3 controls for the subsequent pulses, so that in each case the first Pulse interval of a sequence is suppressed. In this way it is avoided that System-related shifts in the read pulses occurring at the beginning of a pulse train affect the speed measurement. The same may apply to that last read pulse interval of a measurement sequence. Therefore, the second counter Z-G The counting result determined is only then declared valid and transferred to the REG-G register, even if the next read pulse following the measurement sequence meets the specified distance condition Fulfills.

The end signal derived from the end of counting of the first counter Z-SF, the corresponds to the transfer signal C01, therefore the flip-flop FF4 sets its output signal both counters Z-SF and Z-G stops, and the AND gate U4 only starts with the next Pulse at the output of gate U3 loaded the register REG-G.

The resetting of both counters Z-SF and Z-G is done by the multivibrator FF2 controlled during a Write process - signal SYN = 1 - is constantly set and when reading with the first at the output of gate U3 occurring pulse is reset and both counters are enabled. This tilting stage FF2 is also set via the D input if the distance condition for the reading pulse to be counted is not fulfilled, which is monitored by the AND gate U1 will. In addition, as indicated by the dashed line OR gate 02, be set at the end of each measurement with the signal at the output of gate U4, to continuously repeat the speed measurement even during a synchronous field to be able to do what otherwise because of the failure to reset the flip-flop FF2 would be possible because the flip-flop FF4 is set and thus the counters Z-SF and Z-G im The hold state remained until the gate U1 was opened for the first time.

To the function of the still shown AND gate U5 and the two To better understand flip-flops FF5 and FF6 for generating the correction signal KOR, reference is first made to the pulse time diagram of FIG. 3A: This shows in the first line E-DAT a sequence of read pulses corresponding to the known NFM coding without taking into account the regeneration and delay according to the Invention and in the second line the window pulses DF / TF, the window pulses DF is assigned to the data pulses and the window pulses TF to the memory clock pulses C. are. The data pulses with the binary value "1" on the one hand and the memory clock pulses C on the other hand follow each other with the same distance 2TF, which is the window pulse period from 2 corresponds to. Data pulses with the binary value "0" do not have a read pulse result and the memory clock pulses C occur only between data pulses with the binary value "O". This leads to the fact that the distance between two read pulses, as shown, can fluctuate arbitrarily in an address or data field, since three different distances, namely 2TF, 3TF. or 4TF, are possible. The distance from 3TF results from the data sequences "1-0-0 or 0-0-1" and the distance 4TF for the data sequence "1 - 0 - 1.

Since nln the phase of the window with each read pulse, regardless of whether Data or memory clock pulse, is readjusted and, on the other hand, cannot be foreseen is the distance at which the next read pulse follows depends on the determined speed is only readjusted under the assumption that the The next read pulse follows at an interval of 2TF. Only when this expected reading pulse does not appear and does not appear even at a distance of 3TF, because there is also a distance of 4TF is possible, a correction signal KOR is triggered after a period of 3TF and thus additionally regulated.

In this way, the long-term fluctuations are avoided with every readjustment triggered phase jumps, the respective integer multiples of the clock period, e.g.

T = l / l6TF, corresponding, reduced and the long-term regulation more effective, because for errors caused for other reasons, larger tolerances for the evaluation can be granted.

In FIG. 3A this is indicated, for example, by the time limit GO to G3. The time limit GO is determined by the incoming data pulse with the binary value ~ 1 "is marked. The subsequent time limit G1 corresponds to the interval 2TF to which in the majority of cases the next reading pulse can be expected. The further Distance from TF following time limit G2 mar- kiert the possible Time for triggering the correction signal KOR if there has been no read pulse by then has arrived. The subsequent time limit G3 becomes with the incoming read pulse then back to the start time limit GO 'with a new sequence GO', G1 ', G2' etc.

These time limits are shown continuously in FIG. 1B by the output signals CO and D of the window clock counter Z-FB of FIG 1A marked, each with When the final count is reached, the signal CO triggered the limits of the window pulses DF or TF and the leading edges of the output signal of the counting stage D the center of the window mark if the meter is then free running. Instead of the signal CO could just as well the trailing edges of signal D can also be used.

The signal CO clocks the counter Z-F of the input circuit of FIG 13, which is set to "O" with each incoming read pulse A-DAT and then through Counting the subsequent pulses of the signal CO determines the respective window. As soon as the signal F3 appears for the third subsequent window, the gate becomes U5 prepared, which then with the window center signal D of the window clock counter Z-FB 1A is turned on and the flip-flop FF5 sets which the correction signal KOR delivers. The subsequently set flip-flop FF6 sets the flip-flop FF5 and the input counter Z-F back again, so that the flip-flop FF6 with the leading edge of the subsequent clock pulse T is reset again.

The correction signal KOR is always at the fixed point in time the center of the window is effective, as FIG. 3B shows, since all the decisive flip-flops and counters of the Leading edges of the clock pulses T are controlled. The tilting stage FF5 for the correction signal KOR is therefore always at the beginning of the ninth counting step set, so that the new counter reading Zneu at the beginning of the tenth counting step in the window clock counter Z-FB (FIG 1A) and can continue to be counted normally from the eleventh counting step of the cycle. Accordingly, for window pulses that are not to be corrected, as shown, Znew = 10. In the other case, Znew = 11 resp.

Zneu = 9, depending on whether the additional correction leads to a shortening or should lead to an extension of the current window pulse. The meter reading Zalt is consequently not taken into account in this correction, since there is no read pulse A-DAT is available.

Using the timing diagram of FIG. 4, the should now emerge from the permissible speed change, e.g.

+ 6%, the resulting correction values can be derived: This shows Pulse diagram in the first line E-DAT a sequence of read pulses E-DAT with the Data resp.

Storage clock pulses D and C, again without consideration the regeneration and the delay according to the invention, as well as in the second Line the window pulses DF / TF with the consecutive counts of the window clock counter Z-FB (FIG 1A). On the first data pulse D at the time limit GO, either after a data pulse D after a distance of 2T or after a distance of 3TF a memory clock pulse C or a next data pulse only after an interval of 4TF D follow, with dashed pulses indicating the limit positions for the maximum permissible Speed deviation of + 6% and - 6% are specified. The greater the distance of the successive read pulses, the greater the possible shift in position at the time limits G1 or G2 or GD.

After a distance of 2TF, this results, as indicated, compared to the The counter reading 8 characterizing the middle of the window shows a deviation of +2 or - 2 clock periods T. These deviations grow at the distance 3TF to +3 or -3 clock periods and at Distance 4TF to +4 resp.

-4 clock periods. The resulting corrections FK + for too high and FK- for speeds that are too low are indicated in the next two lines and lead to the fact that the trailing edge of the respective window pulses DF and TF either moved forward or postponed.

The following three lines indicate a speed deviation of + 6% as an example, the course of the window pulses with read pulses at a distance indicated by 2TF, 3TF and 4TF. At the time limit GO is in any case initially assume that the next read pulse follows at an interval of 2TF and only one Corresponding correction made, namely change of the counter reading of the window clock counter Z-FB by +2 steps. This correction is repeated with read signals at a distance 2TF with each read pulse, i.e.

in the absence of other shifts in the read pulses, all Data window DF shortened in duration by two clock periods T, while the one in between lying clock window TF last unchanged long.

This is different with the distance from DTF. The reading pulses appear alternately with a data window DF and a clock window TF, the second correction by +2 in the limit area G2 is not sufficient, so that a greater deviation from Center counter reading results in 8 and an additional one Correction becomes necessary, which will be dealt with in the following. At the distance of 4TF, the correction signal KOR occurs at the time limit G2 and causes a early correction by +1, better by the greater distance up to the time limit G3 to be bridged so that a correction by t2 can subsequently be retained Based on the specified limits of + 6% and -6% speed deviations the resulting possible range of change can be divided and it can the relevant correction values for these speed sub-ranges are calculated are, however, only changes by integer multiples of clock periods are possible are. 6 shows a total of 16 speed ranges in the ordinate axis of the table G-BERO to F with the values for the middle of the window according to the counter readings 7 and 8 of the window clock counter Z-FB resulting correction values in the range between +2 and -2.

Except for the displacements caused by speed deviations of reading pulses in the associated window can also, as already mentioned, for various reasons, additional fluctuations in the read pulses occur and lead to shifts in the window.

Extremely wrong phase positions and only peak shifts should be used are weakly regulated. Regardless of the speed-dependent one already described Phase shifts in the window can therefore be corrected in a manner known per se Correct way by taking from the instantaneous position of the reading pulse in the window based on the counter reading corrected and thus a shift towards the center of the window is effected. 5 shows a corresponding control curve, where the coordinate axis FK the change in clock periods of the clocks T for the entire Window area with the sub-areas FBO to FB3. This control curve leads to the correction values given in FIG. 6 for the speed ranges G-BER5 to A. depending on the counts of the window clock counter Z-FB. In the case of greater speed deviations the correction values derived from the speed measurement are superimposed in the area of counter readings 7 and 8, so that e.g. for counter readings 0 and the speed ranges G-BERO to 2 in total the correction value +4 -2 = +2 results. The same applies to the other fields in the table according to FIG. 6.

In addition, those resulting from the correction signals are KOR Correction values for the individual speed ranges G-BERO to F are given. The fluctuations between the values -1 and 0 or 0 and +1 are due to the The fact that on the one hand only integer multiples of clock periods of the Clock T can be taken into account and on the other hand the window center two Counter readings, namely 7 and 8, includes.

The correction values given in the table according to FIG for the sake of clarity, not the result of the delay in the regenerated Read pulses A-DAT conditional shift ~ takes into account the total, as already explains, makes up four clock periods. The specified window-related correction values must therefore be increased by +4 in each case, so that overall changes between -2 and +10 result for the correction network K-NET in FIG. 1A, while for the through the correction signal KOR triggers the corrections -1 or O or +1 already mentioned Constant values 9 or A or B can be generated.

A correspondingly structured correction network K-NET is shown in FIG shown. In the selected exemplary embodiment, there are correction values for each Corresponding adding networks ADD "-2" to ADD ~ + 10 "are provided via the decoder DECA are released and the counter reading supplied with each correction Convert Zalt into the corresponding new counter reading Zneu. There is also a constant generator KON is provided, which is controlled via the DECB decoder, which generates the results G-DAT evaluates the speed measurement and for the respective applicable speed range G-BER, when the correction signal KOR is present, the selection signals for the required Constant supplies. Instead of the decoder and the adder networks, a Conversion table, e.g.

in the form of readable memory (ROM), which depends of the sizes Zalt, G # -DAT and KOR is addressable and in each so marked Storage section contains the corresponding output value Zneu stored.

Furthermore, the evaluation circuit for the result G-DAT could Speed measurement in FIG. 1B depending on the given numerical ratios be simplified. As already mentioned, the valid counting range of the counter is Z-G 451 to 509 clock pulses with a maximum permissible speed deviation of 696 with an average of 480 clock pulses.

In the case of binary counting with nine counting levels A to I of the counter ZG, the following counter readings result: G-ABW IHG 'FEDC' BA + 6% 1 1 1 0 0 0 0 O, 1 1 + 0% 1 1 1 1 0 0 0 1 0 0 -6% 1 1 1 1 1 1 1, 0 1 The comparison of the three counter readings shows that the 16 speed ranges G-BER 0 to F on which the table of FIG.

In addition, there is a speed error with certainty if one of the output signals of the three counting stages G, H and I deviates from the value ~ 1 ", which is monitored in a simple manner by a NAND gate can be that controls a register stage. The downstream register REG-G in FIG 1B would then only need to have five register levels, and on the separate Decoder DEC2 could be dispensed with.

Similarly, other circuit details of the The illustrated embodiment can be modified without thereby affecting the frame the underlying inventive concept is left.

Overall, the invention thus enables a very powerful and adaptable one Arrangement for generating the window pulses, which works digitally, in an integrated Circuit technology can be created and a large control range with low Has error rate.

Claims (14)

Claims method for generating data and possibly Clock window pulses (DF / TF) for a circuit to separate the data pulses from Accompanying pulses (E-DAT) when reading from magnetic tape or disk storage, in particular of floppy disks, using a pulse generator, a free-running one Counter (Z-FB), which by counting the clock pulses (T) supplied by the pulse generator predetermined clock period successively the length of the data and possibly Cycle window (DF / TF) by switching over a trigger stage (FF1) each time it is reached its final count determined, and using a control circuit for Adjustment of the respective window center to the data pulse by moving the relative window position as a result of correction of the counter reading after each arrival of a data pulse depending on the relative position of the data pulses in the associated Window that shows that all incoming read impulses (E-DAT) regenerated synchronously with the clock pulses (T) of the pulse generator and on a predetermined pulse width (e.g. two clock periods) that the regenerated Read pulses (A-DAT) delay the evaluation by a multiple of clock periods And that in connection with each regeneration of the read pulses Time control pulses (TO to T3) are generated, on the basis of which the current counter reading (Zalt) of the window clock counter (Z-FB) is determined and corrected, the corrected Count corresponding to the delay of the read pulses (A-DAT) by a specified one Number (e.g. 4) of clock periods increased and then as a new counter reading (Znew) in the window clock counter (Z-FB) is loaded so that between the leading edge of Data pulse and the edges of the data window pulse (DF) a minimum distance (e.g. of one clock period) is always guaranteed. 2. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that based on the regenerated read pulses (A-DAT) of the address and data fields the respective preceding synchronization fields of the memory the relative reading speed of the memory is continuously measured and that from the speed measurement Derived correction values (G-DAT) when correcting the counter reading of the window clock counter (Z-FB) must be taken into account. 3. The method according to claim 2, d a d u r c h g e -k e n n z e.i c h n e t, that in each case during a predetermined number of successive synchronizing pulses the clock pulses (T) of the pulse generator are counted. and from this the associated and up to Preferences of the result of the subsequent speed measurement valid speed range (G-BER) is determined, with the specified speed ranges (G-BER0 to G-BERF) depending on the relative position of the read pulses (A-DAT) in the window (DF / TF) different correction values are assigned. 4. The method according to claim 3, d a d u r c h g e -k e n n z e i c h n e t that the speed measurement is always carried out with the second incoming synchronization pulse is started and that the result of the speed measurement is only valid is explained, even if the reading pulse ending on the measurement is within a specified distance range (e.g. in the second window). 5. The method according to any one of claims 1 to 4, d a -d u r c h g e It is not indicated that to bridge three possible distances (e.g. 2 TF, 3TF or 4TF) between the read pulses in the absence of a read pulse up to to the window center (signal D) of the third window after the last read pulse accordingly the mean possible distance (3TF) a precautionary correction of the meter reading of the window clock counter (Z-F3) is triggered by a correction signal (KOR) that also dependent on the respective available result (G-DAT) of the speed measurement the counter reading, if necessary, by one counting unit in one direction or the other corrected. 6. The method according to any one of claims 1 to 5, d a -d u r c h g e it is not clear that the counter reading is corrected during a write operation (signal SYN = 1) of the window clock counter (Z-FB) is switched ineffective and this then as free-running The counter triggers write clock pulses (S-T) when it reaches its final reading. 7. The method according to claim 6, d a d u r c h g e -k e n n z e i c h n e t that the initiation of the write process from the result of the immediately preceding Speed measurement of the synchronizing device checked before the start of the writing process and address field is dependent and that at an impermissible speed of the memory system the writing process is blocked by an error signal (G-FEHL). 8. The method according to any one of claims 1 to 7, d a -d u r c h g e it is not shown that the basic clock (IG-T) supplied by the pulse generator is in his tact- period according to the G (and frequency of the Read impulses (E-DAT) and thus dependent on the specified operating mode (e.g. FM- or MFM coding) can be changed. 9. Arrangement for performing the method according to one of the claims 1 to 6, g e k e n n z e i c h -n e t through a four-stage, of clock pulses (T) of the pulse generator clocked shift register (S-REG) for generating the successive, gradually overlapping timing signals (TO to T3) and the regenerated Read pulse (A-DAT) synchronous with the last timing signal (T3) and by a clocked bistable multivibrator (SY-FF.), which is the input of the first stage (A) of the Shift register (S-REG) is connected upstream and the one supplied by the memory Read pulses (E-DAT) are set by clocking with the leading edge and with the second time control signal (T1) is reset again. 10. The arrangement according to claim 9, g e k e n n z e i c h -n e t through a register (REG) connected to the outputs of the window clock counter (Z-FB) for intermediate storage of the current meter reading (Zalt) at the beginning of the second time control signal (.T2) after previous blocking of the counter (Z-FB) with the first time control signal (T1) and by a to the outputs of this register (REG) connected correction network (K-NET), its outputs with the charging inputs of the counter (Z-FB) are connected and the correction counter readings generated in each case as new counter readings (Znew) with the last time control signal (T3) or with the Correction signal (KOR) is transferred to the counter (Z-FB). 11. Arrangement according to claim 10, d a d u r c h g e - k It is noted that the correction network (K-NET) consists of a series of adding networks (e.g. ADD "-2" to ADD fl + 10it), which correspond to that of the upstream register (REG) add a constant (e.g. "-2" to "+10") to the delivered counter reading (Zalt) and the result (G-DAT) of the speed measurement through a corresponding output and the count (Zalt) evaluating decoder (DECA) are released, and consists of a constant network (KON) that depends on the control outputs a second evaluating only the result (G-DAT) of the speed measurement Decoder (DECB) if the correction signal (KOR) is present one of three provides predetermined constant counter readings. 12. Arrangement according to one of claims 9 to 11, g e -characterized r by a control switching element (e.g. window counter Z-F with a downstream decoder DEC1) to determine the signals (F2 and F3) for the presence of the second or third window pulse (DF / TF) after a read pulse (A-DAT) by counting the one supplied by the window clock counter (Z-FB) after reaching the end counter Pulses (e.g. CO), by a second counter (Z-SF) to count the read pulses a synchronization field and by one controlled by the second counter (Z-SF) third counter (Z-G) for counting clock pulses (T) during the preset Running time of the second meter (Z-SF) with downstream register (REG-G) for intermediate storage of the determined result (G-DAT) of the speed measurement, whereby only successively occurring with the signal (F2) for the presence of the second window Read pulses (A-DAT) are counted, while if this condition is not met both counters (Z-SF and Z-G) are reset, and where a when a specified count is reached on the second counter (Z-SF) Control signal (Co1) stopping the two counters (Z-SF and Z-G) and taking over the counter reading contained in the third counter (Z-G) into the downstream register (REG-G). 13. The arrangement according to claim 12, d a d u r c h g e -k e n n z e i c h n e t, that to suppress the first of the derived from the synchronizing field Counting pulses for the second counter (Z-SF) are preceded by a flip-flop (FF3) which is clocked and set by the trailing edge of the derived counting pulses and its output together with the clock input with the inputs of an AND gate (U3) is connected, the output of which supplies the counting pulses actually to be counted, and that the release input (LD) for the acceptance of that contained in the third counter (Z-G) Counter reading in the downstream register (REG-G) an AND gate (U4) upstream is on whose one signal input the control signal that triggers the takeover acts and its second signal input with the output of the actual counting pulses for the second counter (Z-SF) supplying AND gate (U3) is connected. 14. The arrangement according to claim 12 or 13, ge k e n nzeichung by a flip-flop (FF5) clocked by the clock pulses (T) to generate the correction signal (KOR), whose set input is preceded by an AND gate (U5), which is the simultaneous Presence of the signals (F3 and D) for the third window pulse after a read pulse (A-DAT) and for the second half of each window impulse as the output signal (D) of the window clock counter (Z-FB), and also by a by the clock pulses (T) clocked subsequent flip-flop (FF6) to reset the controlling Flip-flop (FF5) and the control switching element (Z-F / DEC).