DE3018002A1 - Replay of digital data from disc system - using modified frequency modulation technique with ROM-based decoding system - Google Patents

Abstract

The replay of digital data from a disc storage system based upon a modified frequency modulated technique, uses r.o.m.s. to generate decoded digital values. The analogue outputs of the disc are digitised by a 'D' type flip-flop to generate a data stream to a shift register. The latters outputs are entered in a counter to define the number of bits of information in a serial transmission. Read only memory stages are accessed at specific intervals to provide data status signals. The conversion process is controlled by a clock generator to provide the decoded binary values.

Description

The present invention relates to a data retrieval

system according to the generic term of claim 1. Through the system in particular, clock and data information should be included in the magnetic layer written on a disk or floppy disk1 is also then uncovered again if the time sequence of the information received differs from the expected temporal sequence deviates.

The recording of higher density digital information on a magnetic storage medium is through the development of numerous coding schemes including phase and frequency coding have been favored. At increased Data processing security is also an emphasis on magnetic recording laid with increased packing density. For this purpose, binary information streams are used used that of a frequency modulation (FM) or a modified frequency modulation (MFM). The FM and MFM information streams represent an encoded Information that is commonly referred to as singly condensed and doubly condensed will.

In US-PS 3 108 261 an MFM recording system is described, which requires a considerable amount of circuitry.

Regarding the simply condensed FM coding, refer to the US-PS 4,034,348. The double compression MFM coding is in a publication by Control Data Corporation entitled MFM Double Density FDD System "Nov. 16 Described in 1976. There is also the insertion of an illegal "O" clock signal in the address mark field to form an address mark and it is on the Use of delay lines referenced to read the inscribed To facilitate information.

The read-back search systems generally include frequency-sensitive ones Devices such as delay lines, oscillators with variable Frequency (XT0), phase lock oscillators (PLO) and feedback loops for generating the timing blanking signals. Own the delay lines a limited accuracy that is unacceptable in newer data processing systems is. The VFO and PLO oscillators must be adjusted to the speed with which the information is received from a storage medium. If the set and adjusted frequency of the oscillators drifts or the system structure is changed, a new adjustment is necessary to prevent reading errors.

The accuracy of the VFO and PLO systems is further enhanced by the Occurrence of write splice points influenced in the information sequence an update of the data recording may be available on the storage medium. Furthermore, the delay lines and the VFO and PLO systems do not come with one Integrated circuit design compatible. Those recovery systems that the feedback loops use to generate the timing blanking pulses the most complex systems in the state of the art. Because of the effort involved, the application limited by feedback loops to FM retrieval systems.

Another example of a VFO system can be found in U.S. Patent No. 3,751,143 in which a device for locking an oscillator with variable Frequency described according to the speed of the incoming data pulse train is.

In U.S. Patent Application Serial No. 866,441, there is a logic system for converting MFM-coded information into an NRZ information sequence (NRZ = Non Return to Zero) describes the without delay lines, VFO oscillators, PLO oscillators or feedback loops works. Instead of this will "1" bits of the information sequence in sequence through an input shift register guided. The output signals of the input shift register are passed through a multiplexer sampled as a function of a control signal indicating the occurrence of clock bits in the MFM information sequence. As a result, timing blanking pulses for generated the operation of the retrieval system.

This system also requires a considerable number of integrated Circuit elements to read the digital MFM signals when retrieving the information to create.

This logic circuit becomes a significant number of integrated Circuit elements added to allow the MFM digital read signals to be retrieved to generate the information.

Based on this prior art, it is the task of the present one Invention of providing an improved data retrieval system, which is particularly useful in characterized by a reduced frequency of errors ~ if the memory unit received information with a changed compared to the normal speed Speed is read and the fewer components and thus an increased Reliability and lower cost. The solution to this problem succeeds according to the invention characterized in claim 1. Further advantageous refinements the invention can be found in the subclaims.

According to the invention, the information is a disk or floppy disk taken in the form of a serial bit sequence, the bit sequence clock and data bits includes. The information is in a modified frequency modulation mode MFM coded. A memory cell includes a clock bit position and a data bit position. Here the memory cell contains never both a clock bit and also a data bit with the binary value "1". If the memory cell has a data bit with has the binary value ~ 0 ", it has a clock bit with the binary value laO", if the previous memory cell has a data bit with the binary value ~ 1 ".

The data sequence is fed to a shift register. A predetermined one The output of the shift register is applied to a counter, causing the counter is enabled the number of clock pulses between successive Store information bits in the serial bit sequence. The clock pulse count is a measure of the time between successive bits. This count together with a signal that indicates whether the previous bit is a clock or data bit was, the address connections of a first programmable read-only memory PROM fed. The content of the selected PROM address memory location indicates whether one or two cells of the information were received and whether the information has the binary value "1" or "O".

The count 1, which is a measure of the time between consecutive Bits is fed to the address terminals of a second read-only memory PROM. Since the time between successive pulses is a multiple of an integer corresponds, the count indicates whether the received pulse is too early, in time or received too late.

The output signal of the second read-only memory PROM sets the counter to a predetermined value in advance when the bit is received in time. The output signal of the second read-only memory PROM also sets the counter im advance to a value greater than the predetermined value if the pulse is too late is received, and it sets the counter to a smaller than the predetermined one Value on1 if the impulse is received too early.

Since the output signal of the counter reaches the first read-only memory PROM addressed to determine whether the received pulse has the binary value "01" or "1" owns, is by presetting the counter to different amounts according to the output signal of the second read-only memory PROM the system in enables changes in the time sequence of the bit stream to be accounted for wear.

Means are also provided to indicate whether the first signal with the binary value "1" is a clock bit or a data bit. Funding is also provided to indicate whether the received data is encoded in blFM or FM mode.

For this purpose, the count output signals of the counter are the last Data signal and the mode signal, the address input terminals of a programmable Read-only memory PROM supplied. The identified address storage location stores Binary bits corresponding to the received data bits, whereby the clock information of the data information is separated. Show the binary bits stored in the PROM also shows the number of memory cells received during the E1FM mode, and they indicate whether the received data has a missing clock bit, which is on an address tag byte refers.

Based on one shown in the figures of the accompanying drawing Exemplary embodiment is explained in more detail below: Figure 1 is a block diagram of a typical system in accordance with the invention; Fig.2a the typical clock and data bit configuration in MFM and FM modes; Fig.2b the bit configuration for one address mark byte in MFM and FM mode; Fig.2c shows the variable timing the bits received in MFM mode; Figure 3 is a detailed logic program of a preferred # Embodiment; Fig. 4 is a timing diagram for the preferred embodiment; 5 shows the information stored in the PR0M address storage locations in the MFM mode; 6 further information stored in the PR0M address memory locations in the MFM mode; and FIG. 7 the information stored in the PROM memory locations for presetting the counter Figure 1 shows the structure of the ~ Honeywell Level 6 minicomputer a system " a memory 4.1 peripheral controller 6, a mass storage controller 10 and has a central unit 18, all connected to a system bus 2 are connected. A disk adapter 12 is attached to the mass storage controller 10 and a plurality of disk units 14 are connected.

FIG. 2a shows a typical one consisting of clock and data pulses Data sequence. The data sequence 20 represents an example of a frequency-modulated recording FM and the data sequence 22 represents an example of a modified-frequency-modulated Recording ItFM.

The solid lines show the actual course of the data sequence corresponding pulse train after the analog signals read by the read head of the plate are digitized. The dashed lines show the position in time of binary "O" bits and clock bits that are not recorded on the storage medium are.

FIG. 2b shows the data sequence of an address mark byte 24 in the MFM mode and the data sequence of an address mark byte 26 in the MFM mode when recorded.

The FM and MFM coding schemes as well as the coding of the address mark byte are in the IBM manufacturer's information for the double-sided diskette ~ GA21-9257-1 ", 2nd edition dated November 1977.

According to Figure 3, the flux changes according to clock pulses or data pulses on the surface of a recording medium by a reading head of the disk unit 14 sensed.

The analog output signal of the read head is digitized and the Plate adapter 12 supplied. Pulses corresponding to the data and clock bits are fed to the clock input of a D flip-flop 30, which when the 200ns pulse rises set when the input signal READOK-OO at connector S of the flip-flop 30 has the logic level flih. The output signal DATSTR + OO becomes the AND input terminal of a shift register 32 and the AND input terminal a shift register 38 via an OR gate 36 in the form of the output signal ALRTST + OO fed. The free-running clock signal 25MHZ + OO causes a Shifting the information entered. The output signal RTDX02 + 00 is used with next rise of the clock signal 25MHZ + 00 is set to the logic level "1" and this Signal resets flip-flop 30 via an inverter 54. The impulses are through the shift registers 32 and 38 by successive clock signals 25? lHZ + 00 postponed. If the output signal RDTXOF is set to the logic level "1", so this signal is fed through an inverter 56 to the connection G1 of the counters 58 and He is supplied with the logic level "O", whereby the counters 58 and 60 to a predetermined Count by means of the output signals RDPM01 + 00 to RDPM05 + 00 of the programmable Read-only memories PROM90 and 92 can be preset. Counters 58 and 60 give with successive clock pulses 25MHZ + 00 each time a new count is generated.

The next data or clock pulse transmitted via the DEVD.T + OO is received, sets the flip-flop 30 again, which the output signal DATSTR + OO to the zero position of the shift registers 32 and 38 when the clock signal rises 25MHZ + 00 applies. The output signal RDTX02 + 00 becomes the next time the clock signal rises 25MHZ + 00 set to logic level 1 and fed to the clock input of a register 63. This inputs the output of counters 58 and 60 into register 62, its output signals LTCH01 + 00 to LTCH08 + 00 to the input address connections 1 to 128 of a read-only memory PROM 64 can be created accordingly.

The one represented by the signals LTCH01 + 00 through LTCH07 + 00 Binary number is a measure of the time between successive input pulses that are generated by the flip-flop 30 via the signal line DVDAT + OO. The signal on the DEVDAT + OO line was a data or clock bit.

For the modified frequency modulation mode MFM, the The output signals of the programmable read-only memory PROM 64 are as follows: Signals PRMBXX + OO -xx 04 03 02 01 1 1 0 0 -04 with the logic level "1" indicates that the content of two information storage cells was received with the logic level -03 1 indicates that the information storage cells contain address marks C missing Clock) -02 with the logic level "O" indicates that the previously received bit is a Was clock bit and that the second data bit has the binary value "O" -01 with the logic level "O" indicates that the first received data bit has the binary value "O" 0 0 0 0 -04 with the logic level "O" indicates that a data cell was received -02 with the logic level "O" indicates that the previous received bit is a clock bit was -01 with the logic level "O" indicates that the data bit in the Felle has the binary value "O" has 0 0 1 1 -04 with the logic level "O" indicating that a data cell is being received became -02 with the logic level "1" indicates that although the preceding bit is a Can be data or clock bit, the bit just received has the binary value i, if the bit position 01 has the logic level 1.

1 0 0 0 -04 with logic level 1 indicates that two memory cells with information received -02 with the logic level "O" indicates that the bit has the binary value "O" in the second received memory cell -01 with the logic level "0" indicates that the bit is in the first memory cell received the binary value ~ 0 "has 1 0 1 0 -04 with the logic level" 1 "indicates that the content two memory cells was received = with the logic level ";" indicates that the Bit in the second received memory cell has the binary value 1 -01 with the Logo level "O" indicates that the bit in the first received memory cell is the Has binary value "O".

The MFM clock signal 22 according to FIG. 2a together with the PROM bit pattern According to FIG. 4, the flip-flop 30 is set when the pulse 22b is received via the signal line DVDAT + OO, thereby simultaneously output pulses RDTX01 + 00 and RDTX11 + 00 of shift registers 32 and 38 are triggered. Be on it referred to that the clock position 22a has the binary value "O". The output pulses the shift registers are shifted by successive clock pulses 25MHZ + 00. The output pulse RDTX06-00 again sets the counters 58 and 60 to a predetermined one Count, which normally corresponds to the hexadecimal value 10. The counters 58 and 60 count the Clock pulses 25.xHZ + OO until the pulse 22e is received via the signal line DEV3AT + OO. The shift registers 32 and 38 shift their content again with successive clock pulses 25CET + 0C, initially the output pulses RDTX01 + 00 and RDTX1: +00 are output. if the output signal RDTX02 + 00 is set to logic level I, the output signals are the counters 58 and 60 are stored in the register 62 and the signal LSTDAT + c0 is is at logic "1", indicating that pulse 22b is a bit of data was. The output signals of the register 62 select in the read-only memory PROM 64 select one of the address storage locations between 20C and 222 in FIG. 4, whereby the Output signals PRMB04 + 0C- to PRMB01 + 00 by binary signals 1000 accordingly na which indicates that two memory cells have been read, that the bit positions 22d and 22f have the binary value "0" and that the bit position 22e represents a clock bit.

Bit positions 22b and 22e are approximately 3 microseconds apart in time separated. During this period the counters 58 and 60 have 75 clock pulses 25MHZ + 00 counted. Since the counter is preset to the hexadecimal value 1086 after the signal RDTX16-0 and their content in register 62 with the appearance of the signal RDTX02 + 00 has been transferred, the address memory location 212 is selected (75 + 16 - 7 + 128 = 212; 128 because the previous bit was a data bit and -7 due to the difference between RDTX06-00 and RDTX02 + 00). The signal DATBTO + OO on the bit position 22d with the binary value ~ 0 "is stored in the shift register 44 and shifted when the signal RDTX16 + 00 occurs. The shift register 44 becomes advanced by the signal RDTX16 + 00 via a NOR gate 40 and an AND gate 42, since the signal MFMXXX-OO has the logic level "O" and the signal RDTT6 + 00 the logic level Has "1". The shift register 44 is incremented when the signal RDTY16 + 00 rises.

The content of the shift register 68 becomes RDTX14 + 00 with the next signal shifted and the bit position 22f is in the shift register 44 saved and shifted when the signal RDTX16 + 00 occurs. This second cycle was generated by the output signal ALRTSX + 0O of an AND gate 34, which is the output signal RDTX12 + 00 of the shift register 38 via the OR gate 36 to the logic level "1" sets, the contents of the shift register 38 by successive clock pulses 25MHZ + 00 is shifted.

The counters 58 and 60 are set to the hexadecimal value 10 by the signal RDTX06-00 set in advance after receiving pulse 22e. If the Pulse 22h is received, the output of counters 58 and 60 is again transferred to register 62. Since the previously received pulse was a clock pulse, the signal LSTDAT + OO is at the logic level "0", whereby the lower half of the read-only memory PROM64 is selected. In this case select the output signals of the register 62 an address storage location in the range between 72 and 94 in the read-only memory PROM 64 off, whereby output signals PRMB04 + 00 to PRMB01 + 00 with the corresponding Binary signals 0011 are generated.

The output signal DATBTO + OO with the logic level 1 is in the shift register 44 and the output signal LSTDAT + OO is set to logic level 1 to indicate that pulse 22h is a data bit.

The Latenimpuis 22j leads to binary signals 0011 at the output of the Read-only memory PROM64 are generated, and that a binary value 1 in the shift register 44 is saved.

The data pulse 22n results in binary signals 1010 at the output of the Read-only memory PROM 64 are generated and that two data bits 221 and 22n in the shift register 44 can be stored as described above.

A synchronization between the information is required to produce that is received from the disk adapter 12 and received on the system bus 2 is sent out. 12 bytes with the binary value l10 "are saved on the memory track written, followed by 3 bytes of address marks. The address marks are through a missing clock at the transition point between the memory cells 4 and 5 of each address mark byte.

The shift register 44 stores data bits with the binary value '0', ' received by the unit 14. When the data bits through the shift register 44 are pushed through, then the number of consecutive #ts with the binary value "O" is counted by a counter 84. When the output signal DATX02 + 00 of the shift register 44 is at the logic level "O", it is sent via an inverter 48 to a Input of an AND gate 82 applied. When the signal RDTX14 + 00 occurs the output signal CNT55T + 00 is applied to the clock input of the counter 84, which the increasing clock pulses. The counter 84 is activated by the signal DATX07 + 00 is reset to logic level 1, indicating that a signal with the Binary value 1 is applied to the reset terminal of counter 84 via inverter 5Z will. The output signal CNT55C + 00 with the logic level "1" indicates that 3 bytes with the binary value "O" have been received and it prevents the counter 84 from advancing therein the output of AND gate 82 through inverter 52 at the logic level "O" is held. two bytes with the binary value "O" are indicated by the counter 84 and the third byte with the binary value 0 is stored in the shift register 44.

When the first address mark byte is received with the missing clock pulse the read-only memory PROM 64 delivers binary output signal with the value 1100, which indicates that two information memory cells with a missing clock bits were received. The output signal MISCLK + OO of the shift register 68 is fed to an input of an AND gate 74, which is activated when the signal occurs RDTX17 + 00 an output signal FONEST + OO to the clock input of a D flip-flop 76 applies, whereby this flip-flop is set when the clock signal rises. That The output signal FONDXX-OO with the logic level "O" keeps the flip-flop 76 in the set position State.

The output signal FONEXX + OO of the flip-flop clocks signals into one FIFO memory 80, which enables the storage of data signals on the output line DATFIF + OO of a multiplexer 46 etro # becomes.

One of the two signals CNT5SC + 00 or FONEXX + OO at the OR gate 88 with the binary value "1" sets the clock enable output signal ÅLECLX + OO to Logic level "1". If the output signal PRMB02 + 00 of the read-only memory PROM64 the Has logic level "1", the output signal LSTDAT + OO of the AND gate 72 becomes stored with the logic level "1".

In FM mode, the upper half of the memory locations are stored in the read-only memory PROM 64 is addressed, since that is applied to the decimal address input terminal 256 Signal MFMXX-OO has the logic level 1. In FM mode the output signals show of the read-only memory PROM 64 to: Signals PRMBXX + OO -xx 04 03 02 01 C 0 1 1 -O4 with the logic level "O" indicates that the memory cell has a data bit -02 with a logic level "1" indicates that the previous bit was a clock bit -01 with the logic level "1" indicates that the data bit has the binary value ~ 1 "0 0 0 0 -04 with the logic level "O" indicates that the memory cell has a data bit -CA with the logic level "O" indicates that the data bit has the binary value "O" 1 0 0 0 -04 with the logic level "1" indicates that no data bit is in this half-cell is present.

0 1 1 1 -03 with logic level "1" indicates that the byte is considered to be a Address mark has a missing clock -02 with the logic level "1" indicates that the previous received bit has the binary value 1 -01 with the logic level "1" indicates that this received data bit has the binary value "1" in the FM mode sets the signal PR5SB04 + 00 applied to the NOR gate 40 at logic level 1 the output signal RDTT16 + 00 to the logic level "O", whereby the clock input signal of the shift register 44 is suppressed when writing the address mark.

Further, in the FM mode, it becomes the zero input terminal of the multiplexer 46 enabled, which causes the DATX02 + 00 signal to shift the data information FIF080 is permitted.

FIG. 4 shows a timing diagram for the logic according to FIG the processing of the data sequence 22 according to FIG. 2a.

The freely oscillating 25MHz clock 100 has a cycle time of 40ns. The data are received in the form of a DEVDAT + OO pulse of 200ns, this being The pulse sets the flip-flop 30. The signal DATSTR + OO starts a shift cycle registers 32 and 38. This cycle is 80ns, with the signals RDTX01 + 00 to RDTXo8 + 00 and RDTX11 + 00 to RDTX18 + 00 are output.

In typical operation, pulse 22b is over the signal DATSTR + OO received. The counters 58 and 60 are activated by the timing signal RDTX06-00 set to the hexadecimal value 10, and the contents of the counters when increasing from successive 25MHz clock cycles. The pulse 22e occurs 3ns later of the signal line DATSTR + OO, whereby the count of the counters 58 and 60 in the Register 62 is loaded. The output of register 62 is applied to the address input of the read-only memory PROM 64, whereupon the binary signal 1000 is read out, this indicates that two information storage cells are being received and placed in the shift register 68 have been loaded. The low order bit of the binary value 1000 goes into the shift register 44 with the binary value 10 "(bit 22d). The binary value 1000 is increased by one position shifted to the right and again the least significant bit of the shifted Binary value X100 with the logic level "O" in the shift register 44 as a binary value nO ".

(Bit 22f).

It should be noted that in the case of an output signal with the Binary value 1010 of the read-only memory PROM indicates the lowest-ranking binary value "01l, that the bit position 221 has the binary value "O". A right shift of the binary value 1010 in the shift register results in the binary value X1011 being the lowest order Bit position has the binary value "1". This bit position becomes the shift register 44 with the binary value ~ 1 "(bit 22n).

FIG. 5 shows the bit configurations in the lower half of the read-only memory PROM 64 for MFM mode. The level for the formation of the MFM coding scheme is the following: 1. A memory cell contains a clock position followed by a data position and their duration extends over 2 # s.

2. If a memory cell contains a data bit with the binary value 1, so it does not contain a clock bit.

3. If a memory cell does not have a data bit with the binary value 1 and the previous memory cell has a data bit with the binary value 1, so it has no clock bit. If the previous memory cell has a data bit with has the binary value "O", the present cell has a clock bit.

in MFM mode, if the previous bit was a clock bit, then occurs the next detected bit is either 2 or 3 cis. If the next bit in 4 µs occurs, this indicates that the missing clock position of the address mark has been read became.

If the previous bit was a data bit with the binary value "1", so the next bit is recorded in 2, 3 or 4 cis.

According to FIG. 6, there is a clock bit in each in the FM mode Storage cell. A memory cell extends over 4 µs. No pulse is given received the binary value "O".

When a clock bit is detected, the next detected bit has either the binary value "1" in 2 Cis or it corresponds to the next clock pulse in 4 ## .. . When a bit with the binary value "1" is detected, the next one in FIG. 4 shows Clock bit indicates that the data forms an address tag byte.

According to FIG. 3, the output signals modify the address memory locations the read-only memories PROM 90 and 92 are those preset in the counters 58 and 60 hexadecimal value.

The signals LTCH01 + 00 to LTCH08 + 00 are applied to the address input terminals the read-only memories PROM 90 and 92 are applied. According to Figure 2c, the time is between the pulses A and B 2. This leads to an output count of the counters 58 and 60 of 5910. The counters were at 1010 when the logic signal RDTX06-00 rose has been preset. Counters 58 and 60 were originally set to 1610 so that they have counted the rise of the clock signal 25 MHZ + OO 43 times. Counters 58 and 60 normally count 25MHZ + 00 in 2ßS 50 clock cycles.

However, the first clock cycle counted corresponds to 25MHZ + 00 to the Rise of the clock after the rise of the signal RDTX06-00, which signal the counters Presets 58 and 60 at the 8th clock pulse in the cycle. The count becomes that Register 62 transferred when the RDTX02 signal rises, resulting in a count from So - 8 + 1 or 4310 leads. The addressed storage location in the PROM 90 and 92 is given by 128 + 16 + 43 = 18710. The number 128wo is added because the Bit A in Figure 2c was a data bit and the signal LTCH08 + 00 has the logic level "1".

According to FIG. 7, the address memory location 187 has the hexadecimal value 10 or the decimal value 16.

According to Figure 2c, the data bit c is delayed by 0.3 # s, whereby a Count of 7 is added, resulting in an addressing of the memory location 19410 leads in read-only memories 90 and 92.

The content of memory location 19410 results from FIG. 7 as a hexadecimal value 13 or a decimal value 19 which is preset in counters 58 and 60. That According to FIG. 2c, data bit D is received 6 # s earlier, resulting in an address memory location from 225 (128 + 19 + 85 - 7) and to a preset value of -hexadecimal OA or decimal 10 leads.

The data bit E is received 0.3Es later, eliminating the address storage space 18810 is selected and the hexadecimal value 10 is preset.

According to FIG. 5, the address memory location 187 indicates that the bit A is a data bit and that the bit B is a data bit with the binary value "1". The address space 194 indicates that bit C is a data bit with the binary value "1". The address storage space 225 indicates that two memory cells were read, the first memory cell a data bit with the binary value "O" and the second memory cell a data bit has the binary value ~ 1 ".

As for the logic circuits, the following circuit components have been made used: flip-flop 30 74S74 flip-flop 66 74S74 flip-flop 76 74L74 shift register 32, 38 746S164 Shift register 68 746S195 Counter 58, 60 74LS169 Counter 84 74LS161 Register 62 74LS374 Multiplexer 46 74LS157 All of these elements are in the book by Texas Instruments Inc. "The TTL Databook for Design Engineers Copyright Described in 1976.

Read-only memories PROM 64, 90 and 92 93446 These read-only memories are in "Bipolar Memory Databook" published 1977 by Fairchild, 464 Ellis Street, Mountainview, California.

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Claims (8)

Data retrieval system Claims: Data retrieval system for converting a from a device in frequency modulation mode FM or in modified Frequency modulation mode MFM received information sequence of clock and data signals into decoded data signals, g e k e n n z e 1 c h n e t d u r c h an interval timer for the reception of the information sequence --a for the formation of interval timing signals, the # 4t information sequence between successive information bits display at a predetermined logic level; one to the interval timer connected read-only memory that responds to the interval clock signals ROM for generating multiple data status signals; and one connected to the ROM and data interpreting means responsive to the data status signals for Display of the bit allocation of successive bytes of the information sequence, whereby the consecutive bytes several bytes with data signals in a bit configuration with the binary value "O", followed by several bytes with a bit configuration accordingly an address tag followed by several bytes of data field. 2. System according to claim 1, d a # d u r c h g e k e n n z e i c h n e t that the interval time clock device has: a freely oscillating clock generator for generating clock pulses; a receiving device for storing each Information bits at the predetermined logic level and for generating an output data signal; a first shifting device connected to the receiving device and the clock generator, the several shift timing signals due to the output data signal and the clock pulses generated, a metering device connected to the snow-making device and the clock generator, which is triggered by a first Verschiebe-Zeittaktsigr.ai and based on the Clock pulses that generate interval timing signals. 3. System according to claim 2, d a d u r c h g e k e n n z e i c h n e t that the interval clock device on a predetermined count according to the change over time between successive information bits of the information sequence is triggered at the predetermined logic level and an integer. 4. System according to claim 2, d a d u r c h g e k e n n z e i c h n e t that the ROM comprises: one to the counter and the first shifter connected register for storing the interval clock signals on the basis of a second shift timing signal, thereby generating multiple lock signals will; a read-only memory ROM connected to the register, which is based on the Lock signals responds to select an address memory location of the ROM, whereby this address memory location corresponds to several binary signals stores; and a second shifter connected to the ROM and the first shifter is connected to the binary signals on the basis of a third shift timing signal to store, thereby generating second and third data status signals. 5. System according to claim 4, d a d u r c h g e k e n n z e i c h n e t that the data interpreting means comprises: one to the second and first Shifting device connected third shifting device for storage of the second data signal and its shift due to a fourth shift timing signal, thereby generating multiple data shift signals; one to the first and third Shift device connected zero byte counter, which is due to a first data shift signal with the logic level "O" the fourth shift timing signal counts and generates a zero byte output when the first data shift signal of logic "O" level during a predetermined number of the fourth shift timing signals Will be received; and one to the zero byte counter and the second shifter connected data field recognition device, which is indicated by the zero byte output signal is prepared and set by the third data status signal, creating a series cycle indicating that the system is using a predetermined number of bytes received all "011 data bits and address tag bytes and that the next information is given by the data field bytes. 6. System according to claim 5, d a d u r c h g e k e n nz e i c h n e t that the ROM further comprises: one to the ROM, the zero byte counter and the data field recognition device connected device for last data, those based on the first binary signal, the zero byte output signal and the serial clock generates a last data signal which is fed to the register to generate a first Generate locking signal within the plurality of locking signals. 7. System according to claim 6, d a d u r c h g e k e n nzeich that the interval timer further comprises: one on a predetermined one Count adjustable device attached to the register and the counter is connected and due to the interlocking signals an address memory location selects the device with a predetermined count, this address memory location Stores bits indicating predetermined counts. 8. System according to claim 7, d a d u r c h g e k e n n -z e i c h n e t that the device has a read-only memory for the predetermined count Includes ROM with 512 memory locations.