DE3170791D1 - Bipolar transistor and process for fabricating same - Google Patents

Bipolar transistor and process for fabricating same

Info

Publication number
DE3170791D1
DE3170791D1 DE8181100812T DE3170791T DE3170791D1 DE 3170791 D1 DE3170791 D1 DE 3170791D1 DE 8181100812 T DE8181100812 T DE 8181100812T DE 3170791 T DE3170791 T DE 3170791T DE 3170791 D1 DE3170791 D1 DE 3170791D1
Authority
DE
Germany
Prior art keywords
bipolar transistor
fabricating same
fabricating
same
bipolar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181100812T
Other languages
English (en)
Inventor
Cheng Tzong Horng
Robert Otto Schwenker
Paul Ja-Min Tsang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3170791D1 publication Critical patent/DE3170791D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)
DE8181100812T 1980-03-03 1981-02-05 Bipolar transistor and process for fabricating same Expired DE3170791D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/126,610 US4309812A (en) 1980-03-03 1980-03-03 Process for fabricating improved bipolar transistor utilizing selective etching

Publications (1)

Publication Number Publication Date
DE3170791D1 true DE3170791D1 (en) 1985-07-11

Family

ID=22425781

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181100812T Expired DE3170791D1 (en) 1980-03-03 1981-02-05 Bipolar transistor and process for fabricating same

Country Status (4)

Country Link
US (1) US4309812A (de)
EP (1) EP0035126B1 (de)
JP (1) JPS5946104B2 (de)
DE (1) DE3170791D1 (de)

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* Cited by examiner, † Cited by third party
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US4371423A (en) * 1979-09-04 1983-02-01 Vlsi Technology Research Association Method of manufacturing semiconductor device utilizing a lift-off technique
US4415371A (en) * 1980-12-29 1983-11-15 Rockwell International Corporation Method of making sub-micron dimensioned NPN lateral transistor
US4372034B1 (en) * 1981-03-26 1998-07-21 Intel Corp Process for forming contact openings through oxide layers
JPS5866359A (ja) * 1981-09-28 1983-04-20 Fujitsu Ltd 半導体装置の製造方法
JPS5873156A (ja) * 1981-10-28 1983-05-02 Hitachi Ltd 半導体装置
US4385975A (en) * 1981-12-30 1983-05-31 International Business Machines Corp. Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
US4584763A (en) * 1983-12-15 1986-04-29 International Business Machines Corporation One mask technique for substrate contacting in integrated circuits involving deep dielectric isolation
DE3564518D1 (en) * 1984-09-29 1988-09-22 Toshiba Kk Heterojunction bipolar transistor and method of manufacturing the same
US4662956A (en) * 1985-04-01 1987-05-05 Motorola, Inc. Method for prevention of autodoping of epitaxial layers
US4782030A (en) * 1986-07-09 1988-11-01 Kabushiki Kaisha Toshiba Method of manufacturing bipolar semiconductor device
DE3880860T2 (de) * 1987-03-04 1993-10-28 Toshiba Kawasaki Kk Halbleiterspeicheranordnung und Verfahren zu ihrer Herstellung.
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions
US4818713A (en) * 1987-10-20 1989-04-04 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques useful in fabricating semiconductor devices having submicron features
US5374576A (en) * 1988-12-21 1994-12-20 Hitachi, Ltd. Method of fabricating stacked capacitor cell memory devices
US20010008288A1 (en) * 1988-01-08 2001-07-19 Hitachi, Ltd. Semiconductor integrated circuit device having memory cells
KR910005401B1 (ko) * 1988-09-07 1991-07-29 경상현 비결정 실리콘을 이용한 자기정렬 트랜지스터 제조방법
US5128272A (en) * 1991-06-18 1992-07-07 National Semiconductor Corporation Self-aligned planar monolithic integrated circuit vertical transistor process
DE4231310C1 (de) * 1992-09-18 1994-03-24 Siemens Ag Verfahren zur Herstellung eines Bauelementes mit porösem Silizium
US5266505A (en) * 1992-12-22 1993-11-30 International Business Machines Corporation Image reversal process for self-aligned implants in planar epitaxial-base bipolar transistors
KR960704351A (ko) * 1993-07-12 1996-08-31 존 엠. 클락 3세 비소 에미터를 지니는 반도체 디바이스를 제조하는 방법(process for fabricating semiconductor devices having arsenic emitters)
WO1996024160A2 (en) * 1995-01-30 1996-08-08 Philips Electronics N.V. Method of manufacturing a semiconductor device with a semiconductor body with field insulation regions provided with recessed connection conductors
US5981374A (en) * 1997-04-29 1999-11-09 International Business Machines Corporation Sub-half-micron multi-level interconnection structure and process thereof
US6133139A (en) * 1997-10-08 2000-10-17 International Business Machines Corporation Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof
US6444536B2 (en) * 1999-07-08 2002-09-03 Agere Systems Guardian Corp. Method for fabricating bipolar transistors
FR2799048B1 (fr) * 1999-09-23 2003-02-21 St Microelectronics Sa Procede de fabrication d'un transistor bipolaire vertical auto-aligne
US6660664B1 (en) * 2000-03-31 2003-12-09 International Business Machines Corp. Structure and method for formation of a blocked silicide resistor
US7132299B2 (en) * 2004-02-27 2006-11-07 Micron Technology, Inc. Method of forming a magnetic random access memory structure
US7169654B2 (en) * 2004-11-15 2007-01-30 Freescale Semiconductor, Inc. Method of forming a semiconductor device
EP1878045A2 (de) * 2005-04-28 2008-01-16 Nxp B.V. Bipolartransistor und verfahren zu seiner herstellung
US7687887B1 (en) * 2006-12-01 2010-03-30 National Semiconductor Corporation Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3940288A (en) * 1973-05-16 1976-02-24 Fujitsu Limited Method of making a semiconductor device
US4174562A (en) * 1973-11-02 1979-11-20 Harris Corporation Process for forming metallic ground grid for integrated circuits
US4068018A (en) * 1974-09-19 1978-01-10 Nippon Electric Co., Ltd. Process for preparing a mask for use in manufacturing a semiconductor device
US3986897A (en) * 1974-09-30 1976-10-19 Motorola, Inc. Aluminum treatment to prevent hillocking
DE2621956A1 (de) * 1975-05-19 1976-12-02 Nat Semiconductor Corp Verfahren zur passivierung einer aluminiumschicht auf einem halbleiter- schaltungsbaustein
US4063992A (en) * 1975-05-27 1977-12-20 Fairchild Camera And Instrument Corporation Edge etch method for producing narrow openings to the surface of materials
DE2535156C3 (de) * 1975-08-06 1978-08-31 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer Schicht mit vorgegebenem Muster von Bereichen geringerer Schichtdicke und Verwendung der Schicht als Maske bei der Dotierung
US4060427A (en) * 1976-04-05 1977-11-29 Ibm Corporation Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps
US4110125A (en) * 1977-03-03 1978-08-29 International Business Machines Corporation Method for fabricating semiconductor devices
US4104086A (en) * 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
US4139442A (en) * 1977-09-13 1979-02-13 International Business Machines Corporation Reactive ion etching method for producing deep dielectric isolation in silicon
US4159915A (en) * 1977-10-25 1979-07-03 International Business Machines Corporation Method for fabrication vertical NPN and PNP structures utilizing ion-implantation
US4160991A (en) * 1977-10-25 1979-07-10 International Business Machines Corporation High performance bipolar device and method for making same
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
US4242791A (en) * 1979-09-21 1981-01-06 International Business Machines Corporation High performance bipolar transistors fabricated by post emitter base implantation process
US4252582A (en) * 1980-01-25 1981-02-24 International Business Machines Corporation Self aligned method for making bipolar transistor having minimum base to emitter contact spacing

Also Published As

Publication number Publication date
EP0035126A3 (en) 1982-09-01
EP0035126B1 (de) 1985-06-05
JPS5946104B2 (ja) 1984-11-10
EP0035126A2 (de) 1981-09-09
US4309812A (en) 1982-01-12
JPS56126967A (en) 1981-10-05

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee