DE3114062A1 - Circuit arrangement for clock conversion - Google Patents

Abstract

The invention relates to a circuit arrangement for converting a clock with the frequency f1 into a clock with the frequency <IMAGE> At clock frequencies in the MHz range, it is no longer possible to start from a master clock which is higher by a multiple than the required clock in the clock conversion. It is therefore proposed to divide the original clock with the frequency f1 by the factor m and logically to combine the resultant pulse sequence with the original pulse sequence. The required frequency f2 is then filtered out by means of a narrow-band filter from the frequency mixture of the logically combined pulse sequence. <IMAGE>

Description

Licentia Patent-Verwaltungs-GmbH Z13 PTL-BK / Mo / be

Theodor-Stern-Kai 1 BK 81/35

D-6000 Frankfurt 70

Circuit arrangement for clock conversion

When transmitting digital signals over cables a ternary code is often used. This code allows against the binary code and the pseudo-ternary codes (AMI, HDB3) a reduction in walking pace. Because lines at high frequencies one with the frequency show increasing attenuation is obtained by reducing the step speed with the same transmission length less attenuation.

Ternary codes of the family 4B-3T are often used for this; a word made up of 4 binary steps (bits) is converted into a word made up of 3 ternary steps (tits), as such transmitted and converted back on the receiving side.

When converting to the ternary signal, a clock conversion in the ratio ^J 1: 3 is necessary, with reverse conversion in a ratio of 3: 4.

31U062

BK 81/35

Methods are known which carry out this clock conversion.

Such a method works with a master clock that is 6 times higher than the binary clock and thus 8 times higher than the ternary cycle. By dividing it by 6, you get the binary rate, when you divide it by 8, you get the ternary rate. The division ratio should be even in order to get an output clock with a duty cycle of 0.5. 10

This method is for very high clock frequencies in the MHz range not usable.

A second method works with clock synthesis. Here, the binary clock is divided by 8, which results in a controllable oscillator generated ternary clock by 6, both clocks are compared in a phase comparison circuit, their output signal after filtering and amplification

controls the controllable oscillator. 20th

This method can also be used for high frequencies, but the effort is considerable.

In a third method dec Binärtakt is divided by a factor of 4 and the resulting signal is very greatly shortened in time so that narrow Imp arise rise with long pulse intervals. Then it arrives at a narrow band filter, eg a tank circuit, which filters out the third harmonic as the desired ternary cycle. Since this tank circuit generally has a poor quality, a noticeably damped oscillation will occur on it. Furthermore, the energy content of the resonant circuit is heavily dependent on the pulse duty factor of the control signal.

This method is also suitable for high frequencies with the

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T "- .. ^: .:. 31U062

- 5 - BK 81/35

written nights len usable.

The invention is based "on the object of a clock converter circuit anzueber. that works up to very high frequencies (MHz range) and can be implemented with less effort is than it was previously possible.

The problem is solved as described in claim 1. the Subclaims indicate "advantageous developments. 10

In the following, the invention will be explained in more detail with the aid of figures using an exemplary embodiment.

Fig. 1 shows an exemplary circuit arrangement according to the invention,

FIG. 2 shows the timing diagram associated with FIG.

In the embodiment, the binary clock with the frequency f., Divided by the factor H , the resulting pulse train is linked with the original pulse train. The resulting frequency mixture contains high spectral components at dt-r sought frequency f ~ of the ternary cycle. By filtering with an oscillating circuit, the current cycle is obtained, which can be converted into a square-wave signal in a subsequent pulse shaper stage. In general, the clock division is done by logic circuits. The combination of the original pulse train of frequency f- with the divided pulse train of frequency f ₂ ^{/ m} can be done in an exclusive-OR gate (Fig. 1).

The effort of the solution according to the invention is therefore very low, the control of the narrow band filter is, for example, significantly improved compared to the third known method.

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Claims (3)

31U062 Licentia Patent-Verwaltungs-GmbH Z13 PTL-BK / Mo / be Theodor-Stern-Kai 1 BK 81/35 D-6000 Frankfurt 70 Claims ; 1J Circuit arrangement for converting a clock of a first frequency f- into a clock of a second frequency fp with the help of logic circuits and filters, the two frequencies in a rational ratio - to stand by each other, characterized by that the frequency f .. of the first clock with the help of a Divisible by the factor m, that the resulting pulse train with the frequency f., / m with the pulse train of the first clock with . Can be linked using a logic circuit (L) and that- from the frequency mixture of the linked pulse train with the help of a narrow band filter the desired clock with the frequency f «= f _i . £ ■ can be filtered out. 2 ι m - 2 - BK 81/35 2. Circuit arrangement according to claim 1, characterized in that that the logic circuit (L) is an exclusive-OR circuit. 3. Circuit arrangement according to claim 1, characterized in that that the logic circuit (L) is an analog multiplier is.