DE3107570C2 - Raster scanning video display system - Google Patents

Abstract

A raster scan video display system is described in which a panning control system is provided so that a panning operation can be performed over an arbitrarily large image which may be larger than the image memory recordable from which the display is formed. For this purpose, the image memory is made toroidally addressable, i.e. in a modulo or border manner. Therefore, if a memory address limit is reached during a raster readout, the readout operation continues without interruption from the opposite limit. The image memory is slightly larger than is required to display the image currently being played back. The excess memory zone has an edge zone which surrounds the readout zone which has just been scanned and which contains image data which form a continuation of the image data just read out and displayed. This enables an immediate pivoting into the edge zone. In addition, the surplus storage area has a rewrite area on the opposite side of the peripheral area from the readout area, into which new image data can be inputted as continuation of the data information during the panning operation. Appropriate circuitry facilitates the entry of new data into the rewrite zone and controls the panning speed to ensure that the displayed image does not reach the rewrite zone until the new data has been entered in that zone

Description

The invention relates to a raster scanning video display system according to the preamble of Claim 1.

Graphic viewing device stations are increasingly being used to make computer-generated image information visible Use. By displaying such information on the screen of a cathode ray tube (CRT), the user can see the image almost as quickly as it is produced by the host computer. This is before Especially advantageous when construction work is carried out with the participation of computers, as construction changes can already be displayed graphically when they are carried out. With the help of Scaling and panning facilities allow the operator to use the video display system or viewing device are facilitated. The term "panning" means moving what is displayed Image section to adjacent sections of the image. The possibility of pivoting allows the operator of the video display system provides a smooth, seamless movement of whatever appears on the screen "Viewing window" over a larger image that is not completely on the screen at this point in time Display can be brought. /

Cathode ray tube based video display systems can be divided into two basic classes: Raster scan imaging and vector generated displays. For a vector generated CRT display the image is broken down into a list of vectors that are emitted by the electron beam from the cathode ray tube Regenerate each image to be drawn on the cathode ray tube individually. The more complex the drawing the higher the number of vectors to be drawn and the lower the drawing speed of the image, since the number of vectors that can be drawn by the system in a given time unit is limited is.

Raster scan video display systems to which the invention pertains operate in a conventional manner Televisions similar principle. The surface of the cathode ray screen is covered by the electron beam in a Numerous horizontal lines swept over. The intensity of the electron beam is determined by the scanner, des CRT screen modulates to produce different intensities of light or color on the screen and accordingly to make the desired image visible. In contrast to the vector scanning system, the Image generation in the raster scanning system is unaffected by the image content.

A raster scanning video display system of the genre of the present invention is disclosed in US Pat. No. 4,070,710 known. In addition to creating a background grid for the image and changing the scale of the one to be displayed The known video display system enables the image content to be panned, i. E. H. an apparent shift of the image displayed on the display device over a larger image stored in the main memory. Such Viewing devices have a limited size, if only for reasons of cost. A picture 100 or 120 cm long or Width cannot be displayed on the screen at the same time. The panning gives the Operator the ability to move the viewing window formed by the screen to see the overall picture to make them visible in sections one after the other.

To achieve the panning effect is in the video display system known from US-PS 40 70 710 with Raster scanning when the limit of the image memory is reached, the entire image memory is rewritten, whereby the display data is transferred to another part of the image memory. As the entire image memory content is rewritten, the operation of the known video display system must be interrupted, when the panning movement reaches the limit of the image memory. It's technologically difficult to do the whole thing image to be displayed in the image memory in the short period of about 1 ms between two successive ones Rewrite raster scans. These are a high-speed image memory and complicated digital logic circuits necessary.

An alternative known method is based on double buffering of the image memory. Two image memories, each of which can store the information required for an entire raster scan occupied with the data from two raster scans in two consecutive pairs. During the raster scan of the one image memory, the other image memory can be moved in a suitable manner with an additionally shifted one Image to be brought up to date. The alternate use of the image buffers for each Raster scanning is continued until the desired goal of the pivot command is reached. This System requires twice the image storage capacity for the video display system. The overall circuit must be like this be designed to operate at a sufficiently high speed to transfer data relating to a Image into the appropriate image memory within one raster scan, e.g. B. within 17 ms or Veo second to be able to enroll again.

A third known method of achieving a panning effect in video display systems with raster spacing

sampling consists in providing a sufficiently large image memory in which a larger part of the The entire image can be saved. When a pan command is received, the information in Raster form read out from another part of the image memory. This method has the advantage that within

the limits of the image memory the pan can be carried out as quickly as you like, since the data is in the

Image memory are immediately available. In addition, the needs to write new data in the image memory P-.

tends to use the circuit not to be as fast as in the systems previously discussed because the re-enrollment y

ben is independent of the raster scan time. But is unfavorable costly increase in Bildspei- F ₄

storage capacity. Also, the extent of the picture panning is even with a corresponding enlargement of the picture memory

chers limited. Therefore, this known video display system is only for limited panning movements

suitable. f

The invention is based on the object of improving the video display system with raster scanning of the type mentioned at the outset so that, with limited image storage capacity and a relatively low operating speed of the writing device, it is possible to pan over an image of any size on the viewing device.
To achieve this object, the invention provides the characterizing features of claim 1.

In the invention, the storage capacity of the image memory is only slightly larger than that used for. Storage of the data just displayed on the screen is required. The additional. '"\

Storage capacity in the edge zones surrounding the read-out zone in the image memory is used for writing the; '. ' brought data directly to the respective image border. The image memory becomes toroidal accessed, where the original address of the image accessed by the raster scanner is somewhere ;; -, can be in the image memory. If a memory address exceeds a coordinate limit, the Access to the opposite border in a toroidal fashion, with a toroidal overrun of the image memory.

In the video display system according to the invention, the image memory is divided into three zones:

1. the read-out zone, which defines the data ι that defines the image part that is displayed on the screen

contains;

2. the pan or edge zone, which contains the image data which the image parts in connection with the Define readout or display zone. This edge zone can be used when the image is panned by the raster scanner can be accessed immediately, since the image data required for panning are immediate;

available in cash; ί

3. The write-in zone which is used by the write-in device for entering and storing new data i , which define additional image parts to support the image display panning. §

In the following, the invention will be described in greater detail using an exemplary embodiment shown in the drawing explained In the drawing shows

F i g. 1 a schematic representation of the organization of the image memory,

F i g. 2A and 2B are schematic representations of the toroidal aspect of the image memory with the display zone, the pivoting limit zone and the writing zone before and after a toroidal pivoting operation, ψ

F i g. 3 shows an electrical block diagram of an exemplary embodiment of the invention, ■ ν

F i g. 4 is an electrical block diagram of the circuit shown in FIG. 3 swivel control device shown, 1

F i g. 5 is an electrical block diagram of the circuit shown in FIG. 3 illustrated write control device,

6 is a flow chart showing an alternative example of a method for determining a Swivel speed is summarized,

F i g. 7A to 7D and 8A to 8E show a pictorial representation of the toroidal organization of the image memory in FIG Pivoting in a single axis and in two axes, with the addition of erasing and writing Stripes within the image memory under control of the circuit according to FIGS. 9 to 11 is illustrated,

9 and 10 together show an electrical block diagram of another exemplary embodiment of one according to the invention trained torus swivel control device,

F i g. 11 is an electrical block diagram of a strip, erase and write control device which together >

men with the circuit according to FIGS. 9 and 10 is used * and

F i g. 12 is an illustration of the zones of a main picture that is written into the picture memory when panning. will practice.

In the following, preferred exemplary embodiments of the invention are explained with reference to the drawing?

F i g. 1 shows a schematic representation of an image memory 105, the digitized for storing data% ■ for a video graphics display system comprising raster scanning is used as later will be explained, which has; _ image memory 105 a slightly greater capacity than the one to store the data of the each | f

image currently being displayed would be required. Even if it is one of many currently available || as an image memory directly accessible memories, e.g. B. a core memory, a semiconductor memory or a magnetic Bupple- (ma | V

gnetic domain) Storage can be used that has a special address for the storage used f |

may have control scheme is shown in FIG. 1 assumes that the image memory 105 has a suitable image memory addition | ίτ handle control circuit in a two-dimensional, grid-like, orthogonal address coordinate type address- g!

can be ized. As in Fig. 1 the image memory can be characterized by certain parameters Jyj,

be, d. that is, it can be addressed in such a way that it has P vertical columns of data and Q horizontal if.

With such an address organization there are P χ Q discrete addressable image information Φ; elements. It is assumed that the data defining each pixel, ie picture element, is contained in a part of a Γ-; Memory word or can be stored in some memory words. This is not critical for the invention:. ■ -, £

table, since the amount of information stored for each image pixel affects the addressability of the image memory? |

through an appropriate image memory access control circuit in a specified manner on a coordinate basis yj

unaffected.

A right-angled subgroup 102 of storage locations is shown within the image memory 105 , which corresponds to the display zone which is currently accessed synchronously with the raster scan and which is used to form the CRT display. This display zone 102 of the image memory 105 is essentially the digitized representation of the image which is currently being displayed on the display system. As shown, the number of columns used in the image display zone 102 can be denoted by / and the number of rows is denoted by L. The number of rows and columns in display zone 102 is directly related to the parameters of the raster scan. Thus, in one example of the invention, the raster controller 312 generates horizontal raster lines of 416 pixels each. Therefore, in this example / would have the value 416 and L would have the value 312 so that the size of the display zone 102 corresponds to the parameters of the raster scan. Of course, the invention described here is not restricted to these particular parameters for the image memory, since all numerical examples are within the scope of the present inventive concept.

A pan zone 103 surrounds the display zone 102. This pan zone 103 adds / additional columns to each side of the display zone 102 and M additional rows to the top and bottom of the display zone 102 . The pan zone 103 of the image memory 102 contains data which define the image at the edge next to the displayed image. When the display image origin 101 is moved within the image memory 105 , the pivot zone 103 creates immediately available image data on which the CRT image can be generated.

The panning zone 103 surrounds a writing zone 104 with a vertical stripe adding 2K additional columns of image data and a horizontal stripe adding 2N additional rows of image data. The writing zone 104 is that zone of the image memory 105 into which new graphic data are completely or partially written when the display zone 102 is panned. While the panning zone 103 creates a boundary of the image information which can be accessed immediately during the panning to form the CRT display, the write-in zone 104 is that part of the image memory 105 which is updated with the new image data during this panning process, so that it is after can serve as a new pivot zone 103 for updating. It is clear that the locations of zones 102, 103 and 104 in memory 105 are not fixed, but change as the CRT image is panned.

The current part of the write-in zone 104, which holds a new image stored due to a panning operation, is different for the two exemplary embodiments described below. G in the embodiment according to F i. 7A through 11, the entire vertical or horizontal stripe is written in a single stripe erasing and writing operation. In the embodiment according to FIGS. 3 to 6, the inscription is requested for a column or a row in each case, the inscription taking place along certain inscription border lines 104- V and 104 - // These lines represent in the exemplary embodiment according to FIGS. 3 to 6 represent the pictorial "edge" of the image data surrounding the display zone 102. When the display zone 102 is panned in the image memory 105 , the write-in boundary lines 104- V, 104- // ensure that that part of the write-in zone 104 is localized new image data must be updated to maintain the desired boundary information.

The write-in boundary lines consist of a vertical line 104 V and a horizontal line 104 - //, each of which has a special relationship to the position of the display region, if the address in the image memory 105 to the origin or home position of the displayed on the display screen image with X, Y , where the first value (ie "X") of the coordinate pair specifies the column of the image memory, then the vertical write-in boundary line 104-V consists of all pixels (picture elements) whose image memory addresses have a line value equal to X ' = (X + 1 + J + K) mod. P have. The horizontal write-in boundary line 104 - // consists of all pixels which modulate the image memory address with column values equal to Y ' = (Y + L + M + N) . Q have. (In the embodiment of FIGS. 1 to 6, the y-origin is in the upper left corner of the memory and Y increases as the image moves downwards.) As a result, the write-in boundary lines 104- V, 104- // each arranged in a toroidal shape "on half" of the image memory 105 from the center of the display zone 102 in the image memory 105 , where the modulo P and modulo Q operations cause the image memory to be addressed in a toroidal manner.

If the display zone 102 is panned horizontally and vertically by a certain number of pixels, the writing boundary lines 104 - //, 104- V are preferably moved horizontally and vertically by the corresponding number of pixels in order to obtain the panning zone 103 . As long as this write operation proceeds mii a step of always sufficient so that a boundary or an edge of image data in the image memory 105 is present, the display region 102 surrounds then the operator or the operator takes the fact not true that the image memory is not the information regarding of the entire image traversed in the pan

Like F i g. 1 shows, the pan zone 103, although it contains data surrounding the display zone 102, can be from one coordinate boundary edge to be "bordered" to the opposite edge. In the same way it is possible albeit in FIG. 1, it is not shown that the display zone 102 or the write-in zone 104 are also "enclosed" in a toroidal shape in the image memory 105, which is due to the position of the display image origin 101 in the image memory 105 depends It is essential that the coordinate address boundaries of the image memory 105 run in a toroidal shape, so that a positioning of the display zone 102 anywhere in the image memory 105 and a maintenance of the the pivot zone 103 surrounding the display zone 102 is enabled.

As noted above, certain known panning systems have provided additional image storage capacity execute the pan directly via this additional memory. With these known systems that was However, panning is limited to the actual size of the image memory toroidal access and a corresponding memory structure made use of the one continuous Allow panning of an image regardless of the actual image memory addressing limits.

As an illustrative example of the embodiment according to FIG. 1, the pivot zone 103 can be dimensioned so that

it enables M = 10 additional lines of image data to be maintained above and below the display zone 102 and / = 10 additional columns of image data on each side of the display zone 102, with the write zone 104 having an overall width of 2K = 2Λ / = 10 picture elements for the vertical and horizontal In this exemplary embodiment, the following results for the entire image memory:

(1 _ [(416 + 10 + 10 + 10) x (312 + 10 + 10 + 10)] / 416 χ 312)

19%

more than the display zone. This embodiment clearly shows the small increase of 19% of the Image storage capacity that is sufficient to correct a pan across an image in accordance with the teaching of the invention.

If an acnwenwiperaiiuii of X pixels is carried out horizontally, the part of the inscription zone 104 to be updated with the new bridge data is the part between the vertical inscription boundary 104-V and a parallel line which extends around X positions or places in the inscription line "!" . When the panning operation is performed in an upward and downward direction, a similar horizontal stripe in the writing zone 104 must be updated. A panning operation with both vertical and horizontal directional components, of course, requires an update of both the vertical and horizontal stripes associated with the respective directional components.

Although the panning operation may be determinative of the portion of the writing zone 104 to be updated the actual updating of the write-in zone 104 can be performed asynchronously with respect to the actual panning operation as long as the panning zone 103 is sufficient for panning the CRT image to provide the required image data.

In the illustrative example discussed above, a satisfactory pan rate with an appropriate "safety zone" around the display zone with / = M = 10 and K = N = 5 was obtained. In such an exemplary embodiment, a pivot zone 103 which contains the display image by 10 pixels in all directions provides data that extends in all directions and with a writing zone 104 with horizontal and vertical strips totaling 2A. = 2N = 10 additional picture elements coupled is sufficient edge information for a typical swing opera? Vx λ of a 416x312 pixel display. . .

Although FIG. 1 depicts the image memory organization as a rectangular coordinate system with specified lines and columns of image information, the invention provides an additional organizational structure for the Image storage. In particular, the image storage coordinate system is expanded to a ring-shaped or toroidal configuration in which a continuation along a coordinate axis is wrapped around the axis or a Moving around to the opposite side of the axle causes

Figures 2A and 2B more clearly illustrate the toroidal, or co-ordinate-enclosing structure of FIG Image memory 105 according to the invention. In Fig. 2A is the image origin 101 of the image to be displayed on the CRT Also illustrated is the display zone 102 of the image memory. The pivot zone 103 surrounds the Display zone 10Z Also shown are write-in boundary lines 104-V, 104-Win of the write-in zone 104.

FIG. 2B is a similar illustration of the image memory with a new image origin 106 made up of a CRT pan command results. The original image origin 101 is also shown. The display zone 102 of the The image memory has been suitably implemented and corresponds to the new display origin 106. The pivoting zone 103 and the writing boundary line 104-V, 104-rt have also been moved in a suitable manner. Since the display The origin of the image memory used is from the one shown in FIG. 2A indicated position to that according to FIG. 2 B the swivel zone or swivel edge 103 was accessed in order to transfer data to the CRT To deliver image pixels that were not previously displayed. Along with the movement of the display origin the write-in zone 104 has been updated to maintain an appropriate information boundary zone surrounding the displayed image. After the update, parts of the enrollment zone 104 became parts of the Panning zone 103 reclassified according to the movement of display zone 102. .,. ", ·.

The speed at which panning can occur is a function of several factors, including the dimensions of the panning zone 103 and the access speed to the image data. To prevent, that the operator or the operating person notices the presence of a restricted image data edge in the image memory 105, it is desirable to limit the swivel speed so that the swivel zone 103 t, "; ™" ^ hwnkfn can be maintained dynamically by the write logic, or vice versa, to ensure that the image update speed corresponds to the actual or maximum pan speed. Access to the image memory 105 in a toroidal fashion gives the possibility of continuous pivoting movement, with only a small part of the total image that can be captured by pivoting is actually stored in each case in the image memory 105 a main computer) can be accessed by a write-in circuit if necessary, notes the operator not the fact that the image memory does not contain the entire image over which the panning movement occurs is performed , .

An advantage of the invention is that only a minimal amount of image information during a Panning operation is written in the image memory 105. The panning system is provided so that the Display image origin can be located anywhere in image memory 105. The toroidal Structure of the image memory 105 increases the flexibility of image storage by eliminating the effect of the Coordinate boundaries. ,. , "

F i g. 3 is an electrical block diagram of an embodiment of the invention by which the toroidal image memory organization of FIGS. 1,2A and 2B is realized The graphic information is on the CRT 112 made visible The CRT operator gives a joystick 110 or a control panel either the pan direction or the desired target point of the image origin for the pan movement on It is not necessary to use the keypad or control panel 111 or a control

'■: enter stick 110; these input options are only representative of the specification of the parameters

i; meter of a swivel command.

, '"." ■ The joystick 110 is operated with a pan command processor 116 via a signal bus 113

: tied together. Similarly, the keypad or control panel i i i is connected to the via a signal bus 114

Pan command processor 116 connected. The pan command processor 116 uses the commands from the joystick 110 to i. commands received from the control panel 111 or any other pan command input device for the

Determination of the direction and the speed of the desired pivoting operation or the eventual one ! Image origin. This information is sent to the swivel control device 121 via a signal bus line 118.

The CRT 112 is connected to a raster control device 117 via a cable 115. The raster control device 117 generates synchronization signals on a bus 119 which indicate the beginning of each raster image or half-image, the beginning of each horizontal scanning line and the time of a bit information pixel. The raster synchronization signals from the bus 119 are beitet from the swing controller 121 processed \. The raster synchronization signals, which indicate the position on the CRT 112 for which the image information

tiön is just desired, as well as the front swivel arm processor 121 via the signal collection HS for Information provided gives the swivel control device 121 the possibility (using a |, appropriate toroidal translation) the display image origin 101 and the appropriate image memory addresses

) with the pixel information to be displayed in accordance with the raster scan of the CRT 112.

The swivel control device requests synchronously with the raster synchronization signals on the signal bus 119 121 image data from an image memory access control device 125 via an address bus 129. The image memory access controller 125 processes the memory access request from the pan controller device 121 and formats the request in the machine address scheme, which is based on the actual memory

chi; structure in the image memory 105 is required. The requested data are transmitted via a signal bus

_r -, 120 transmitted to raster control device 117. The grid control unit 117 uses the signals on the signal bus

f 'tung 120 pending data for formatting a composite video signal for the CRT 112th

| ί. The swivel control device 121 supplies the address of the display image origin via a signal bus 122

· 'And the pivoting movement information to the enrollment control device 126. The enrollment control device 126 use

: det this information to determine the need to update the frame buffer pan margin

103. If the panning zone 103 of the image memory 105 is due to a panning request for an update ■ -. · If necessary, a remotely located host or main processor 128 is connected via a signal bus

127 accessed. It is assumed that the main processor 128 is the one to be displayed or pivoted to contains or can generate overriding overall image. For example, the main processor can have a large ;, contain directly accessible storage capacity with digitized image information. Via manifold 127

ν, the write controller 126 can request any part of the image to be partially displayed and the information

! ■■ Store in the image memory 105, creating the desired relationship between the display zone 102 and the

Pivot zone 103 is maintained. The image information from the main processor 128 is received from the write controller 126 processed and via a memory address bus 123 and a data bus 124 provided to the image memory access control device 125

F i g. 4 is a more detailed electrical block diagram of an embodiment of the in FIG. 3 shown Pan controller 121. As mentioned above, the pan controller 121 is with the pan command processor 116 connected via a signal bus line 118. This signal bus 118 includes two signal buses 130, 131. The signal bus 131 provides the column coordinate value for the desired ■ Image origin to a comparison circuit 164. In this embodiment, on the signal bus 118 from the pan command processor 116 selects the desired image display origin rather than a pan direction specified. Of course, a pivot direction can be selected over a number of desired display images. Origins are indicated.

p _: The signal bus line 118 also includes the signal bus line 130, which contains the line value of the coordinate

|| ten address for the desired image origin to a comparison circuit 155 transmits. The synchronization

The signal line 119 from the raster controller 117 comprises three indicated signal lines: a horizontal sync ^; || synchronization signal line 138, a vertical synchronization signal line 133 and an image synchronization signal line 132. The bilusynrönisaiiorissignäHeiurig 132 indicates the beginning of a raster scan image. The vertical

> i synchronization signal line 133 indicates when the raster scan begins a new horizontal line. the A horizontal sync signal line 138 is pulsed by the raster controller 117 when information for

each pixel are required so that a CRT raster scan line can continue to be formatted.

A register 134 contains the column coordinate value of the image source address for the preceding one Raster image. The comparison circuit 164 compares the value stored in this register 134 with that of the signal line 131 obtained column coordinate value for the desired original address. The comparator 164 determines the absolute value of the difference between the two column coordinate values and outputs this to one Signal bus 142. In addition, it puts a signal on a line 141 which indicates whether the column coordinate value of the origin is moved left or right. The difference value on the signal collector 142 is transmitted to a minimum value sector 143, which contains the value arriving via the signal line 142 the maximum permissible horizontal (column) change between successive ones, stored in a register 144 Comparing raster images The minimum value selector 143 is used for limitation in this example the maximum horizontal pivoting movement from one raster image to another, so that is guaranteed that the enrollment control device 126 connects the enrollment zone 104 with the one for maintaining the pivoting zone 103 in the image memory 105 can update required speed.

The left or right signal on line 141 from comparator 164 goes to an adder / subtracter 165, which determines whether the output of the minimum selector 146 is from the previous

The value stored in the column acir register 134 should be added or subtracted from the display origin The result of this addition or subtraction is sent to a register 136 via a signal bus 139 directed to contain the map coordinate value of the display image origin for the next raster image The im Y / ert stored in register 136 is passed through signal bus 135 to modulo P counter 137 and closed containing the column coordinate value for the display image origin from the previous raster image Register 134 transferred. Register 134 takes the contents of register 136 upon an appropriate pulse on the image synchronization signal line 134, whereby the register 134 is caused to the contents of the To lock register 136, d. H. record and save. In addition, the image synchronization signal line is activated with pulse scanning 132 is connected to the modulo-P counter 137, whereby the counter 137 has the value

ίο the content of register 136, d. H. the column coordinate value for the one used in the next raster image Display origin is preset (modulo-P).

The modulo P counter 137, a component in a torus addressing formatter 250, is used to obtain the structure of the torus frame addressing for the image memory coordinate system. As mentioned above, the image memory 105 is intended to be addressable in a rectangular coordinate system with Q rows and P columns. This counter 137 is preset by the image synchronization signal line 132 to the column coordinate word for the display image origin of the next raster image in the image memory 105 (modulo-P). With each horizontal synchronization signal pulse on the line 138, this counter 137 is incremented or incremented, as a result of which the desired column coordinate value accessed by the image memory access blocking device 125 is brought up to date. Since the counter 137 is a modulo P counter, it runs back to zero when the value P is reached, ie the value corresponding to the number of columns in the image memory 105, thereby creating the wraparound feature in the horizontal (columns -)Direction. The output signal of this modulo-P counter 137 is made available to the image memory access control device 125 via a signal collecting line 147 as part of the signal collecting line 129 and forms the horizontal raster read-out address.

A circuit similar to that for the column coordinate border i..t for the row border feature of the Swivel control device 121 is provided. The signal bus 118 from the pan control processor 116 to the Pivoting control device 121 outputs the line value of the coordinate for the origin via a signal bus 130 of the display image to which the panning leads. This signal bus 130 ends in a comparison circuit 155. The comparison circuit 155 compares the desired coordinate value with the value stored in a register 153, that is the line value for the one in the previous raster image used display image origin. The absolute value of the difference between these two line values is calculated using a Signal bus 157 is made available to a minimum value selector 158. In addition, the comparator gives 155 on a signal line 156 to indicate whether the value pending on signal line 130 or the value in register 153 stored value is greater, d. H. it is determined whether the display origin is moving up or down.

The signal on line 156 is used to select the ones to be carried out in an adder / subtracter circuit 161 Surgery.

The minimum value selector 158 compares the absolute value difference to one coming from the comparator 155 Signal bus 157 with the register value stored in a register 160. Register 160 contains a maximum permissible change in the line origin coordinates between successive raster images, which limits the vertical slewing speed to a specified value. this is it urgent? Ability to limit pan speed to ensure pan zone »03 always contains sufficient image data surrounding the display zone 102. This register 160 transfers its value via a signal bus 159 to the minimum value selector. The output signal of the minimum value selector 158 is obtained from a signal bus 163. This value is put into the adding / subtracting circuit 161 is entered which is the column value for the coordinates of the display image origin in the image store 105 is calculated for the next raster image and makes it available on a signal bus 162. This The value is stored in a register 152. The output of the minimum value selector 158 on the Signal bus 163 is also available to the write-in control unit 126 via a signal bus 122 made.

The value in register 152 is used to preset (modulo-Q) a modulo-Q counter 150 when raster scan synchronization signal 133 indicates that modulo-Q counter 150 should be preset in this way at the start of a new raster image. This counter 150 is a modulo Q counter, it being assumed that Q lines are available in the image memory 105. The counter 150 is incremented or incremented by the vertical synchronization signal line 133 whenever the raster control device indicates that the next raster line is to be formatted. Since the counter is a modulo Q counter, it returns to the value zero when the value Q is exceeded, as a result of which a toroidal frame addressing takes place in the row direction in the case of the invention.

The output of counter 150, the vertical line component of the raster readout frame store address, is available on a signal line 148 and is transmitted to the image memory access control device via the signal bus line 129 125 made available. As mentioned earlier, the signal bus includes 129 also the horizontal (column) coordinate value for the pixel to be addressed. Therefore stand on the signal bus 129 image memory addresses are available which correspond to the raster scan synchronization signals access the image memory 105 on the signal bus 119 via the image memory control device 125 in a toroidal manner. Since these column and row addresses are on buses 147, 148 with the video sample clock signal

b5 are synchronized, the torus address formatter 250 directly provides image memory addresses for the raster scan in a toroidal shape.

In addition, the signal line 122 cmn Einsshreibsieuergcrai 126 contains the line coordinate value for the display image origin of the previous raster image on a signal bus 154, the column

coordinate value for the display image origin of the previous raster image on a signal bus 140, the column coordinate value change of the display origin on a signal bus 146, and the Change of the line coordinate value for the display image origin on a signal bus Ϊ63. Upper These signal bus lines, which belong to the signal bus line 122, are available to the write control device 126 the address of the image memory for the display image used in the previous raster scan image, and s also the change in the display image origin from the previous raster scan image /.ur Disposal. This information is sufficient for the enrollment control device 126 to establish the enrollment zone 104 in the To determine image memory 105, which must be rewritten to maintain the desired pan zone 103.

If the desired display image origin address is too far from signal bus 118 to be identified by ι ο To achieve a pan in a raster image, the pan control device 121 generates a series of vosi Display image origin addresses, one per raster image. As a result, a seamless Panning image on the display screen or CRT 112 at the maximum permitted by the panning control unit Speed takes place

An electrical block diagram of one embodiment of the write control device 126 is shown in FIG. 5, in addition to the signals via the signal bus lines 140, 141, 146, 154, 156 and 163 from the swivel control device 121, the write control device 126 receives a sequence of clock pulses generated in a clock generator 270 via a signal line 170. In this embodiment, the clock generator 270 should generate the clock pulses at least at such a frequency that a sufficient number of pulses are available to update the maximum number of columns and rows when panning between successive raster images. The column coordinate value for the display image origin of the previous raster image, which is available via the signal bus 140, is processed by an adder 178. The adder 178 adds a write-in column shift constant to the value received on the signal line 140, which is stored in a register 176. This register 176 contains the appropriate number (I + J + K) for specifying the shift that is required from the column value of the display origin address within the image memory to the column coordinate value for the vertical line 104-V of the write limit 104. The sum signal from the adder 178, ie the column coordinate address of the vertical line of the write limit, is transmitted via a signal line 179 to a modulo P counter 260.

As mentioned above, the write controller 126 must have one column of image data in the write zone 104 for update each pan column and one line of image data for each pan line. The in F i g. 5 shown The embodiment of the write-in control device uses the clock pulses from a write-in clock generator 270 first to update the columns and then to update the rows of the writing zone 104. Alternative embodiments of the write controller 126 could also suitably change the lines Update before the columns or update the rows and columns at the same time.

A write clock signal line 170 is connected to two AND gates 171, 172. The AND gate 171 also receives an input from a signal line 261 which is at a Η value when the content of a counter 262 is not zero. The signal line 261 forms the output of an inverter 263, which the signal on the line 173 inverted. The signal line 173 carries a signal at the Η value when the counter 262 has a Has zero value. The counter 262 only has the value zero after the correct columns of the write-in zone 103 have been updated. It is important that the signal line 163 indicates whether the row or column part of the Pivot zone 103 is rewritten. When the column part of the pivot zone 103 is updated, so the signal on line i73 is low (low), thereby enabling the Write clock signal line 170 is connected to column clock signal line 174 via AND gate 171. On the other hand, when the signal line 173 is Η (high), it means that the counter 262 has reached the value zero, and the AND gate 172 couples the clock signal line 170 of the row clock signal line 175 through.

The signal bus 146 which shows the change in the column coordinate values of the origin between the the current raster scan and the previous raster scan image is used to preset a Counter 262. Each clock pulse on column clock signal line 174 decrements the contents of counter 262. so In addition, the column clock signal line 174 causes the contents of the modulo P counter 260 to increment or is decreased, depending on whether there is a signal on line 141 indicating the direction of change the column values of the display image origin is at an H or an L value. This counter 260 provides toroidal rim column addressing by ensuring that the column coordinate value is in the suitable addressing range for the image memory access control device 125 lies. The counts of this counter 260 are transmitted to a request formatter 186 over a signal line 181. After receiving the Column coordinate value for a column, which is used to maintain the desired pivot limit in the When image memory needs to be updated, formatter 186 generates the necessary signals, code or Command groups used by the special main processor 128 for accessing the required image data and forwards the results to a main interface module 206 via signal trunk 187. The formatter 186 tracks the location in the main processor image from which the data for the column to be updated is to be obtained. For this purpose, the formatter 106 also receives the pan direction signal from the line 141 and via a line 188 data from the line request formatter 204, which indicate the main picture vertical position from which line data are to be accessed. The main interface module 206 reformats the request as necessary to interface with to provide a signal bus 127 to the main processor 128 which provides the complete image information.

As noted above, the count of counter 262 is determined by the pulses on column clock signal line 174 continued to increase until the result is zero, removing the column clock signal pulses on line 174 via the

Signal line 173 will be blocked. When this is done, the columns of write zone 210 that must be updated to maintain the desired boundary of panning information on each side of the image display being rasterized had appropriate requirements formatted for main processor 128. At this point, line clock signal line 175 is due the influence of the signal line 173 on the AND gate 172 is activated

It should be noted that the main processor 128 does not have to provide the requested column of image data in synchronism with the requests. The main interface module 206 can store in a built-in memory a list of image requests for which the main memory 128 has not yet acquired image data, together with a list of the corresponding rows and columns for rewriting in the image memory

ίο 105 preserve. If the requested data is eventually fed to the main interface module 206, it can be stored in the image memory 105 , although additional data requests are received at the same time. The main interface module 206 coordinates the image data from the main processor 128 with the corresponding zone in the image memory 105 to be updated.
A circuit similar to that for updating the columns of the pan zone is also provided for updating the pan zone 103 above and below the display zone 102 . A counter 264 is triggered over signal bus 163 to record the change in the vertical direction (ie, change in line coordinate values) between the display image origin in the previous raster image and the display image origin in the current raster image. An adder 196 adds the line value of the coordinates for the display image origin address in the previous raster image, obtained from the signal bus 154, to the content of a write line shift register 194 and stores the result via a signal line 197 in a modulo Q counter 265. The register 194 contains a constant value (L + M + N) which indicates the line shift compared to the line coordinate value of the previous display image origin in order to obtain the line coordinate value for the horizontal line forming the writing limit 104,
each clock pulse received on row clock signal line 175 decrements the value of counter 264.

In addition, clock pulses on the row clock signal line 175 increase or decrease the modulo Q counter 265, depending on the direction of change of the display image origin values according to the signal on the signal line 156. If a zero result is obtained in the counter 264 , the pan zone is 103 Fully updated in both horizontal and vertical directions. Modulo Q counter 265 performs toroidal bezel line addressing, ensuring that the line coordinate values transmitted to line request formatter 204 over signal bus 198 are in the correct addressing range for image memory. The lines request formatter 204 passes to the input of the Zeilenkoordiantenwerts for the desired row in the in the image memory 105 to be updated Einschreibzone 210 an appropriately formatted request via a signal bus 205 to the host interface module 206. The host interface module 206 performs a Neuformatisierung the requirement for additional image information in the for the main processor 128 required form and forwards the request over the signal trunk 127 to the main processor 128.

In addition to its function of requesting data from the main processor 128 , the main interface module 206 also reformats the image data (received from the main processor 128 due to previous requests from the columns 186 or rows 204 request formatters via the signal bus 127) into an image memory address and corresponding image data, which are suitably formatted for processing by the image store access controller 125. The image memory address is placed on bus 123 and the appropriate new image data required to maintain the desired pan limit is placed on bus 124 .
Other methods of controlling the pan speed in relation to the speed at which additional image information can be obtained from the main processor can be used within the scope of the present invention. For example, instead of specifying a maximum horizontal and vertical change in the display image origin between the raster images, a more complex algorithm can be used in which the dynamic availability of image data from the main processor is taken into account and the actual border still remains around the display zone

so F i g. 6 summarizes an alternate embodiment for determining the maximum allowable horizontal and vertical changes in display image origin between raster images. It should be noted that a speed at which panning occurs is essentially determined by a series of display image origin addresses, one for each raster image. As mentioned above, the embodiment of the swivel controller 121 as shown in FIG. 4 represents a relatively simple and uncomplicated way of ensuring that the image data necessary for each raster image are available in the image memory in the course of the panning operation. This was done by storing a maximum permissible change in the column coordinate values between the display origin coordinate addresses for the subsequent raster images in register 144. The corresponding maximum allowable change in the display origin line coordinate values between successive raster images was stored in register 160. It was essential that these registers limit the horizontal and vertical components of the pan speed or pan size to a value that would match the availability and response speed from the main processor 128.

Such a method of limiting the slewing speed or rate makes certain assumptions regarding the main processor 128 . Such a scheme is based on the assumption that the main processor has a uniform or precisely predeterminable response time for supplying or generating the requested image data. Such a pan speed limitation can be an undesirable limitation because if the pan zone 103 contains all of the image data required for the entire pan operation, there is no need to limit the pan speed due to the limitations of the main process.

sors 128 is present. In other words, a panning operation in which the display arm is only one a short distance could be carried out at a slewing speed that varies according to the Solange sets the desired visual effect of the panning for the person looking at the viewing screen 112 such as display zone 102 and focus zone 103 contain enough image data to perform the desired panning operation complete without access to the main processor 128 for additional image information can, the swing speed can be determined solely according to the maximum swing speed according to the desired tttti display effect

FIG. 6 generally shows a less restrictive method for determining the swivel speed, in which additional information is taken into account compared with the exemplary embodiment according to FIG. 4. At the beginning (method step 300) the desired last pan display origin is recorded. Alternatively, if the operator demands a certain pan speed and pan direction, such a request can be broken down into a series of desired display origin addresses, the series or sequence corresponding to the specified direction and pan speed.As soon as the desired last display origin address has been determined, the next step is ( Decision block 301) in determining whether the display zone 102 and the pan zone 103 in the image memory 105 contain enough image data to fully perform a panning operation to the desired aye origin address. If the main processor 128 is arranged not to respond immediately to requests or to respond at unpredictable speed to a request for image data updates, then panning zone 103 may not contain all of the image data requested by previous panning operations, but this can be accounted for if determined whether additional image data is needed to perform the panning operation in progress. In this regard, in the embodiments according to FIG. 3 to 6 the limits in FIG. 1 between the pivoting zone 103 and the writing zone 104 artificially. All parts of zones 103 and 104 are immediately available for pivoting, with the exception of the special parts of the enrollment zone (e.g. those near lines 104-V and 104- HJ, which are currently being updated. 2s

If no additional image data is required to perform the panning operation, as in Given process block 302, a pan speed can be calculated which is rapid but visual creates a pleasant panning effect on the screen. It is entirely possible that the panning speed becomes so high that the CRT operator performs the panning operation as a sequence of concrete image jumps sees for each raster image, an effect which is usually undesirable as a smoother, i.e. H. slower ones Slewing speed is more familiar to the CRT operator

On the other hand, when additional image data is required to complete the desired panning operation are, it is determined (decision block 303) whether the main processor for additional requests Image data is available Since the invention does not rely on the use of a special main processor the decision to be made at this point is a function of the main processor used. For example, the main processor can provide a precisely predictable response speed to a Have image data request. Conversely, the speed at which the main processor 128 can increase to a responds to a given image requirement, is difficult to predict due to the nature of the requirement, due to other processing functions being performed by the main processor other, higher priority requests being processed by the main processor and a variety of other factors. In addition, the main processor can handle a variety of image data requests summarize to create or access the desired image data more effectively.

If the main processor is available for additional image data requests, then how through Processing block 304, as shown, calculates a pan speed which is based on the image data acquisition speed the main processor 128 is tuned fis will be remembered that the main processor Image data need not deliver in exact synchronization with the request. This is because this is unnecessary since the pan zone 103 provides a safety area for image data that is included in the course of the pan operation Advantage can be provided, making the pivoting operation smoothly up to the highest average speed at which the main processor 128 image data can be performed can procure. This point is very important as many types of current main processors are much closer to 10 Write lines or lines in one batch after a waiting time of 170 ms (10 frame or image times) as can deliver a write line or line every 17 ms. One reason for this is that the output of the Image data may require access to a disk storage device that requires data transfer can run quickly but only after a relatively long dead time. In grid form, 10 lines can be entered with three bits per pixel require 15,000 bits of data. Typical disks can process this amount of data in 2 ms after a initial waiting time of perhaps 100 ms.

When the main processor is not available to process additional image requests it is determined (processing block 305) when the host system is available for such processing Could be available. Thereafter, as indicated in process block 306, a pan speed is established calculates which is slow enough so that additional image data is not required until the Main processor 128 can provide such additional data. If not exactly determined When the main processor 128 can create such additional image data, it can even at Starting at a low pan speed, it will be necessary to stop the pan operation in order to allow the To give the main processor the opportunity to comply.

After the optimum swivel speed has been determined, the swivel control device 121 is set (Processing block 307) to limit the pan speed to the determined speed. In the example! according to FIG. 4 registers 144 and 160 can be appropriately set so that the slewing speed does not exceed the desired speed. Although the execution examples

games have been described using a circuit structure of the digital logic, it is clear that a suitable Combination of circuit and program (hardware and software) the corresponding results accordingly of the invention results.

F i g. 7A to 11 show an alternative embodiment for the inventive toroidal pivoting ^

system. In this embodiment, the image memory 15 (corresponding to the image memory 105 of the '

Embodiment according to FIG. 1 to 6) erased and re-inscribed in "right-angled" strips of the -

Width W _s . The erasing and writing of each stripe is carried out by the panning control circuit 16/4 and 16β as shown in FIGS. 9 and 10 depending on a reduction in the size of the remaining image memory r- ^

andes triggered in the pivoting direction If this remaining margin has a predetermined height or width, ϊ

ίο falls below the same value (typically equal to the strip width W ₁ ), then the circuit 16A 16ß a ss

Strip Erase and Write Controller 17 (Fig. 11) insert new data into the appropriate memory strip. By doubling the circuit according to FIGS. 9,10 and 11 for each axis can be a combined vertical and horizontal toroidal pivoting is realized with suitable strip-wise writing of the image memory will.

5 The conditions under which the strip inscription takes place are shown in FIGS. 7A to 8E. To facilitate the explanation, FIGS. 7A to 7D show the panning in the vertical direction only. In this example, the image memory 15 is H _n , = 96 lines high and W _n , = 112 columns wide. The CRT display is defined by a "window" or display area 18 of the memory 15 having a height of Hd- 48 and a width of Wd = 64 generated Of course, these values only serve to simplify the description. In an actual raster display frame buffer, the "window" may typically be 312 lines high and 416 columns wide, and;.

the total memory size can be 360 χ 464, for example. λ

In the example according to FIG. 7A, at the start time T = 0, the origin of the window 18 is at f-

x = 16, y = 20. The scanning speed shown is one line (ie + y) per CRT image or frame in ^;

Upward direction. The memory 15 has an edge 19 of data surrounding the window 18. In the + y direction of the pivoting movement, the width W _{b of} this edge 19 is "over" the window 18 at T = 0 (96-68) = 28 data lines. The width of the edge 19 "under" the window 18 opposite to the direction of the pivoting movement is 20 lines. In this illustrated example, H _n , = Ha + 3W ₅ and W _n , = Wd + 3 W _s , where both Hd and Wd are multiples of Wi.

In the example according to FIGS. 7A to 7D, the erasing and writing of a memory strip 20 takes place when the width Wj, of the adjacent image data in the edge area 19 in the direction of the scan (including the data available through the toroidal border) is less than 16 lines At + ypro As shown in the panning speed shown, this condition occurs at time T = 12, where each unit of time T corresponds to a CRT frame. This condition (shown in Fig. 7) is detected by the panning control circuit 16B (Fig. 10) which causes the control unit 17 (FIG. 11) to delete and write new data in the strip 20 indicated by hatching in FIG. 7B. The height of this strip 20 is Wj = 16 lines. It is written with image data which are adjacent to the image section at the upper edge of the memory 15 and is available when the window continues an "up" pivot with a toroidal bypassing to the "bottom" of the memory 15 Edge 19 remains directly below the window 18, which has a width of 16 lines and contains unmodified image data. This zone ■

is available for immediate use in the event that the pan direction is to be reversed. :

In the embodiment according to FIGS. 7A-7D, each rewritten memory strip becomes the

Width W ₁ = 16 rewritten within 16 frame or image times. Therefore, the strip 20 is to the '"-.

Time T = 28 (FIG. 7C) is completely described with data which represent the part of the image adjacent to the upper edge of the memory 15. Therefore, the strip 20 is now available for use as part of the window 18 when this window is pivoted upwardly in a toroidal manner over the upper (y = 96) edge of the memory 15. This is shown in FIG. 7D for the time T = 32. Data for the upper section 18a of the window 18 is now accessed from the strip 20, which is deleted at the time T = 12 and rewritten during the interval T = 12 to T = 28 has been

A further panning in the + y direction is made possible by writing in the next following strip 20 'which was deleted at time T = 28 (FIG. 7C). At this time, the available margin width in the panning direction was 16 lines. This condition triggered the writing in the strip 20 ', the writing being terminated at time T = (28 + 16) = 44.

The F i g. 7A to 7D show a toroidal addressing of the memory 15 both for the input of new data

into strips 20, 20 'etc. as well as to access window 18 for the CRT display. At time T = 32 % (FIG. 7D), the origin of window 18 is, for example, χ = 16, y = 52. The address of the upper left "corner" i *

of the window 18 is therefore obtained by adding the height Hd = 48 of the window 18 to the original value of the y-axis § (y = 52), this addition being modulo 96 (ie modulo of the height H _n , = 96 of the image memory 15), which to an i |

upper edge coordinate of (52 + 48 = 100) - 96 = 4 leads. In other words, the upper edge of window ft section 18a is at y = 4. Similar toroidal addressing is used with regard to the image memory input |;

new data used for strips 20 and 20 ' U

Two-dimensional toroidal swivel around. ¹ stripe writing operations of the image memory 15 are in the ', ":'

F i g. 8A through 8E. The dimensions of the memory 15 and window 18 'are the same as those of Figs.

F i g. 7A-7D. Now, however, the horizontal swivel speed or swivel rate is' + 2x (ie two f |

Columns) per CRT frame or image, and the vertical speed is + y (i.e. one line) per frame j |

or picture. In this representation, a strip of width Wi is displayed within 8 frame times or image times || i

enrolled. At the start time T = 0 (FIG. 8A) the window origin is χ = 20, y = 20. p

At time T = 6 (FIG. 8B) the edge 19 is to the right of the window 18 'in the horizontal pivoting direction ϊ |

equal to 16 columns. At this point in time, a swivel control device similar to that of FIG. 10 releases the | i

12th

Deletion and rewriting of a vertical strip 20A of width W _s = 16 columns. This strip 20/4 is separated from the left edge of the window 18 'by an invariable portion of the edge 19 which is also 16 columns wide. This section is available for immediate access in the event that the direction of the horizontal pivoting movement is reversed.

At time T = 12 (FIG. 8C) the window 18 'reaches the original height of y = 32, so that the available margin above the window 18' in the direction of the vertical pan is now 16 lines. At this time (. As in the case of the example shown in FIG 7B) triggers the pivot control circuit 16S erasing and rewriting in a horizontal strip 20ßder width W ₅ - from 16 lines.

As can be seen in FIG. 8C, the horizontal strip 20i) overlaps a section 20/4 'of the vertical strip 20/4 which is currently being rewritten. This condition is scanned via connections between the swivel control units for the associated vertical and horizontal axes and a suitable priority scheme is provided. Preferably, the last erase and write commands will be given priority over a write operation started earlier. Therefore, in the examples according to FIG. 8C the newly initiated erasure and writing in the horizontal stripe 20ß priority over previously initiated writing in the vertical stripe 20A In this case, at time T = 12, the deletion of the stripe 20ß also leads to the deletion of the zone 20/4 ', whereupon the area 20 / 4 'is considered to be part of the area 20ß for inscription purposes and the zone 20A' is excluded from the continued inscription of the vertical strip 20/4.

A toroidal addressing in the vertical axis is shown in FIG. 8D shows where at time T = 16 the image 18 'is guided around the memory 15 and contains a zone 18a' which runs inward from the “left” edge of the memory 15. The horizontal coordinate of the right edge of this window section 18a ' is obtained by modulo W _n , = 112 addition. Therefore, at the time T = 16, the horizontal original position of the window 18 ' χ = 52, so that the right edge of the strip 18a' is given by χ = (52 + 64 = 116) - 112 = 4. A similar toroidal addressing is used for Data entry is used in vertical stripes 20/4 and the adjacent vertical stripes 2OC, the erasure and writing of which started at T = 14 and continues at T = 16. At this time T = 16, the strip 20 β is still further written, and the overlapping zone 2OC is excluded from the strip 205, but included in the later started writing of the vertical strip 2OC

Full toroidal or modulo addressing of memory 15 in both the vertical and horizontal axes is shown in FIG. 8E at time T = 32. The origin of the window 18 'is now at χ = 84, y = 52. The coordinates of the diagonally opposite corner of the window 18' are ^Modulo-Add: tion is found as follows:

χ = (84 + 64 = 148) - 112 = 36 and y = (52 + 48 = 100) - 96 = 4.

At the time T = 32, both a horizontal strip 20DaIs and a vertical strip 20 £ are written. The writing of the strip £ 20 ″ began at a later point in time (at T = 30), so that it dominates in the overlap zone 20E '.

The swivel control device 16Λ, 16ß in FIGS. 9 and 10 and the strip erasing and writing control device 17 11 serve to carry out the vertical toroidal pivoting according to FIGS. 7A-7D. A duplicated group of such control devices is advantageously used for the horizontal axis the toroidal two-axis pivoting according to the Fi g. 8A-8E to be realized. Suitable compounds serve to control the writing priority in the strip overlap zones 20Λ ', 20C' etc.

Reference is made to FIG. 9 below. The pivot control circuit 16/4 advantageously receives as input signals a first digital signal R _nc w representing a new pivot speed and a second digital signal d _cw representing a new pivot direction. These signals can be received from a pan control processor analogous to that indicated at 116 in FIG. 3 designated processor can be delivered. The values /? _nc »and d _ne w are stored in the corresponding registers 22 and 23 when a“ new speed or direction available ”pulse RNP occurs, ie is delivered simultaneously on a line 24.

Circuit 16/4 makes certain determinations or determinations, the first of which is whether

ciüc SCiiw'cfik- Oucf Strcifcncinschrcibopcrätiön ucfZcii gcfäuc äuiäüit öucr fiiCnu WcPiH lCciiic uicScf v / pcfäüG-NEN expires, then the circuit 16Λ dissolves immediately by a panning operation of that a new pan speed signal R, and a direction signal d on the corresponding lines 25 and 26, where will. As will be described below, the circuit 16.8 (Fig. 10) uses the speed and direction signals R and d at the beginning of each CRT frame to obtain the original coordinates of the window 18 to be displayed on the screen for that frame Circuit 165 also determines whether a new strip 20 in image memory 15 needs to be erased and rewritten. If this is the case, the direction signal rf on the line 26 is used by the control unit 17 (FIG. 11) to support the determination of the original coordinates of the new strip to be inscribed.

In order to determine whether a pivoting movement is currently in progress, the content of a latch circuit 27ω (FIG. 9), which stores the current speed signal R , is compared with zero in a comparator 28. If there is currently no pivoting movement taking place, R = 0 and a Η signal is applied as the first input to an AND gate 29, which is activated by the RNP pulse on line 24.

If there is no stripe writing operation, the content S of a register 30 (FIG. 11) is zero. Accordingly, there is a Η signal on a line 30a to the AND gate 29, which represents this state S = O. In this condition (R = 0.5 = 0), which indicates that neither a panning operation nor a strip write operation is in progress expires, the AND gate 29 develops an output signal that, after a short delay, the insertion of a new swing speed signal R in the interlocking switch

device 27 and a new direction signal d in a latch circuit 31 causes. The resulting presence of these values R and c / on lines 25 and 26 then triggers the corresponding pivoting operation. The delay enables appropriate comparisons to be made by circuit 16Λ prior to input of the values R and d into the latching circuits 27 and 31. The delay is carried out in part by a circuit 24a which delays the RNP pulse and puts a delayed RNP 'pulse on a line 24a'. The output signal of the AND gate 29 triggers a monostable multivibrator 32, the output 32 'of which carries a signal at a Η value somewhat longer than the time delay of the circuit 24a. Accordingly, a short time after the AND gate 29 develops an H output signal , a corresponding H-output Si gnal developed by an AND gate 33 on a line 33 '. This signal enables the latch circuits 27 and 31 to be loaded via corresponding OR gates 34 and 35. The load or input pulse from the OR gate 35 causes the new direction signal d " _e " to be entered into the latch circuit 31 from the register 23.

The swing speed value R which will dig into the locking circuit 27 is thereby

determines that it is first determined whether the new speed R " _e w is equal to or less than a certain maximum swivel _{speed R max} , the latter being stored in a register 36. This value Rmax is suitably selected with reference to the properties of the main processor 128, to ensure that the strip inscription is completed before the window 18 pivots "in" the newly inscribed strip

This determination takes place in a circuit 37, the output signal of which is at a Η value when R "ew> Rmax. In this case, a gate 38 is activated in order to apply the maximum swivel speed value R _m , x to a gate 39. If, on the other hand, /? "" ■ is equal to or less than the maximum acceptable value, the resulting L value at the output of the comparator 37 is inverted by a circuit 40, whereby a gate 4t is driven which sends the value R _new to the gate 39 applies If the AND gate 33 has an H value puts on the line 33 ', the gate 39 is activated via an OR gate 42. As a result of this, the appropriate value Rnew or R _{max is} entered into the locking circuit 27 and given to the line 25 as the new Schwenkgeschwindig keitswert R.

If a panning operation is in progress when the new speed and direction signals are received, the AND gate 29 is not activated and the locking operation described above takes place Instead, a Η signal appears on a line 28 'indicating that R Φ 0. In this case, the circuit 16Λ determines whether the pan direction used in the current panning operation is the same as or different from the new direction according to the </ _nw signal is For this purpose, the # 0 signal is fed to an AND gate 44 which is activated by the RNP pulse. The current direction signal d is compared with the new direction _signal d ew in a comparator 45. When the direction is the same (d “ _C w = d), a third input signal is applied to the AND gate 44 at a Η value Load signal via a line 47 'and the OR gates 34,35 for the latch circuits 27 and 31. This leads to a new speed value Rnew or Λ ™ ,, which is input into the interlock circuit 27. The value of d " _e w = d" is entered into the latch circuit 231 entered again. Panning continues in the same direction at a new speed

If the new pivoting direction deviates from the current pivoting direction, the comparator 45 delivers a Η signal on a line 45 'which indicates this condition (ά _ηίν ψά). As a result, AND gate 48 develops a high output on line 48 'which halts the panning operation in progress by inputting the value "zero" to latch 27 through gate 51. This will make the Value R = 0, which represents a swivel speed of zero, applied to the line 27, whereby the current swivel operation is effectively terminated.

It is possible that the writing in a strip of the memory 15 is currently in progress when the new, oppositely directed panning signal d " _C w is received. In this case, the circuit 16.A waits after the current panning operation has been stopped until the writing in the strip has ended the swivel operation is triggered in the new, opposite direction. To this end, the Signal on line 48 'a flip-flop 52 in the "1" state. The flip-flop 52 remains in this state as long as until the 'current strip writing operation has ended. Then the Signa! on line 30a (the State 5 = 0) to the Η state and causes the flip-flop 52 to be reset to the "zero" state. The resulting output signal on a line 52 'causes a trigger circuit 53 to delay th pulse on the line 47 ', whereby the new value Rnew or Am «is superimposed in the interlocking circuit 27 and the new direction signal d _ne w is superimposed in the interlocking circuit 31. The queuing of these values J? and d on lines 25 and 26 initiates the panning operation in the new reverse direction. If no stripe writing is in progress while the reverse directional condition is detected, flip-flop 52 is set to the "zero" state immediately after the pulse on line 48 'goes low. This results in an immediate triggering of the panning operation in the new reverse direction. In this case (S = 0 when the condition is established in the opposite direction), precautions are taken to ensure that the next new value of Rnew or d _ncK does not occur until the output signal from the trigger circuit 53 first loads the latches 27 and 31 has caused

The circuit 16B according to FIG. 10 (eg. The device 125 in F i g. 3) returns to the beginning of each CRT image or frame in the image memory access control unit, the vertical origin coordinate yo of the window 18, in this image or frame on the CRT that for Display should be brought. A corresponding circuit 16ß, which is assigned to the horizontal pivoting operation, provides the screen window original coordinates in a similar manner.

dinate yo for the horizontal axis. The circuit 16Ö also determines whether a new, horizontal strip 20 should be deleted and rewritten. If this is the case, it develops a Η signal on a line 30b, which sets the contents of register 30 (Fig. 11) to 5 = 1, thereby performing the strip erase and write operation is triggered.

The operation of circuit 16B is synchronized with the CRT frame rate by receiving the frame signal F from a raster control device (e.g., device 117 shown in FIG. 3). This image signal F sets a flip-flop 55 to the “1” state, as a result of which a series of operations is triggered which are carried out sequentially according to the state of a counter 56. The counter 56 is initially set to zero and is then incremented by the high speed clock pulses which are sent out via an AND gate 57 to the counter. The latter is activated by the "1" output of the flip-flop 55. The first clock pulse sets the counter content to "1", which produces an output signal on line 56-1 which resets a flip-flop 58 to "0". This switches off a gate 59, which prevents the screen window original coordinate yo, die is currently stored in a register 60 is transferred to the image storage cycle controller (IMAC) 125. During the following operations of the circuit 16S, this original address yo is updated in accordance with the current pan speed R and the direction signals d. When the counter 56 reaches a count of "7", the output signal on the line 56-7 sets the flip-flop 58 to the "1" state. This enables the gate 59 to transmit the new original coordinate yo from the register 60 to the address bus (e.g. to bus 129 in FIG. 3) of the IMAC. This coordinate yo and the value xo from the horizontal pan controller are then appropriately used to access the IMAC 125 and generate the desired window display on the CRT screen. The frequency of the clock pulses supplied to the counter 56 is very high compared to the video sampling frequency, so that the update of the original address oo is carried out quickly at the beginning of each CRT picture or frame.

The available width Wt, of the margin 19 in the + y-pivoting direction is shown by the content of a register 61 aiige. The content of this register 61 is updated each time a new strip is rewritten by the control device 17. First, the contents of register 30 are interrogated to see if 5 = 2, indicating that a strip has been written but the margin width register 61 has not yet been updated. This determination is made by an AND gate 62, to which the "1" output signal of the counter 56 on the line 56-1 and the S = 2 signal on a line 30c are fed as input signals. When S = 2 is true, AND gate 62 develops a high output, causing gate 63 to transfer the current contents Wb of register 61 to adder / subtract circuit 64. In this circuit 64, the strip width W _{5 is added} to the preceding edge width Wt or subtracted from the latter, which depends on whether the panning is carried out in the + y or -y direction according to the panning direction signal d . The addition (or subtraction) is modulo H _n,. The sum is temporarily stored in a register 65. The content of the register 65 therefore represents the new edge width W _b , which is now available for the + y panning as a result of the completion of the writing in a new strip of the image memory

At the next clock pulse, when the counter 56 gives an output signal on a line 56-2, an AND gate 66 causes a gate 67 to load this new value Wb from the register 65 into the register 61. At the next clock pulse, when the counter 56 puts an output signal on the line 56-3, an AND gate 68 supplies a signal via a line 30c / to the register 30 which sets the value of S to zero. If not earlier, the condition 5 = 0 confirms that no strip inscription is currently taking place.

When 5 is set to zero, the register 61 contains the new value Wb which indicates the remaining available margin width in the + y panning direction including that through the newly written strip during an ongoing panning movement vertically upwards. The available edge width VVV in the - y pivoting direction corresponds to the value (H _n , -H _d - W _b ). This value WV is obtained by a subtraction circuit 61Λ which subtracts the value VVj from the register 61 from the constant value (H _n , -HJ) which represents the entire vertical width of the edge 19 in the image memory 15.

Next, the panning speed signal R, which indicates the number of lines swept by the window 18 in each CRT picture or frame, is compared with the available margin width IV * or WV in the panning direction, indicated by the direction signal d. This comparison is performed by a circuit 69 which supplies the value Wb via a gate 70a receives when the direction signal d indicating a + y-pivot and the value ViV through a gate 70b receives when the signal d is a -y pivot directional Obergurig indicative The comparator 69 a Η signal to an AND gate 71 when a sufficiently wide margin is available to perform the current panning operation (ie, when R <Wb or R < VVV). The AND gate 71 is activated when the counter 56 develops an H output signal on a line 56-4. If at this point in time there is enough margin space to move the window, a flip-flop 72 is set to the "1" state and inputs A high output signal on a line 72 '.

The original vertical coordinate yo of the window 18 to be displayed on the CRT screen is now updated in accordance with the swivel speed signal R , and the value Wb indicating the remaining edge width is reduced accordingly of the panning speed signal R is to be moved for each picture or frame, added to or subtracted from the original value yo just reproduced. This is done in an addition / subtraction circuit 73. The panning direction signal d present on line 26 is used to set the type of operation (addition or subtraction) Signal d the circuit 72 such that the value R is added to the previous coordinate value yo.

When the counter 56 advances to "5", an AND gate 74 activates a gate 75 in such a way that it applies the new original value y ₀ + R to a buffer register 76. When the counter 56 advances to "6", activates

an AND gate 77 a gate 78 in such a way that the latter transfers this new original value from the register 76 into the Enter register 60 instead of the previous value. In the next step of the counter 56, a Η signal is set on the Line 56-7 sets the flip-flop 58 to the "1" state, whereby the gate 59 is activated in such a way that it does this new screen window original value jo from register 60 for the associated image memory access control device As a result, the window 18 is accessed during the current CRT image or frame from the new position in the image memory 105, defined by this new vertical original address yo and a new horizontal original address X ₀ supplied by a corresponding control device for horizontal pan . In order to update the register 61 defining the remaining edge width, the swivel stroke is in the running

ίο image or frame subtracted from the previous remaining edge width Wb according to the signal R

or added to this, depending on whether the panning is up or down This is done in £;

an addition S '/ subtraction circuit 79, which the value W _b via a signal from the output signal of the AND gate 74 |,

activated gate 80 is supplied. If the pivoting movement is upwards, the direction signal d f ■

the circuit 79 to subtraction, and the resulting difference (Wb-R) is in a register 81 between-,.

stored If the swivel movement is directed downwards, the sum Wb + R is formed and in , &

Register 81 saved When counter 56 reaches count "6", the output signal from ■ is activated >

the AND gate 77 a gate 82, which thereupon this new value W _b from the register 81 into the remaining U ^

Enters register 61 indicating the width of the margin instead of the previous value < ■ " Finally, it is determined whether an additional strip in the image memory 15 is to be erased and written

got to. This is done by comparing the new residual margin width value Wb from the register 61 (or the value £ | Wb ' from the subtraction circuit 61A) with the stripe width W _s in a comparator circuit 83. If the ^ C pivoting movement is in the + y direction and Wb < W _s, or if the pivoting movement comparable downward * runs \ and Wi, '<W _5, indicating must be cleared that no new edge strips and enrolled so \ Ί is an aND gate 84 is activated when the counter 56 to " 7 «advances The resulting H output signal of the ^

AND gate 84 on line 306 resets the content of register 30 to S = 1, whereby a - 'strip erase and write operation from control device 17 is triggered. When counter 56 reaches its maximum count of "8", the resulting signal on line 56-8 resets counter 56 and also resets flip-flops 55 and 72 to zero, thereby disabling the operation of circuit 16 /? so [completed until the next CRT image signal appears

In the following, reference is made to FIG. 11 referred to. The control unit 17 conducts the erasing and writing operations; tion of a horizontal stripe in the image memory 15 when the content of the register 30 is set to 5-1. ':' A corresponding control device (not shown) controls the erasing and writing of vertical strips in the memory 15, as far as this is required by horizontal scanning. If S - 1, an H output signal i on a line 3Oe sets a flip-flop 85 in the 1 «state This triggers a stripe erase operation by a flip-flop 86 is set to the "1" state via a trigger circuit 85 '. A circuit 87 is thereby activated to erase the data present in the image memory 15 in a horizontal strip (e.g. strip 20 in FIG. 7B) of width W _1. The vertical source address of the V ₁ (for the + y-swivel) · just to delete horizontal strip is stored in a register 88 and, via a manifold 88 'to the erase control circuit 87th In the case of an upward panning, the control circuit 87 uses this Ur jump ^ address V ₅ from register 88; in the case of a downward panning (indicated by the direction of the signal d) , the circuit 87 obtains the appropriate strip origin address by modulo H _n , subtracting a constant (determined by the required width of the edge 19 in the -y direction and the width W _{5 of} the strip) .; '..; from the address supplied by register 88. The erase operation can include the entry of binary zeros into all storage locations in the strip of width W ₅ , the original address of which is supplied or calculated from

the content of register 88. ₍

When this deletion is complete, a Η signal is given on a line 87 ', which the flip-flop 86 in ■ / ■ ι

resets the "zero" state. This causes a signal via a trigger circuit 86 'and an AND gate £?

89 given, which sets a flip-flop 90 to the "1" state, whereby a "new data request" signal r j which is transmitted to the main processor 128 via a line 90 '. This will make the main pro V

so the processor is conditioned to deliver the new data for writing in the previously erased horizontal strip. The original address V _{5 of} this strip in the image memory 15 is also given to the main processor via the bus 88 ', as is the swivel direction signal d via the line 25. The original address of the strip with reference to the main image which is stored in the processor 128 is also supplied is produced. ■> /

Depending on these data request, strip origin address and pan direction signals; · the main processor 128 develops the correct data for writing in the horizontal strip and returns this to the control unit 17. The new data and the corresponding image memory addresses identify the information is from the Processor via a corresponding pair of busses 91 D, 91A to ■ .; ' given to an intermediate storage buffer 92 in control unit 17. A "data available" signal that simultaneously · from the processor 128 via a line 9t P and an AND gate 93, triggers the input of the new data and address information in the buffer 92.

When enough new data has been received, the buffer 92 issues a write command to the image memory access controller 125 over line 92W and simultaneously transfers the new stripe data and the corresponding image memory addresses to the IMAC over lines 92D and 92A. The IMAC 125 leads

b5 then carries out the appropriate writing operation of the strip in the image memory 15. Upon completion of this operation, an acknowledgment signal is sent from the IMAC 125 via a line 92 'to the buffer 92, as a result of which a "Schrcibbcendigungs" signal is generated on a line 92'. This signal activates an addition / subtraction circuit S3, which the original address V ₄ in the image memory 15 of the next horizontal strip

calculated, which is to be deleted and rewritten in the direction of the + ^ - swivel. To this end, the circuit 93 adds or subtracts the stripe width value W ₁ to or from the previous stripe origin address Ys from the register 88. An addition is made when the pan direction signal d indicates an upward scan and a subtraction is made in a downward scan. The calculation by the circuit 93 is modulo W _n ,, the width of the image memory.

After a slight delay via circuit 94, the newly processed strip origin address Y _{1 is} input from add / subtract circuit 93 via gate 95 into register 88 , where it is available for use the next time a strip erase and write operation is initiated will. The "write complete" signal also sets the contents of register 30 to the value S = 2 in order to terminate the erase and write operation.

Even if the register 88 tracks the respective origin Y _{s of} the horizontal strip 20 in the image memory 15, it is nevertheless necessary to enter the main processor 128 with the strip origin address within the "main image" stored or generated in the processor. This main image 96 is shown in FIG. 12 (corresponding to the example according to FIGS. 7A to 7D). When the CRT display is initially generated at time T = O (FIG. 7A), the portion 15 'of the main picture 96 contained in the picture memory 15 is located at an original address XmYm within the main picture. This initial original value in the vertical direction (Ym) is stored in a register 98 (Fig. I 1)

During a vertical upward panning, when the strip 20 (FIG. 8B) is to be written, the original address of the portion of the main picture containing the required strip data% can be calculated and entered into the main processor 128 through a circuit 98. As can be seen in FIG. 12, these data are obtained from a memory section 20Λ /, the original address of which is X _n ,, (Ym + Hm). The bottom area of the image memory 15 is entered in accordance with the strip 20 shown in FIG. 7B. That is, the data is entered into a portion of the image memory which has a vertical origin address Y = 0 (value stored in register 88)

If the upward panning is continued, the next strip 20 '(Figs. 7C and 7B) is obtained from a zone 2OW of the main picture 96 which has an original address X _m , (Y _m + H _m + W ₁ ) also becomes this value advantageously entered into the main processor 128 from the computing circuit 98 via a bus 98 '. If the pivoting movement is downward from the initial position shown in Fig. 7A, the data for the first strip to be rewritten is obtained from the zone 2OM "(Fig. 12) which has an original address Xm, (Ym-W ₅ ) . Generally the vertical original address Y ₁ ' in the main image 100 of the strip to be newly written is given by the following relationships:

Upward panning: Y ₅ ' = (Y _m + H _n ) + (N- 1) χ W _s (1)

Pan down: Y, ' - Y _n , + (N χ W ₅ ) (2)

where N is a signed integer and represents the cumulative number of stripes which have been rewritten during the vertical pan starting at T = 0, the image memory 15 being data located at the origin X _m , Ym with reference to the main image 96 contains.

The value N can be obtained from a counter 99 (FIG. 11) which is initially set to zero and is then increased or decreased by "1" each time a new strip is written in (when panning up or down). To this end, a "set up 1" signal on line 306 is used to increment counter 99 when the direction signal c / indicates an upsampling and to decrement counter 99 when it is downsampling. The content N of the counter 99, which is present on a line 99 ', is used by the arithmetic circuit 98 to calculate the new strip origin address in the main picture in accordance with equation (1) or (2). Which of the two equations is used depends on the direction of rotation indicated by the signal d.

If a horizontal panning has led to the deletion and rewriting of one or more vertical strips (e.g. strips 20A, 20C in FIGS. 8C and 8D) in memory 15, the corresponding horizontal shift in main image 96 must be made upon request new write data from the main processor 128 are taken into account. This calculation can also be carried out in circuit 98. The horizontal original coordinate X _{5 of} a new horizontal strip to be rewritten by the control device 17 can be calculated from the initial horizontal address X _m and the number N 'of the vertical stripes that have already been rewritten. This number N ' is obtained from a counter in the vertical stripe writing control device (not shown) which corresponds to the counter 99 in the horizontal stripe control device 17 according to FIG. The valid horizontal stripe coordinate X ₅ is then given by:

χ = Xm + (N 'χ W ₅ ).

This calculation is carried out by the circuit 98 and the result is given to the main processor 128 together with the vertical origin V via the bus 98 '.

In the event that during the writing in a horizontal strip 20, 20 ', etc., the erasing and writing operations of a vertical strip should start one after the other, it is necessary to define the overlap zone (e.g. 2OA', 2OC, 20 £ ' 8C-8E) from the horizontal stripe data which are rewritten into the image memory 15 under the control of the horizontal stripe controller 17. In the embodiment according to FIG. 11 this is done by giving the IMAC 125 the command "remove overlap" together with the horizontal original address of the zone to be removed. That

IMAC then does not introduce any data into the image memory for the horizontal strip 20, O ⁷ , which is rewritten for those locations whose horizontal addresses are between Xi (the origin of the vertical strip that has just been erased and written) and Xi + W, when panned to the right or horizontally Xi + W _n , - W, lie to the left when pivoting horizontally. The horizontal pivoting direction is indicated by a signal d _h from the vertical stripe write control device.

The removal command can be obtained from a flip-flop 100, which is indicated by a "Setz Sauf!" - Signa! appears on the line 30b at the beginning of each erase and write operation of the control device 17. If a vertical strip write operation is triggered during this write operation (for example with regard to the strip 20A in FIG. 8C), then the "set 5 to 1" signal used by the vertical stripe write control device (not shown) to reset the flip-flop 100 to the "NuU" state. The "zero" signal resulting on a line 100 'supplies the required command signal "remove overlap" to the IMAC 125. The vertical stripe- The original coordinate X _s (in memory 15) of the vertical stripe that has just been written in is obtained from the register in the vertical stripe write-in control device in accordance with the register 88 and applied to the IMAC 125 via a line 88a same as for a horizontal strip. Therefore, the writing of at most one vertical stripe starts during the writing of one horizontal stripe. However, appropriate logic can be used to prevent a "run" condition from occurring in the event that two (or more) strip scans are triggered on one axis during a single strip scan on the other axis.

Various modifications are possible within the scope of the inventive concept. For example, the image memory 15 or 105 can consist of a bit-addressed or linear memory instead of a memory that is directly addressed by x and y coordinates. In such a linear or bit-addressed memory, data can be stored in the "bottom" line (corresponding to y = - 0 of the memory IS in FIGS. 7A to 7D) from addresses zero to (Wm-1), the second Row can be accessed by the addresses W _n , to (2W _1n -I) and the n-th row by the values (n-1) W _m to (n W _m -1).

The pivot zones on opposite sides of the displayed window do not need the have the same width. For example, if it is established that the pivoting movement is in a certain direction (e.g. to the right or upwards) is continued for a certain minimum period of time, the edge or the pivot zone in this direction can be wider than the pivot edge in the opposite direction. this allows faster panning in the given direction than if both edges were the same Sides of the displayed window are provided.

The exemplary embodiments described above can also be implemented using a suitably programmed microprocessor instead of the precise circuit structure shown in the drawing.

For this purpose 10 sheets of drawings

Claims (12)

Patent claims: 1- Raster scanning video display system with a viewer, graphic data to be displayed storing image memory, which is able to store more graphic data than on the display device. can be displayed in time and which is accessible according to a special coordinate system with defined coordinate limits, a raster readout control arrangement assigned to a swivel control device, which reads out graphic image data from a part of the image memory in a raster scanning sequence and synchronously with the video clock of the viewing device, starting at an arbitrarily specified original address, monitors the reaching of a coordinate limit and continues the readout operation from the corresponding opposite limit and with a writing device for writing data into the image memory, characterized in that the writing device (126, 125) is so controlled by the swivel control device (121; 16a, t6b) that new data are entered in edge zones (104; 20) of the image memory (105; 15) outside the respective read-out zone (102; 18) Umse etching of coordinate addresses outside the defined coordinate limits in addresses within these limits in the manner of a toroidal circumnavigation is provided that the original address (101) of the readout zone in the image memory is freely selectable, the edge zones (104; 20) representing data, the data representing the readout zone (102; 18) surrounds in a toroidal shape and that an image memory access control arrangement (125) is in operative connection with the torus access device (250 - FIG. 4) in such a way that the data of the readout zone (102; 18) are accessible torus-like, starting at the freely selected original address, the data newly entered in the edge zones (104; 20) being available for inclusion in the output image data in the subsequent raster readout operation with a different original address and the readout operation being continued seamlessly during panning. 2. System according to claim 1, characterized in that the particular coordinate system is a right-angled Coordinate system is 3. System according to claim 1, characterized in that with the image memory access control device (125) and the writing device (126; 17) a swivel control device (121; 16A \ 6B) is in operative connection, which the image memory access control device (12S) a sequence of successively different original addresses supplies, whereupon the image memory access control device (125) successively accesses image data from corresponding other sections of the image memory (105; 15), and that the pivot control device (121; 16Λ, i6B) of the writing device (126; 17) those zones in the image memory (105; 15) denotes which are not read out by the image memory access control device (125) during the current raster readout operation. 4. System according to claim 3, characterized in that a timing device with the writing device (126; 17) and the swivel control device (121; 16Λ, 16B) is in operative connection and the writing device (126; 17) to terminate the data input in certain zones of the Image memory (150; 15) caused before these certain zones are included in that part of the image memory which is read out on the basis of an original address supplied later. 5. System according to claim 3 or 4, characterized in that the image memory (105; 15) has an edge zone (103; 19) which contains the information currently being accessed for reading out the image data by the readout control device Adjacent image storage section and contains image data that is a graphical continuation of the represent image data just read out, and that that zone (104; 20) of the image memory (105; 15) in which the data is input from the writing device (126; 17) from which to read out accessed section (102; 18) is separated by the edge zone (103; 20). 6. System according to one of claims 1 to 3, characterized in that the pivot control device (121; 16Λ, ViB) has an operator input device (110,111) for entering the desired original address or the desired direction of movement of the original address 7. System according to any one of claims 3 to 6, characterized in that the video display system (112, 117) a raster scan image or frame signal indicating the start of a CRT raster image repetition so developed and that the swivel device (121; tSA, \ 6B) is so designed that it develops a display memory original address for each picture or frame signal 8. System according to one of claims 3 to 7, characterized in that the pivoting device (121; 16Λ, i6B) is coupled to the writing device (126; 17) in such a way that it stores the image data stored in the image memory (105; 15) in a maintains unchanged the adjacent edge zone (103; 19) which has just been accessed by the image memory control device (125). 9. System according to one of claims 1 to 8, characterized in that the writing device (126; 17) coupled to a main processor (128) providing requested data for a portion of the image and requests data relating to parts of the overall image from the main processor (128) and into the Image memory (105; 15) enters. 10. System according to one of claims 1 to 9, characterized in that the pivot control device (121; 16-4, 16ß,) is designed so that it determines the rate of change of the (image memory control) device (125) used original addresses correspond to those speed limited with which the writing device (126; 17) can write data into the image memory (105; 15). 11. System according to any one of the preceding claims, characterized in that one with the Pivoting control device (16Λ, 16S ^ cooperating strip erasing and writing control device (17) provided is that determines when the width of the effective edge zone (19) in that of successive Source addresses identified pivot direction is smaller than a predetermined value, and that after deletes an adjacent strip (2OA 20B ^ dCs image memory (15) and additional pixel data from the Main processor (128) reads into this strip (20A, 20B) so that the strip (20A, 205,) continues and enlarges the adjacent edge zone (19), the strip erasing and writing operation also being feasible in the manner of a torus wrapping 12. System according to claim 11, characterized in that a separate, similar swivel control device (16/4, 16B) and a separate similar strip erasing write-in control device (17) are provided for the respective control of vertical and horizontal swiveling operations and that the separate vertical and horizontal Einschreibsteuergeräte are connected by a write-in blocking means for determining when one of the Einschreibsteuergeräte triggers an erase and write operation in a horizontal or vertical direction on a strip (2OA, 20B) of the partially an inscribed precisely in the other direction strips (2OA, 20B) overlaps, wherein the write-in blocking device prevents the write-in of the overlap zones by one of the write-in control devices