GB2173980A - Data display arrangements - Google Patents

Data display arrangements Download PDF

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Publication number
GB2173980A
GB2173980A GB08509853A GB8509853A GB2173980A GB 2173980 A GB2173980 A GB 2173980A GB 08509853 A GB08509853 A GB 08509853A GB 8509853 A GB8509853 A GB 8509853A GB 2173980 A GB2173980 A GB 2173980A
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United Kingdom
Prior art keywords
data
display
address
memory
processor means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
GB08509853A
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GB8509853D0 (en
Inventor
David Edward Penna
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Priority to GB08509853A priority Critical patent/GB2173980A/en
Publication of GB8509853D0 publication Critical patent/GB8509853D0/en
Priority to EP19860200620 priority patent/EP0198555A2/en
Priority to AU56171/86A priority patent/AU5617186A/en
Priority to JP61087225A priority patent/JPS61281331A/en
Publication of GB2173980A publication Critical patent/GB2173980A/en
Withdrawn legal-status Critical Current

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/34Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
    • G09G5/346Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory

Abstract

In a data display arrangement, a quantity of data stored in a display memory 5 is displayed as an entity on a CRT display device 1. The stored data is selected from a large background memory 4 under processor control 3 in response to user command signals 6, 7. The mode of selection involves the progressive comparison of each of a sequence of command signals with key data codes to transfer discrete portions of the data from the background memory to the display memory as determined by each command signal in conjunction with each preceding command signal. Figure 5 shows a flow chart of the selection mode. The arrangement is particularly useful with electronic dictionaries, wherein the sequence of command signals corresponds to the sequence of letters in a particular word. <IMAGE>

Description

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GB 2 173 980 A 1
SPECIFICATION
Data Display Arrangements
This invention relates to digitally operable data display arrangements for displaying as an entity on the screen of a CRT (cathode ray tube) or other raster scan display device, a quantity of data which is stored in a 5 display memory and is accessed repeatedly for its display in a recurrent cycle of scanning lines. The scanning lines, which can be produced with or without interlaced field scanning, are modulated at a given pixel or dot rate to produce a dot matrix display (e.g. a 320x250 resolution dot matrix colour display).
In a data display arrangement of the type set forth above, the stored data can comprise at least one information bit in respect of each of the pixels or dots which represent the data as produced on the screen of 10 the display device by the scanning action. Provided that the information bits for the successive dot rows of the display are read out from the display memory in the same lines of the scanning cycle in each field, the display is a static display.
This static display can be "scrolled" by modifying the read out operation every few fields such that information bits for the dot rows of the display are read out from the display memory in progressively 15 different scanning lines. The display can be cycled/wrapped-aroundjf dot rows "lost" at the top of the display are re-inserted at the bottom. Alternatively, the "lost" dot rows can be replaced by new dot rows by progressively changing the stored data in the display memory as the scrolling takes place. This produces a continuously up-dated display.
If, every few fields, the information bits for each dot row are read out in the preceding adjacent 20 scanning line rather than the scanning line in which they were currently being read out, then visually smooth scrolling occurs because the display is moved (up) only one scanning line every few fields. Visually smooth scrolling would also occur if the display is moved up only a few scanning lines every few fields. The scrolling can be made hard, i.e. less smooth such that it is visually "jerky", by moving up the display a significant number of scanning lines every few fields.
25 In a data display arrangement of the type set forth above display scrolling is a convenient way of searching through data, the rate at which the scrolling (smooth or hard) is effected being determined by how frequently the scanning lines for displaying the dot rows are changed. However, in applications where a large amount of data is to be accessed and displayed a portion at a time in order to find a particular item, it can become impracticable to search through the data by scrolling. Although it is apparent that scrolling can 30 be made to take place at any desired rate, the actual maximum rate that can be used in practice is limited by the ability of a userto read the data during scrolling.
It is an object of the present invention to provide an improved means for accessing and displaying a portion at a time a large amount of data.
According to the invention there is provided a data display arrangement of the type set forth above, 35 comprising a background memory for storing a large amount of data, a display memory for storing as said quantity of data a selected portion of the data read from the background memory, a display generatorfor producing video signals in accordance with the selected portion of the data in the display memory for driving the display device, and processor means and an associated user interface device for the selection for display of selected portions of the data in the background memory; which data display arrangement is 40 characterised in that said interface device has a plurality of switch means each of which is operable to produce a respective command signal, in that the processor means is operable, when the command signal produced by an operated switch means is the first signal in a sequence of command signals, to access data in the background memory at a starting address which is identified uniquely from the command signal, in that the processor means is then operable to read out and write into said display memory a selected portion 45 of the data from that starting address and respective further addresses, and in that the processor means is further operable, when the command signal produced by an operated switch means is not the first signal in a sequence of command signals, to access data in the background memory at a new starting address which is identified from that command signal in conjunction with the or each preceding command signal of the sequence, a new selected portion of the data from the new starting address and respective further 50 addresses being then read out and written into said display memory by said processor means.
The invention thus affords the advantage that it provides a means whereby, without a scrolling technique being used, a selected portion of the data from a much larger portion of data can be displayed selectively as an entity, with the selected portion being readily progressively altered in response to different combinations of sequentially produced command signals.
55 The invention was primarily evisaged as a practical means for searching through a dictionary list of words arranged in alphabetical order. Only a relatively few of the words of the list can be displayed at any one time, so that with the list containing several thousand words, which is likely, it becomes impracticable to search through the list using known scrolling techniques to find a particular word. The present invention enables the list to be accessed a portion at a time by the selective use of a sequence of command signals 60 which control the display of successive discrete portions of the list as sub-lists until a portion containing the required word is displayed.
In more general terms, the large amount of data which is stored in the background memory may be in the form of a list of items, and any portion of this list, which portion each time contains a same given
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number of items, can be read from the background memory by said processor means as a selected portion for display. Thus, any item of the list can be found and displayed without scrolling being necessary.
In carrying out the invention, particularly for the above-mentioned application thereof to a word list, the interface device is suitably a data entry keyboard device of known type, for instance a conventional ASCII 5 keyboard device, the keys of which constitute the switch means. The (ASCII) codes which are produced in response to key operation constitute said command signals. The use of such a keyboard device thus provides a simple means of producing a sequence of "select" command signals.
In the case where the list of items is textual, the data in the background memory can be in the form of multi-bit codes which represent respective text (alpha-numeric) characters. When a selected portion of the 10 list is read from the background memory by the processor means, the latter writes corresponding to data into the display memory as dot patterns for the characters concerned, at least one information bit being stored for each dot of each dot pattern.
In a data display arrangement in accordance with the invention the processor means may be further operable to provide also a scrolling function in response to "scroll" command signals from a second 15 interface device. Although such a scrolling function would in practice normally be used only for local scrolling relative to an initially displayed selected portion, it could in principle be used to scroll through all the data in the background memory.
The second interface device is suitably a graphics tablet the pen of which provides successive indexing "scroll" command signal in response to vertical movement (up or down) of the pen of the graphics tablet. 20 Preferably, both for the selection and display of discrete selected portions of data in response to
"select" command signal and for the selection and display of modified selected portions of data by scrolling in response to "scroll" command signals, the processor means is arranged to redefine the entire contents of the display memory for each different display.
In orderto scroll the display a short distance, the data in the display memory could be re-located or 25 "lost", as necessary, and new data for display could then be introduced into the display memory at the appropriate locations. However, it is preferred simply to redefine the entire contents of the display memory for each change in the display in the same manner as that used for changing the display of the selected portions of data in response to "select" command signals.
Conveniently, the entire display is redefined every field scan of the display device using a scan 30 synchronisation technique, which involves erasing the data in the display memory progressively for each scan line of the display afterthe data has been usedforthe display in that scan line and inserting into the display memory the same or new data, as required, before that data is required for the display in that scan line of the next field. Assuming standard TV scanning of 50 fields per second, plus 4 ms field blanking, approximately 30 ms is available in which to redefine the display. In effect, the display is redefined every 35 field scan although the scan synchronisation is effected over two successive field scans, as will be described. This technique gives the advantage that an adequate prior is available between successive displays for re-defining the data in the display memory.
As regards the logic operation of the processor means of a data display arrangement in accordance with the invention, the "select" command signals may be in the form of multi-bit binary codes, the 40 processor means being operable to compare the first "select" command signal code which is received with start codes of afirst set of start codes which pertain respectively to the starting addresses of respective groups of addresses in which different sections of the data stored in the background memory are located.
Correspondence between the first "select" command signal code and one of the start codes of the first set causes the processor means to identify with an address pointerthe appertaining starting address which 45 is thereby identified as a first address of a given number of addresses from which data is then read out and written into the display memory as a selected portion of data.
Each of these start codes may be a data code which is also stored in a respective address and represents an item of data located at that address.
When the second "select" command signal code of a sequence is received, this is compared with a 50 second data code in successive addresses of the group which is identified by the first "select" command signal, the first correspondence between the second "select" command signal code and one of the second data codes causing the processor means to identify with the address pointerthe address containing that second data code as a new first address of a new same given number of addresses from which data is now read out and written into the display memory as a new selected portion.
55 The selection of further new selected portions of data for display can thereafter be effected in similar manner by comparing the codes of further "select" command signals with subsequent data codes, commencing with the next data code in the last new first address that has been identified.
For each comparison step of the foregoing operations, an address offset step can be provided, so that each selected portion of data which is read out and written into the display memory is taken from said given 60 number of addresses beginning with an offset starting address which is not the address actually containing a data code which satisfies the comparison step.
In order that the invention may be more fully understood, reference will now be made byway of example to the accompanying drawings, of which:—
Figure 1 shows a block diagram of a data display system embodying the invention;
65 Figure 2 shows a table for the ASCII data code;
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GB 2 173 980 A 3
Figure 3 and 4 show memory maps illustrating the principles of the invention;
Figure 5 shows in the form of a flow chart logic operations of the system in the performance of the invention; and
Figures 6a to 6e shows diagrammatically a scan synchronisation technique.
5 Referring to the drawings, the data display arrangement shown in Figure 1 comprises a display device 1, a display generator 2, a processor 3, a background memory 4, a display memory 5 and user interface apparatus 6 and 7. The display device 1 is suitably a colour television monitor (TV) which is connected to receive R, G, B, video signals from the display generator 2. These R, G, B, video signals are produced in the display generator 2 by three digital-to-analogue converters (D/A)8,9and 10, respectively. The display 10 generator 2 also includes a colour look-up table (CLUT) 11 which is suitably a read/write memory and is responsive to dot information received from the display memory 5 over a bus 12 to produce digital signals for driving the converters 8,9 and 10. A display timer (TIM) 13 in the display generator 2 provides line and field synchronisation signals LS and FS for the television monitor 1 over a connection 14. The timer 13 also provides over a connection 15 timing signals T for controlling the transfer of dot information from the 15 display memory 5 to the colour look-up table 11.
The display memory 5 is suitably a random-access memory (RAM) which has a capacity for storing dot information for at least one display frame. The dot information would comprise one or more information bits per dot to be displayed, depending on the range of colours afforded by the colour look-up table 11. A combined address/data bus 16 interconnects the display generator 2 and the display memory 5 with the 20 processor 3. The background memory 4, which is also at least partially a random-access memory (RAM), is also connected to the address/data bus 16. The background memory 4 may also have a read-only memory (ROM) part which contains permanent program data for controlling the "house-keeping" operations of the processor 3. The user interface apparatus 6 and 7 comprise a keyboard data entry device (KEY) and a graphics tablet (TAB), respectively. The processor 3 can be a commercially available microprocessor (up), 25 for instance the Signetics S68000 MP-
It is assumed that data stored in the RAM memory 4 is textual and comprises multi-bit codes which represent text characters. When a text character is to be displayed, the code therefor is read from the RAM memory 4 by the processor 3 and written into the display memory 5 at an appropriate location as dot information.
30 Consider now the application of the present invention for displaying any selected portion of a dictionary list of words which contains words beginning with all the letters of the alphabet. The list can comprise many thousands of words, for example 30,000 words, which is the sort of capacity of a small English language paper dictionary. The words are in alphabetical order in the list. It is assumed each letter of the alphabet is represented by a respective 7-bit code combination of the ASCII code.
35 A table for the full ASCII code is shown in Figure 2, although for the purposes of the present invention only the codes for certain letters of the alphabet will be referred to. In the bit notation used in the table, bit 67 is the high-order, and bit 61 the low-order, bit position. Thus, the 7-bit code for the letter "R" is 67(1), 66(0), 65(1), 64(0), 63(0), 62(1) and 61 (0).
In the background memory 4, each word of the list of words is stored at a separate address, each 40 address comprising a plurality of byte locations BY1, BY2,... BYm of 8 bits 68 to 61 (see Figure 4), one location for each of the codes which representthe letters of the word. Assuming a list of words containing 30,000 words, as aforesaid, 215 (32K) different memory addresses are required for this purpose in the background memory 4. In hexadecimal notation these addresses can be identified by respective address codes in the range 0000 to FFFF.
45 A memory map for this part of the background memory 4 is illustrated diagrammatically in Figure 3. In this memory map, which is designated by the reference numeral 17, the first address is identified by the hexadecimal code 0000 and the last address is identified by the hexadecimal code 7530. The addresses are divided into a number of different groups GP1 to GP26 of different size. Each group contains addresses for storing the codes for all the words beginning with a respective particular letter, so that the size of a group 50 that is, how many addresses it contains, depends on the number of words in the wor.d list that begin with the letter concerned. The stored data is thus effectively divided into sections, one section for each letter of the alphabet, which are stored in respective ones of the groups of addresses GP1 to GP26. The arrow 18 represents an address pointer which identifies any particular address from which read out is to occur.
The address group GP15 comprises the addresses in which are stored all the words in the word list that 55 begin with the letter "O". If the hexadecimal address code for the first address of this group is, say, 3A98 and there are 500 sequential addresses in the group, then these addresses will have the address codes 3A98 to 3C8C, as indicated. Address group GP1, which comprises the addresses in which are stored all the words in the word list that begins with the letter "A", is shown as having 900 sequential addresses with address codes 0000 to 0385. Address group GP26 has only 40 sequential addresses with address codes 7509 to 7530. 60 This latter address group comprises the addresses in which are stored all the words in the word list that begin with the letter "Z".
The address group GP15 for words beginning with the letter "O" is shown more fully in Figure 4. By way of example, it is assumed that the first 60 word addresses, and the 75th, 76th and 500th word addresses of this group contain, respectively, the letter codes for the following words which begin with the letter "0".
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OAF
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OBJURGATE
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OBSESS
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OAK
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OBLATION
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OBSIDIAN
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OAKUM
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OBLIGATO
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OBSOLETE
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OAR
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OBLIGE
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OBSTACLE
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OASIS
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OBLIGATION
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OBSTETRIC
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OAST
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OBLIQUE
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OBSTINATE
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OAT
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OBLITERATE
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OBSTREPEROUS
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OATH
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OBLIVION
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OBSTRUCT
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OBDURATE
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OBLONG
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OBSTRUENT
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OBEDIENCE
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OBLOQUY
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OBTAIN
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OBEISANCE
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OBNOXIOUS
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OBTRUDE
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OBELISK
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OBOE
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OBTUSE
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OBESE
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OBOLE
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OBVERSE
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OBEY
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OBOVATE
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OBVIATE
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OBFUSCATE
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OBSCENE
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OBVIOUS
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OBITER
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OBSCURE
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OCARINA
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OBITUARY
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OBSECRATE
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OCCASION
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OBJECT
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OBSEQUIES
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OCCIDENT
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OBJECTIVE
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OBSEQUIOUS
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OCCLUDE
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OBJURE
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OBSERVE
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OCCULT
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76. OCULAR
500. OZONE
In Figure 4, the letter codes for the 1st, 9th, 24th, 32nd, 53rd, 76th and 500th words are shown in their respective word addresses 3A98,3AAO, 3AAF, 3AB9,3ACD, 3AE3 and 3C8C. Each letter code comprises 7 bits in correspondence with the ASCII table shown in Figure 2. The left-hand (high-order) bit position b8 of each 8-bit byte is unused. The address pointer 18 is shown again in Figure 4. It will be appreciated that, in 25 practice a word address can comprise more than one memory address, depending on the size of the word and the byte capacity of the memory addresses.
The logic operations which are performed by the processor (3—Figure 1) of the data display arrangement to produce the display of a selected portion of the stored list of words will now be explained in outline with reference to the flow chart shown in Figure 5. For this explanation, it is convenient to consider 30 the request by a user of the display of that portion of the word list which contains a particular word which is located centrally in the displayed portion. The word chosen for this purpose is "OBVIOUS". In the flow chart the legends in the various boxes have the following meanings.
19—STRT —when the arrangement is switched-on, initialisation occurs to set various counters, flags, indicators, etc., to their starting values. 35 20—BY=BY1 —A "comparison pointer" selects memory addresses in which are stored "group codes" which identify uniquely the twenty-six different address groups.
(Each address group has an individual "group code" allotted to it. The "group code" is the letter code for the particular letter that the words stored in the address groups begin with that is, the letter code in the 40 first byte BY1 of each word address. Thus, the "group code" for the address group GP15 is the letter code for the letter "0"; that is, 1001111.).
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21—GP=GP1
22—DETIstCS
23—1stGS=GP?
24—GP=GP+1
— The "group code" is read out from thefirst byte BY1 of the first word address in thefirst address group GP1. (The address pointer (18) is set to thefirst word address of an address group when the relevant "group code" is read out).
— The first command signal produced by the keyboard device (KEY) is detected. (In the present instance, this first command signal will be the letter code for the letter "O").
— The first command signal (letter code "O") is compared with the "group code" (letter code "A") forthe first address group GP1.
— The "group code" read out is incremented to the "group code" for the second address group GP2 (letter code "B"), if there is no correspondence between the compared codes in step 23.
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(The address pointer (18) is also set to the first word address of the second address group GP2. This incrementing thereafter continues, with adjustment of the position of the address pointer (18) until the letter 55 code "O" representing address group GP15 is compared with the letter code "O" representing the first command signal.).
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25—RD 24 ADR — When step 23 detects correspondence between the compared letter codes, the words stored in thefirst 24 word addresses in the address group concerned, i.e. group GP5 in this instance, are read out and the appropriate dot information for these words is written 5 into the display memory 5, as mentioned previously. The position 5
ofthe address pointer 18 determines the starting address for this read out.
25—DSP5 — This is a subroutine for displaying the contents ofthe display memory 5 on the display device 1.
10 (It is assumed that there are 24 words displayed as a sub-list at any one time as the selected portion of 10 the word list, hence the read-out from thefirst 24 sequential word addresses ofthe address group GP15.
This displayed sub-list therefore comprises the words "OAF" to "OBLIGE" in the foregoing word list, as read out from the word addresses 3A98 to 3AAF).
27—BY=BY+1 —The "comparison pointer" selects for read out letter codes which 15 are stored in the second bytes BY2 of the word addresses of the detected address group.
28—LC=LC1 —The "letter code", which in the present example will be for the
"letter "A" ", is read from the second byte BY2 of thefirst word address in the address group GP15. (The address pointer (18) is 20 set to this first word address ofthe address group GP15.) 20
29—DET NXT CS — The next (second) command signal produced by the keyboard device (KEY) is detected. (In the present instance, this second command signal will be the letter code for the letter "B").
30—NXT CS=LC? — The second command signal (letter code "B") is compared with
25 the "letter code" (letter code "A") in the second byte of the first 25
word address ofthe address group GP15.
31—LC=LC+1 — The "letter code" read out is incremented to the "letter code" in the second byte BY2 ofthe second word address (in which the letter codes for the word address (in which the letter codes for the 30 word "OAK" are stored) of address group GP15, if there is no 30
correspondence between the compared codes in step 30. The address pointer (18) is stepped once so as to be set to this second word address. The letter code "A" is also in this second byte BY2,
so that further incrementing to the next word address occurs.
35 (This incrementing thereafter continues, accompanied by adjustment ofthe position ofthe address 35 pointer (18), until the letter code "B" in the second byte BY2 ofthe 9th (3AAO) word address ofthe address group GP15 is read out and compared with the letter code B representing the second command signal.
When step 30 (NXT CS=LC?) detects correspondence between the letter codes, step 25 (RD 24 ADR) is returned to so that the words stored in this word address and the subsequent 23 word addresses in the 40 address group GP15 are read out and the appropriate dot information for their words is written into the 40 display memory 5 in place ofthe dot information previously written in. Again, the position ofthe address pointer 18 (at address 3AAO) determines the starting address for this read out. The displayed sub-list of words (step 26—DSP5) now comprises the words "OBDURATE" to "OBOE" in the foregoing word list.
Thereafter, step 27 (BY=BY+1) increments the "comparison pointer" to select for read out letter codes 45 which are stored in byte BY3 of the word addresses, and step 28 (LC=LC1) resets the read out ofthe letter 45 codes in the bytes BY3to start from the word address identified by the pointer 18. Step 29 (NXT CS) detects the next command signal received (i.e. the letter code "V") and step 30 (NXT CS=LC?) will detect the correspondence of this letter code "V" with the "letter code" V read out from byte BY3 of the word address 3ACD. Step 25 (RD 24 ADR) is then returned to again and the words stored in this word address and the 50 subsequent 23 word addresses are read out and the appropriate dot information for these words is written 50 into the display memory 5 as new dot information. The address pointer is now at word address 3ACD which is the starting address for this read out. The displayed sub-list of words (step 26—DSP5) now comprises the words "OBVERSE" to "OCULAR" in the foregoing word list.
The word chosen for display (i.e. OBVIOUS) now appears in the displayed sub-list. However, this word 55 is the third in the sub-list and therefore appears near the top ofthe display screen ofthe display device. The 55 display can be scrolled to move the word chosen to a more central position in the displayed sub-list under the control ofthe graphics tablet (TAB—Figure 1).
This scroll feature is represented in the flow chart of Figure 5, by the steps 32 (SCR DET) and 33 (AP—OFS).
60 32—(SCR.DET) —A "scroll" command signal (up or down) produced by the 60
graphics tablet (TAB) is detected.
33—(AP—OFS) — The position ofthe address pointer (18) is offset by one address
(up or down).
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Steps 25 (RD 24 ADR) and 26 (DSP5) are then repeated to read out and display words from the 24 addresses concerned. This accomplishes a "hard scroll" by which the displayed sub-list is changed (i.e.
moved up or down) one word at a time. For smoother scrolling, the display memory (5—Figure 1) would be required to store at least one extra word at each end ofthe words which form the displayed sub-list, with the 5 scan lines initially receiving display data progressively for one or the other of these extra words, depending 5 on the scrolling direction. Step 25 would then be required to read 26 sequential addresses into the display memory.
As regards the detection of the "group codes" which identify the address groups GP1 to GP5, all the word addresses may be addresses sequentially and the code in the first byte BY1 therein read out and 10 compared with a received "select" command signal code. Alternatively, the address pointer (18) can be 10
programmed to cause only thefirst address in each ofthe address groups to be addressed. A further possibility is to store either the word addresses or the letter codes in these bytes BY1, in a separate sub-memory the addresses of which can then be addressed sequentially to read out these word addresses or letter codes to determine the code to be compared with or received "select" command signal code. 15 As a further modification, an address offset step 37 (as shown in dotted lines in Figure 5) can be 15
provided in conjunction with the step 25, so that the 24 word addresses from which data is read out for display following each comparison step do not run from the actual word address that contains a letter code which satisfies the comparison step. The effect of this, when the offset results in a preceding word address being the first ofthe 24 word addresses read out, is to cause a word which is selected by a sequence of 20 "select" command signal codes which has a code for each letter of the word, to be positioned centrally 20
without any scrolling being necessary.
The diagrams 6a to 6f represent the dot information in the display memory (5—Figure 1) during different instants that the display rub-routine (DSP5—Figure 5) is being performed. In each of these diagrams, the block 34 represents one information bit level ofthe display memory, the lined rectangle 35 25 represents the information bitsforthesub-listofwordsto be displayed, and the arrow 36 represents the 25 addressing scan position from which the bit information is being read out for a scan line at any instant. In diagram 6a, the bit information for the entire word sub-list is present in the display memory, and the addressing scan position is about one-third way down the display memory. In diagram 66, the addressing scan position is about two-thirds way down the display memory and about one-third ofthe dot information 30 which has already been used for this field scan has been erased. In diagram.6c, the addressing scan position 30 has reached the end of the scan and all ofthe dot information behind it has been erased. To achieve this, the rate at which the dot information is erased row-by-row is made fast enough to "catch-up" with the line scan, but not before the end of the field scan. In diagram Qd, the addressing scan position is now, in effect, in the vertical blanking period between successive field scans. During this period, new dot information is being 35 stored in the display memoryforthe next field scan. In diagram 6e, the next field scan has started and the 35 display memory is about half-filled with new dot information. In diagram 6f, the display memory is completely filled with new dot information and the next field scan is nearly completed. Thereafter the cycle represented by diagrams 6a to 6f is repeated to refresh the display memory with new dot information every otherfield scan. It has been calculated that it takes approximately 25 ms. to both erase old dot information 40 from and write new dot information into the display memory. For a field scan period of 20 ms. and vertical 40 blanking interval of 4 ms, approximately 30 ms. is available forthe erase/write operation, by starting this operation when the addressing scan position is about one-third way down the display memory as shown in diagram 6s.

Claims (1)

  1. 45 1. A digitally operable data display arrangement for displaying as an entity on the screen of a raster 45 scan display device, a quantity of data which is stored in a display memory and is accessed repeatedly for its display in a recurrent cycle of scanning lines; which data display arrangement comprises a background memory for storing a large amount of data, a display memory for storing as said quantity of data a selected portion of data read from the background memory, a display generatorfor producing video signals in 50 accordance with the selected portion ofthe data in the display memory for driving the display device, and 50 processor means and an associated user interface device forthe selection for display of selected portions of the data in the background memory; and which data display arrangement is characterised in that said interface device has a plurality of switch means each of which is operable to produce a respective command signal, in that the processor means is operable, when the command signal produced by the operated switch 55 means is the first signal in a sequence of command signals, to access data in the background memory at a 55 starting address which is identified uniquely from the command signal, in that the processor means is then operable to read out and write into said display memory a selected portion ofthe data from that starting address and respective further addresses, and in that the processor means is further operable, when the command signal produced by an operated switch means is not the first signal in a sequence of command 60 signals, to access data in the background memory at a new starting address which is identified from that 60 command signal in conjunction with the or each preceding command signal ofthe sequence, a new selected portion ofthe data from the new starting address and respective further addresses being then read out and written into said display memory by said processor means.
    2. A data display arrangement as claimed in Claim 1, characterised in that the large amount of data
    7
    GB 2 173 980 A 7
    stored in the background memory is in the form of a list of items, and any portion of this list, which portion each time contains a same given number of items, can be read from the background memory by said processor means as a selected portion for display.
    3. A data display arrangement as claimed in Claim 2, characterised in that said list of items is a 5 dictionary list of words.
    4. A data display arrangement as claimed in any preceding Claim, characterised in that said interface device is a data entry keyboard device, the keys of which constitute said switch means.
    5. A data display arrangement as claimed in any preceding Claim, characterised in that said processor means is further operable to provide also a scrolling function in response to "scroll" Command signals from
    10 a second interface device.
    6. A data display arrangement as claimed in Claim 5, characterised in that said second interface device is a graphics tablet and associated pen for providing successive indexing scroll command signals in response to vertical movement of the pen on the graphics tablet.
    7. A data display arrangement as claimed in Claim 5 or Claim 6, characterised in that, both for the
    15 selection and display of discrete selected portions of data in response to "select" command signals and for the selection and display of modified selected portions of data by scrolling in response to "scroll"
    command signals, the processor means is arranged to redefine the entire contents of the display memory for each different display.
    8. A data display arrangement as claimed in Claim 7, characterised in that the processor means is
    20 operable such that the entire display is redefined every field scan ofthe display device using a scan synchronisation technique which involves erasing the data in the display memory progressively for each scan line ofthe display, after the data has been used forthe display in that scan line and inserting into the display memory the same or new data, as required, before that data is required forthe display in that scan line in the next field.
    25 9. A data display arrangement as claimed in any preceding Claim, characterised in that the data in the background memory is in the form of multi-bit codes which represent respective text (alpha-numeric) characters, and in that when a selected portion ofthe list is read from the background memory by the processor means, the latter writes corresponding data into the display memory as dot patterns for the characters concerned, at least one information bit being stored for each dot of each dot pattern.
    30 10. A data display arrangement as claimed in any preceding Claim, characterised in that the "select" command signals are in the form of multi-bit binary codes, and in that the processor means is operable to compare the first "select" command signal which is received with start codes of a first set of start codes which pertain respectively to the starting addresses of respective groups of addresses in which different sections ofthe data stored in the background memory are located, correspondence between thefirst
    35 "select" command signal and one of the start codes of thefirst set causing the processor means to identify with an address pointer the appertaining starting address which is thereby identified as a first number of addresses from which data is then read out and written into the display memory as a selected portion of data.
    11. A data display arrangement as claimed in Claim 10, characterised in that each ofthe start codes of
    40 the first set is a data code which is stored in a respective address and represents an item of data located at that address.
    12. A data display arrangement as claimed in Claim 11, characterised in that when the next "select" command signal code of a sequence is received, the processor means is operable to compare this next signal with a second data code in successive addresses of the group which contains the identified starting
    45 address, thefirst correspondence between the next command signal code and one ofthe second data codes causing the processor means to identify with the address pointer the address containing that second data code as a new first address of a new same given number of addresses from which data is now read out and written into the display memory as a new selected portion of data.
    13. A data display arrangement as claimed in Claim 11 or Claim 12, characterised in that for each
    50 comparison step, an address offset step is provided, so that each selected portion of data which is read out and written into the display memory is taken from said given number of addresses beginning with an offset starting address which is not the address actually containing a data code which satisfies the comparison step.
    14. A digitally operable data display arrangement substantially as hereinbefore described with
    55 reference to the accompanying drawings.
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    Printed for Her Majesty's Stationery Office by Courier Press, Leamington Spa. 10/1986. Demand No. 8817356. Published by the Patent Office, 25 Southampton Buildings, London, WC2A 1AY, from which copies may be obtained.
GB08509853A 1985-04-17 1985-04-17 Data display arrangements Withdrawn GB2173980A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB08509853A GB2173980A (en) 1985-04-17 1985-04-17 Data display arrangements
EP19860200620 EP0198555A2 (en) 1985-04-17 1986-04-14 Data display arrangements
AU56171/86A AU5617186A (en) 1985-04-17 1986-04-16 Electronic information display device
JP61087225A JPS61281331A (en) 1985-04-17 1986-04-17 Electronic information display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08509853A GB2173980A (en) 1985-04-17 1985-04-17 Data display arrangements

Publications (2)

Publication Number Publication Date
GB8509853D0 GB8509853D0 (en) 1985-05-22
GB2173980A true GB2173980A (en) 1986-10-22

Family

ID=10577799

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08509853A Withdrawn GB2173980A (en) 1985-04-17 1985-04-17 Data display arrangements

Country Status (4)

Country Link
EP (1) EP0198555A2 (en)
JP (1) JPS61281331A (en)
AU (1) AU5617186A (en)
GB (1) GB2173980A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2180973B (en) * 1985-08-12 1989-08-02 Sharp Kk Information retrieval device
GB2282685A (en) * 1993-05-31 1995-04-12 Mitsuhiro Aida Text input method
AU700320B2 (en) * 1993-08-31 1998-12-24 Mitsuhiro Aida Text input system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2070399A (en) * 1980-02-27 1981-09-03 Xtrak Corp Real time toroidal pan
GB2145308A (en) * 1983-08-16 1985-03-20 Ibm Display selection in a raster scan display system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2070399A (en) * 1980-02-27 1981-09-03 Xtrak Corp Real time toroidal pan
GB2145308A (en) * 1983-08-16 1985-03-20 Ibm Display selection in a raster scan display system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2180973B (en) * 1985-08-12 1989-08-02 Sharp Kk Information retrieval device
GB2282685A (en) * 1993-05-31 1995-04-12 Mitsuhiro Aida Text input method
GB2282685B (en) * 1993-05-31 1998-03-04 Mitsuhiro Aida Text input method
AU700320B2 (en) * 1993-08-31 1998-12-24 Mitsuhiro Aida Text input system

Also Published As

Publication number Publication date
EP0198555A2 (en) 1986-10-22
JPS61281331A (en) 1986-12-11
GB8509853D0 (en) 1985-05-22
AU5617186A (en) 1986-11-06

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