DE3066328D1 - Calculation method and assembly for the presentation of randomly upward or downward biased calculation results, and with determination of the number of correct significant digits - Google Patents

Calculation method and assembly for the presentation of randomly upward or downward biased calculation results, and with determination of the number of correct significant digits

Info

Publication number
DE3066328D1
DE3066328D1 DE8080400145T DE3066328T DE3066328D1 DE 3066328 D1 DE3066328 D1 DE 3066328D1 DE 8080400145 T DE8080400145 T DE 8080400145T DE 3066328 T DE3066328 T DE 3066328T DE 3066328 D1 DE3066328 D1 DE 3066328D1
Authority
DE
Germany
Prior art keywords
presentation
randomly
calculation
upward
determination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080400145T
Other languages
English (en)
Inventor
Jean Vignes
Vincent Ung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bpifrance Financement SA
Original Assignee
Agence National de Valorisation de la Recherche ANVAR
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agence National de Valorisation de la Recherche ANVAR filed Critical Agence National de Valorisation de la Recherche ANVAR
Application granted granted Critical
Publication of DE3066328D1 publication Critical patent/DE3066328D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Automatic Assembly (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Calculators And Similar Devices (AREA)
DE8080400145T 1979-02-02 1980-01-30 Calculation method and assembly for the presentation of randomly upward or downward biased calculation results, and with determination of the number of correct significant digits Expired DE3066328D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7902784A FR2448188A1 (fr) 1979-02-02 1979-02-02 Procede et ensemble de calcul, aleatoirement par exces ou par defaut, pour fournir des resultats de calcul avec le nombre de chiffres significatifs exacts

Publications (1)

Publication Number Publication Date
DE3066328D1 true DE3066328D1 (en) 1984-03-08

Family

ID=9221561

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080400145T Expired DE3066328D1 (en) 1979-02-02 1980-01-30 Calculation method and assembly for the presentation of randomly upward or downward biased calculation results, and with determination of the number of correct significant digits

Country Status (6)

Country Link
US (1) US4367536A (de)
EP (1) EP0018238B1 (de)
JP (2) JPS55103641A (de)
AT (1) ATE6099T1 (de)
DE (1) DE3066328D1 (de)
FR (1) FR2448188A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727506A (en) * 1985-03-25 1988-02-23 Rca Corporation Digital scaling circuitry with truncation offset compensation
US4831576A (en) * 1986-05-06 1989-05-16 Yamaha Corporation Multiplier circuit
JPH02293928A (ja) * 1989-05-08 1990-12-05 Nec Ic Microcomput Syst Ltd マイクロコンピュータ
US5325316A (en) * 1990-10-11 1994-06-28 Fujitsu Limited Compression processing method of real number data in processing system and apparatus therefor
US10540143B2 (en) 2015-10-24 2020-01-21 Alan A. Jorgensen Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof
US9817662B2 (en) 2015-10-24 2017-11-14 Alan A Jorgensen Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3569685A (en) * 1968-07-11 1971-03-09 Fairchild Camera Instr Co Precision controlled arithmetic processing system
US3699326A (en) * 1971-05-05 1972-10-17 Honeywell Inf Systems Rounding numbers expressed in 2{40 s complement notation
US4110831A (en) * 1977-06-29 1978-08-29 International Business Machines Corporation Method and means for tracking digit significance in arithmetic operations executed on decimal computers

Also Published As

Publication number Publication date
JPH0210448B2 (de) 1990-03-08
JPS63211428A (ja) 1988-09-02
FR2448188A1 (fr) 1980-08-29
ATE6099T1 (de) 1984-02-15
FR2448188B1 (de) 1982-10-29
EP0018238A1 (de) 1980-10-29
US4367536A (en) 1983-01-04
JPS6346452B2 (de) 1988-09-14
JPS55103641A (en) 1980-08-08
EP0018238B1 (de) 1984-02-01

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee