DE3065982D1 - Semiconductor memory device using one transistor memory cell - Google Patents

Semiconductor memory device using one transistor memory cell

Info

Publication number
DE3065982D1
DE3065982D1 DE8080301583T DE3065982T DE3065982D1 DE 3065982 D1 DE3065982 D1 DE 3065982D1 DE 8080301583 T DE8080301583 T DE 8080301583T DE 3065982 T DE3065982 T DE 3065982T DE 3065982 D1 DE3065982 D1 DE 3065982D1
Authority
DE
Germany
Prior art keywords
transistor
memory cell
memory device
semiconductor memory
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080301583T
Other languages
English (en)
Inventor
Mitsuo Higuchi
Kiyoshi Miyasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3065982D1 publication Critical patent/DE3065982D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
DE8080301583T 1979-05-26 1980-05-14 Semiconductor memory device using one transistor memory cell Expired DE3065982D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54065349A JPS5847796B2 (ja) 1979-05-26 1979-05-26 半導体メモリ装置

Publications (1)

Publication Number Publication Date
DE3065982D1 true DE3065982D1 (en) 1984-02-02

Family

ID=13284381

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080301583T Expired DE3065982D1 (en) 1979-05-26 1980-05-14 Semiconductor memory device using one transistor memory cell

Country Status (4)

Country Link
US (1) US4314360A (de)
EP (1) EP0020054B1 (de)
JP (1) JPS5847796B2 (de)
DE (1) DE3065982D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3030867A1 (de) * 1980-08-14 1982-03-11 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung fuer einen in zeilen und spalten organisierten festwertspeicher zur vermeidung des absinkens von bitleitunspotenialen
JPS57147196A (en) * 1981-03-06 1982-09-10 Fujitsu Ltd Read-only memory
US4388705A (en) * 1981-10-01 1983-06-14 Mostek Corporation Semiconductor memory circuit
JPS6048090A (ja) * 1983-08-26 1985-03-15 伊勢電子工業株式会社 螢光表示装置
US4627032A (en) * 1983-11-25 1986-12-02 At&T Bell Laboratories Glitch lockout circuit for memory array
US4709352A (en) * 1984-11-19 1987-11-24 Oki Electric Industry Co., Ltd. MOS read-only memory systems
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
US4833646A (en) * 1985-03-04 1989-05-23 Lattice Semiconductor Corp. Programmable logic device with limited sense currents and noise reduction
GB2176357B (en) * 1985-06-12 1989-07-12 Stc Plc Improvements in semiconductor memories
US4722075A (en) * 1985-10-15 1988-01-26 Texas Instruments Incorporated Equalized biased array for PROMS and EPROMS
IT1231902B (it) * 1987-10-20 1992-01-15 Sgs Microelettronica Spa Memoria elettronica cmos di sola lettura a funzionamento statico
JPH0715952B2 (ja) * 1988-04-13 1995-02-22 株式会社東芝 半導体記憶装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648071A (en) * 1970-02-04 1972-03-07 Nat Semiconductor Corp High-speed mos sense amplifier
US3962686A (en) * 1972-05-16 1976-06-08 Nippon Electric Company Limited Memory circuit
US3810124A (en) * 1972-06-30 1974-05-07 Ibm Memory accessing system
US3909808A (en) * 1974-12-23 1975-09-30 Ibm Minimum pitch mosfet decoder circuit configuration
JPS5333542A (en) * 1976-09-10 1978-03-29 Hitachi Ltd Signal detection circuit
US4094012A (en) * 1976-10-01 1978-06-06 Intel Corporation Electrically programmable MOS read-only memory with isolated decoders
US4151603A (en) * 1977-10-31 1979-04-24 International Business Machines Corporation Precharged FET ROS array

Also Published As

Publication number Publication date
EP0020054B1 (de) 1983-12-28
US4314360A (en) 1982-02-02
JPS55157195A (en) 1980-12-06
EP0020054A1 (de) 1980-12-10
JPS5847796B2 (ja) 1983-10-25

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee