DE3065036D1 - Method of making a vertical dmos type field effect transistor - Google Patents

Method of making a vertical dmos type field effect transistor

Info

Publication number
DE3065036D1
DE3065036D1 DE8080400865T DE3065036T DE3065036D1 DE 3065036 D1 DE3065036 D1 DE 3065036D1 DE 8080400865 T DE8080400865 T DE 8080400865T DE 3065036 T DE3065036 T DE 3065036T DE 3065036 D1 DE3065036 D1 DE 3065036D1
Authority
DE
Germany
Prior art keywords
making
field effect
effect transistor
type field
vertical dmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080400865T
Other languages
German (de)
English (en)
Inventor
Eugene Tonnel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Application granted granted Critical
Publication of DE3065036D1 publication Critical patent/DE3065036D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8080400865T 1979-07-10 1980-06-13 Method of making a vertical dmos type field effect transistor Expired DE3065036D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7917848A FR2461360A1 (fr) 1979-07-10 1979-07-10 Procede de fabrication d'un transistor a effet de champ du type dmos a fonctionnement vertical et transistor obtenu par ce procede

Publications (1)

Publication Number Publication Date
DE3065036D1 true DE3065036D1 (en) 1983-11-03

Family

ID=9227711

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080400865T Expired DE3065036D1 (en) 1979-07-10 1980-06-13 Method of making a vertical dmos type field effect transistor

Country Status (5)

Country Link
US (1) US4375717A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0022388B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5617074A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3065036D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2461360A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2100507A (en) * 1981-06-17 1982-12-22 Philips Electronic Associated Method of making a vertical igfet
GB2108758B (en) * 1981-10-26 1985-08-21 Intersil Inc Power field-effect transistor structures
US4554570A (en) * 1982-06-24 1985-11-19 Rca Corporation Vertically integrated IGFET device
DE3380377D1 (en) * 1982-06-24 1989-09-14 Harris Semiconductor Patents Vertical igfet device and method for fabricating same
JPS5941870A (ja) * 1982-08-25 1984-03-08 Toshiba Corp 半導体装置の製造方法
JPS6190464A (ja) * 1984-10-11 1986-05-08 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
IT1213234B (it) * 1984-10-25 1989-12-14 Sgs Thomson Microelectronics Procedimento perfezionato per la fabbricazione di dispositivi a semiconduttore dmos.
FR2576710B1 (fr) * 1985-01-25 1988-03-04 Thomson Csf Procede d'obtention d'une diode dont la prise de contact est auto-alignee a une grille
ATE109593T1 (de) * 1986-02-04 1994-08-15 Canon Kk Photoelektrisches umwandlungselement und verfahren zu seiner herstellung.
JPS62230057A (ja) * 1986-03-31 1987-10-08 Nec Corp 縦型電界効果トランジスタ
JPS63119574A (ja) * 1986-11-07 1988-05-24 Toshiba Corp 半導体装置の製造方法
US5028555A (en) * 1987-12-02 1991-07-02 Advanced Micro Devices, Inc. Self-aligned semiconductor devices
EP0460857B1 (en) * 1990-05-31 1997-03-19 Canon Kabushiki Kaisha Method for producing a semiconductor device with a high density wiring structure
US5223732A (en) * 1991-05-28 1993-06-29 Motorola, Inc. Insulated gate semiconductor device with reduced based-to-source electrode short
US5321291A (en) * 1991-12-16 1994-06-14 Texas Instruments Incorporated Power MOSFET transistor
EP0654829A1 (en) * 1993-11-12 1995-05-24 STMicroelectronics, Inc. Increased density MOS-gated double diffused semiconductor devices
US5631484A (en) * 1995-12-26 1997-05-20 Motorola, Inc. Method of manufacturing a semiconductor device and termination structure
FR2758907B1 (fr) * 1997-01-27 1999-05-07 Commissariat Energie Atomique Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique
US6426259B1 (en) * 2000-11-15 2002-07-30 Advanced Micro Devices, Inc. Vertical field effect transistor with metal oxide as sidewall gate insulator
JP5001494B2 (ja) * 2001-08-28 2012-08-15 セイコーインスツル株式会社 絶縁性基板上に形成された電界効果トランジスタ
DE102007012380A1 (de) * 2007-03-14 2008-09-18 Austriamicrosystems Ag MOSFET mit Kanalanschluss und Verfahren zur Herstellung eines MOSFETs mit Kanalanschluss

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967981A (en) * 1971-01-14 1976-07-06 Shumpei Yamazaki Method for manufacturing a semiconductor field effort transistor
DE2225374B2 (de) * 1971-05-28 1977-06-02 Fujitsu Ltd., Kawasaki, Kanagawa (Japan) Verfahren zum herstellen eines mos-feldeffekttransistors
JPS4859781A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1971-11-25 1973-08-22
US3912557A (en) * 1974-05-02 1975-10-14 Trw Inc Method for fabricating planar semiconductor devices
JPS50150379A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1974-05-22 1975-12-02
JPS5122348A (ja) * 1974-08-20 1976-02-23 Hitachi Ltd Johoshorisochi
JPS5191675A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1975-02-07 1976-08-11
NL7510903A (nl) * 1975-09-17 1977-03-21 Philips Nv Werkwijze voor het vervaardigen van een halfgelei- derinrichting, en inrichting vervaardigd volgens de werkwijze.
US4181542A (en) * 1976-10-25 1980-01-01 Nippon Gakki Seizo Kabushiki Kaisha Method of manufacturing junction field effect transistors
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
US4191602A (en) * 1978-04-24 1980-03-04 General Electric Company Liquid phase epitaxial method of making a high power, vertical channel field effect transistor
US4322882A (en) * 1980-02-04 1982-04-06 Fairchild Camera & Instrument Corp. Method for making an integrated injection logic structure including a self-aligned base contact

Also Published As

Publication number Publication date
EP0022388A1 (fr) 1981-01-14
US4375717A (en) 1983-03-08
FR2461360A1 (fr) 1981-01-30
JPS5617074A (en) 1981-02-18
JPH0526352B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-04-15
FR2461360B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1982-11-26
EP0022388B1 (fr) 1983-09-28

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