DE3000107C2 - - Google Patents

Description

The present invention relates to a microprogram addressing device according to the preamble of claim 1, in a data processing system with a Linking device, the link operations based on of data, these linking operations being a include first and second microprogram routines and ensuring that addresses are the most recent Microinstruction of the first microprogram routine mentioned are associated.

For microprogram control of data processing systems control memories are used in many cases, the sequence of operations through in it in the form of so-called firmware stored microinstruction words is controlled. In one Firmware are various main routines and beyond Subroutines that are shared by the main routines can contain. Is switched from a main routine to a subroutine or must interrupt a routine for some reason the address of the next memory location or of the next command in such a routine to ensure to later on the command of the routine that is no longer executed has been able to return.

According to the state of the art, for example in the US company publication from Advanced Micro Devices "Microprogramming Handbook "1976, pages 1-1 to 1-15 and pages 2-11 to 2-15  an address incrementing device is used for this purpose and a return address register. With help this embodiment is when a subroutine entry is executed the incremented address in the return address register as address for the control memory to return from the Subroutine saved. It can be seen that this is known Set up an elaborate increment and associated Control logic requires that - although appropriate - however takes up a significant amount of space and increases overall Manufacturing costs leads.

The invention is therefore based on the object, the generation to simplify the return addresses from subroutines.

The above task is solved by a microprogram addressing device according to the preamble of the claim 1 in such a way that a state changing device is provided when returning from the second microprogram routine to resume execution of the interrupted first microprogram the state of a bit of the concerned Bits belonging to the last microinstruction concerned Invert address allowed before execution the first microprogram routine is returned.

With the help of this invention in a data processing system, its sequence of operations by stored in a control memory Microinstructions, for example in the form of firmware, is controlled, a simplified one for the return to a briefly interrupted routine and improved practice applied. The address the last microinstruction that was given before such a routine such a program interruption is saved, thereby later returning to the routine in question is that you use the stored address in question, but with a bit of this address in terms of its state  Inversion is changed.

The control store is based on the content of the control store words as well as on the basis of other input signals depending on in the central processor executed operations addressed. The next address will be generated by an address generation logic. It is it is important to address the control memory at the same time the status of more than one test condition (e.g. conditional Jump) is used and taken into account. Wouldn't you can take into account in an appropriate manner, it would be necessary each of the status or test states, for example, accordingly to load clock-controlled into a register. This would always be necessary when these test conditions change. So it is desirable to test several such functions at the same time, without having to load them into a clock-controlled register. For realization this desirable function includes the address generation logic a multiplexer with multiple signal inputs. One the multiplexer takes the input signals from a locking mechanism forth on what is the simultaneous exploitation of more than allows a test condition for addressing the control memory. By using further input signals on the multiplexer the control store can use branch address information and further test status information can be addressed. A page register provides the page address for a multitude of pages contained in the control memory thereby addressing the memory locations in each such page that the multiplexer-signal combination mentioned above is used becomes. By providing the ability to do more than one test condition The addressing of the control memory can be taken into account done faster, and accordingly the overall performance of the data processing system increased.

In the exemplary embodiment of a microprogram addressing device described below includes the data processing system a control store with a variety  of storage spaces, each for storing a Control word is used to control the operation of the processor is used. It is also an arrangement for recording a variety of signals provided or included, which are characteristic for the status information of the data processor. Furthermore the arrangement in question serves to receive an instruction or an instruction, the or the characteristic is for the address information that is used to address the Tax memory is used. It is also an arrangement to accommodate a first selected part an addressed control word of the control words. A first multiplexer arrangement is also provided that has an output. This first Multiplexer arrangement gives the output of signals on your Output free, which are characteristic of the status information the first selected part of the addressed control word of control words. Furthermore, an arrangement for the Decoding of the information provided by the command receiving arrangement is recorded, the recorded The command is characteristic of such address information. A third arrangement is also provided, which either the signals of the first selected part at the output the first multiplexer arrangement or that of the arrangement selects information recorded for decoding. Furthermore is a second multiplexer arrangement with an output and a variety of inputs provided, one of which first input is connected to the selection arrangement and a second entrance of which a selected part an addressed control word of the control words from the Control store fed here receives. It is also an arrangement for addressing the control memory by means of a of the input signals provided by the second multiplexer arrangement be included.  

The data processing system contains a link arrangement to perform link operations for dates. These operations close execution a first routine and a second routine a. Furthermore, a storage device with a Large number of stored instructions or commands provided, which are used to the Link arrangement for performing such operations in one by the relevant instructions or to release commands in a certain way. Besides, is an addressing device for addressing a provided such storage device. In the link arrangement an arrangement is included that for Execution of such routines serves. Furthermore, one Arrangement provided that the execution of the first routine interrupts to execute the second routine. Finally, an arrangement is provided that a Allow address to be retained which is the last command which command belongs to the first routine at the time of the interruption of execution of the concerned first routine was executed. Such one Address includes a variety of bits, each have a first state or a second state. Furthermore, an arrangement is provided, the state allowing such a bit of the address to be changed, associated with the last command, the one in question Change before the return to the execution of the first routine is done so that the next command of such a first routine is addressed to the relevant last command follows the first routine.

An embodiment of the invention will be described below with reference to drawings for example explained in more detail.

Fig. 1 shows the overall system configuration including the present invention.

2 shows an operational sequence state diagram of the processor according to the embodiment of the present invention.

Fig. 3 shows a block diagram of the processor according to the embodiment of the present invention.

Fig. 4 illustrates the contents of the registers of the processor according to the embodiment of the present invention.

Fig. 5 shows in a detailed block diagram of an arithmetic unit of the embodiment of the present invention.

Figure 6 illustrates part of the contents of the control store word used in connection with the present invention.

FIG. 7A to 7F illustrate details of the respective next address generating address generation logic in accordance with the embodiment of the present invention.

FIGS. 8A and 8B illustrate details of a Subroutinen- logic according to the embodiment of the present invention.

Figure 9 illustrates in a table of values the operation of the logic shown in Figure 7A.

The overall configuration of the data processing system shown in FIG. 1, which comprises the microprogram addressing device according to the invention, shows a central processing unit CPU 11 , a commercial instruction processor 13 , which is abbreviated to CIP (Commercial Instruction Processor), a control device 15 and a memory 17 , all via one System bus line 19 are interconnected. The commercial instruction processor 13 is provided to expand the CPU instruction set with further instructions of a commercial type, for example with alphanumeric instruction types, sorting, data conversion, processing instructions, etc.

The commercial instruction processor receives the information from the Central unit and from the main memory and processes them in one logical consequence. Four CIP operating states occur as follows open: idle state, charge state, busy state and not programmed Jump state.  

The recording any commercial command by the CIP facility usually takes place simultaneously with the central unit, because this fetches every command from the main memory and decoded. Execution of the command in the CIP facility takes place asynchronously with the central unit Operations. Any attempt to run a commercial Command in the event that a CIP device in the System is not installed, the central unit causes to enter a certain non-programmed jump state.

As shown in FIG. 2, the CIP enters block 200 and remains idle (block 202 ) when no information processing is taking place; it must be in the idle state in order to receive a command or a command (ie a CIP instruction or an input / output command) from the central unit. Upon receipt of a command (block 204 ), if valid (block 205 ), the CIP device will enter the state of charge (block 206 ) and remain in the relevant state of charge until the entire associated command information has been recorded. If this information is successfully received (block 208 ), the CIP enters the busy state (block 210 ) to process the information. Any further attempts on the part of the central unit to enter into data exchange with the CIP device while the latter is in the busy state will not be acknowledged by the CIP device, and not until the latter returns to the idle state. CIP setup processing involves data exchange activity with main memory; this activity occurs when the required operand (s) are picked up. The CIP device only enters the non-programmed jump state (block 212 ) when special impermissible events occur (block 214 ), such as the determination of an impermissible operand length or an out-of-sequence command. The return to hibernation is made when the operation has completed (block 216 ).

All associated or significant instruction transfers to the CIP facility are shared by the Central unit and the CIP device executed. The relevant instructions are decoded and processed by the CPU unit to the CIP device along with the whole associated information sent out for the Execution of the relevant instruction is required. When the information transfer is complete, place the central processing unit and the CIP device the processing of their corresponding instructions. Any CIP Instruction contains a 16 bit instruction word, which immediately up to six additional words from Description type (also with a width of 16 bits) follow, so-called data descriptors or labels. The instruction word contains the CIP operation code, which is sent to the CIP facility for processing becomes. The data descriptors describe the operand type,  the size and space in memory; the Tag provides the address of a remote data descriptor. Both the data descriptor and the label become processed by the central unit; one related to it standing information through this process is obtained or derived like an operand type and a memory address are sent to the CIP device sent out for processing. The central unit completed the procedure in that the operation code examines or analyzes the one contained in each instruction is. If the central unit has a CIP instruction notes (which means that the CIP facility in Is idle), then the central unit sends the Instruction opcode and the associated or so related information in the following Way out: (i) The central processing unit sends to the CIP device the opcode (i.e. the first word of the commercial instruction). The CIP establishment enters the state of charge when it accepts the opcode; (ii) the central unit calls the first data descriptor and queries the address syllable to find the generate effective address; (iii) the central unit sends the following information: The 24 bit effective byte address of the first operand, the content of the associated CPU data register, if applicable, and the data descriptor of the first operand that is updated is that it is a byte (8 bits) or nibble (4 bits) digit position within a word reproduces; when the second and third operand occurred are, the central unit carries out the appropriate Procedures in steps ii and iii.

At this point, the CIP device is loaded with all of the information required to execute the commercial instruction and also enters the busy state to execute the instruction. If necessary, the CIP device enters into direct data exchange with the main memory in order to obtain the applicable operand or operands. However, it should be noted that the CIP never accesses any of the CPU registers directly. It only uses the information that is sent to it by the central unit. With this, no CPU registers are modified by the CIP device, and the central processing unit continues processing the next and each subsequent CPU command until one of the following conditions occurs: (i) The CIP device shares an unprogrammed one Jump unit (TV) of the central unit with the fact that an illegal event has occurred during the execution of the commercial instruction currently running, or (ii) an internal or external interrupt signal is determined by the central unit.

If the CPU detects an interrupt signal the central unit performs the following operations out. The central unit concerned determines whether the last commercial instruction from the CIP facility has been completed or not. The central unit waiting for the last commercial instruction to finish. When the last commercial instruction is completed the central unit determines whether this is led to a non-programmed jump request Has. If this was the case, then consider the Central unit the non-programmed jump request before executing the interruption. this leads to a typical contextual retention / restoration Operation to get all relevant CPU and CIP status Store information that is needed. With the Completion of the required CPU operations for processing a CIP jump request or if none There is a jump request and a CIP instruction for  the processing is available, the central unit performs following operations. The central unit updated their program counter to go to the commercial Show instructions that she tried to trigger. The central unit postpones the attempt at processing the commercial instruction until the present interruption is served. The person in question Central unit takes into account and serves the by a external interruption caused.

When the CIP device executes an instruction, can all CPU registers, including those registers by the current commercial command or the relevant instruction is referenced by a Program can be changed via the CPU instructions. The However, software needs the operand for a commercial one Instruction not to be modified until the CIP device the processing of the relevant instruction executed. Otherwise, unspecified results occur. The ones included in the CIP instruction repertoire Branch instructions are issued by the central processing unit and executed synchronously by the CIP device.

The three data types that make up the data words that processed by the CIP facility are alphanumeric Data, binary data and decimal data. Any data type is classified in binary information units. By defining this unit, if by reference the alphanumeric and binary data characters are used given by eight bits (one byte); at Use to refer to decimal data they are four bits (nibbles) for packed decimal data and eight bits (one byte) for string decimal data. Include single precision binary numbers also two units (two bytes), and binary numbers double precision is four units (four bytes).  

In Fig. 3 is a main block diagram of the commercial instruction processing processor 13 according to the present invention is illustrated, wherein all of the main data-transfer paths are illustrated between the registers of the processor.

Control store 10 includes a plurality of memory locations, one for each control store or firmware word. These firmware words directly or indirectly control the processor sequences, the data transfer paths and the bus operations.

The operand register files and the arithmetic and logic unit (RALU) 12 mainly comprise two register files, an arithmetic logic unit (ALU) and the associated multiplexers and control registers. The unit 12 also includes the operand register files ( RP 1 and RP 2 ), each of which contains 16 bit positions which are used to buffer operands for execution in the arithmetic logic unit ALU . The arithmetic unit input multiplexer and latch circuits are formed by the following devices; Three 2-to-1 multiplexers (zone selection), two 4-to-1 multiplexers (digit selection) and two 8-bit latches (byte latches). These multiplexers and locking circuits are used to deliver data from the operand register files to the arithmetic and control unit ALU . Data can also be output from the counter provided for the present product to the left side of the arithmetic and control unit ALU or from the operand register file 2 to the multiplication register. The 8-bit arithmetic and control unit ALU (which consists of two 4-bit ALU chips, a carry-preview chip and an entry / discharge flip-flop) can perform the following operations between the left ( 1 ) and right ( 2 ) Execute inputs: binary addition, binary subtraction input 1 from input 2 , binary subtraction input 2 from input 1 , logical OR, logical AND, exclusive OR, setting the ALU output to FF and deleting the ALU output to 00. The RALU device will be explained in detail in connection with FIG. 5.

The excess set ( XS 6 ) correction logic of the RALU device is released when the arithmetic and control unit ALU works in decimal mode; it is used to change the binary output signal from the adder to the correct decimal digit while the transmission output signal is modified for subsequent operations. The XS 6 correction is carried out using a 32-bit to 8-bit PROM chip, which encodes the corrected three high-value bits of the digit and generates the corrected carry. For further controls, a number comprising fewer than two functions is also available at the output of the PROM chip. The output multiplexer of the arithmetic and control unit ALU is used to deliver either the upper four bits of the adder output signal or the corrected decimal zone bits to the internal bus line 14 , depending on whether the arithmetic and control unit ALU is in binary mode or in decimal mode is working. The RALU control logic comprises three registers: RF 1 A - register file 1 address register, RF 2 A - register file 2 address register and ALMR - ALU operation control register. In conjunction with several microinstructions, these registers control all operations within the RALU facility. In addition to the registers described above and the control device described above, two further registers are provided, which are classified as RALU registers. These registers are a current product counter (CPRC) and multiplication register (MIER) . These registers and facilities will be discussed further below.

The control file 16 , which is also referred to as register file C (RFC) , is a RAM memory with 16 storage locations of 24 bits. This memory is mainly used to store all the instruction-related information coming from the central unit 11 (e.g. task or process words, data descriptors, effective addresses, etc.). The control file also contains several working memory locations which are used by the processor (CIP) firmware. The control file 16 receives bits 0-7 either from the internal bus line 14 or from the bus address register (MAR) 18 via the OR logic multiplexer 21 . The bus address register (MAR) 18 and the address adder logic 20 will now be explained in more detail. Register 18 is a 24-bit address register, which is mainly used to address system bus line 19 . It includes a two-input 8-bit multiplexer register at the bottom and a 16-bit increment / decrement device at the top. The input signal input to the lower eight bits by multiplex control comes either from the control file 16 or from the output of the address adder 20 . The address adder 20 is an 8-bit two's complement adder unit which is mainly used to increase or decrease the content of the bus address register 18 . The input signals to the address adder 20 are the eight low order bits of the bus address register and the 8 bit shift register (MSR) 22 . Shift register (MSR) 22 is an 8-bit universal shift register which can be loaded from internal bus line 14 and which can shift left or right by one bit (which means an open end shift with zero fill he follows). The shift register acts as an input device for the address adder 20 in order to increase or decrease the content of the bus address register 18 . In addition, bit zero of shift register 22 can be loaded into the ALU entry flip-flop, which is useful during execution of the conversion instructions.

The bus line output data register (OUR) 24 is a 16-bit data register which is used to transfer data to the data line of the bus line 19 . The relevant register is loaded by the internal bus line 14 with either the lower byte or the upper byte or the entire 16-bit word. The bus line input data register (INR) 26 is a 16-bit data register which is used to receive data from the data lines of the bus line 19 . The content of the input data register can be unloaded and output to the internal bus line 14 .

The input function code register (BFCR) 28 is a 6-bit register which is used to store the function code when the CIP device accepts any input or output command occurring on the bus line 19 . The firmware then checks the content of the function code register 28 and executes the specified command. The input address bank register (INAD) 30 is an 8-bit register which is used to store the high-order eight memory address bits which are received via the address lines of the bus line 19 . The higher eight address bits include the memory module address; they are transmitted by the central unit 11 as a result of a so-called IOLD command or an effective address function output code. The low-order 16 bits of the memory address are received via the data lines of the bus line 19 and keyed into the INR register 26 , whereby the required 24-bit main memory address is formed.

The CIP display register 32 is an 8-bit memory register in which each bit can be set or reset individually. The display register bit configuration is illustrated in FIG. 4. The TRP and TRP line indicators are used by the CIP device 13 only for internal processing; they are not visible to the software. The TRP line (CIP branch line) indicator is used to inform the CPU 11 of an existing non-programmed CIP branch state; the relevant display is transmitted via the bus line 19 by the external jump signal. If the TRP display (non-programmed CIP jump) is set, this display enables the CIP device to only accept input commands from the central unit.

The exam register (AR) 34 is a 16-bit register, which is mainly used to control microprogram branches (masked branches) and the perforation byte coding / decoding logic. This register is loaded with the entire 16-bit word from the internal bus line 14 . The micro-programmable switch register (MPSR) 36 is an 8-bit register in which each bit can be set or reset individually, under micro program control. Each bit within the MPSR register 36 is used as a tag to facilitate micro-programming (which means that the firmware can test each of the register bits and perform branching operations depending on the test results). Some of these bits are also used to control certain hardware functions of the CIP device 13 .

The ROS data register (RD) 38 is a 52-bit memory register which is used to store the control memory output signal (firmware word) for the present firmware cycle. The microprogram return address register (RSRA) 40 is an 11-bit register which is loaded from the output of the address generation (NAG) logic 42 which generates the next address in each case. The relevant register is used to store the microprogram return address when a firmware subroutine is executed. Register file C address multiplexer / selector (RFCA) 31 is a 4-bit, 2-to-1 selector capable of addressing one of the 16 memory locations contained in register file C (this is the control file 16 ). This selector 31 selects a combination of the function code register 28 and either the counter ( 1 ) 46 or selected bits of the ROS data register 38 . The CIP counters 44 comprise three 8-bit up / down counters 46, 48 and 50 , which are set as counter 1 ( CTR 1 ), counter 2 ( CTR 2 ) and counter 3 ( CTR 3 ) or are designated. These counters are charged / discharged via the internal bus line 14 . The content of each counter is available for test and branch operations.

Punch byte decoder / encoder logic 52 includes two PROM memory chips with 512 memory locations of four bits. These memory chips are used to decode / encode the content of the test register (AR) 34 . The byte that is decoded is obtained from AR bits 1 through 7, and the coded beginning of digits is obtained from AR bits 4 through 7. The decode / encode operation is performed by using AR bits 1 through 7 to address a particular PROM location. The content of the designated PROM memory location is encoded so that it matches, either: (1) with the decoded digit, its sign and its validity, or (2) with the encoded perforated byte. Bit 4 of the MPSR register 36 determines whether a decoding operation or an encoding operation is carried out, while the MPSR bit 1 indicates the sign of the encoded digit. In addition, the output signal of the perforation byte decoding / coding logic is available on both halves of the internal bus line 14 .

The CIP test logic 54 selects one of 32 possible firmware test conditions or test states for input to the address generation logic 42 generating the next address. The actual or incorrect state (1 or 0 state) of the function being checked controls bit 50 of the control memory address field provided for the next address (which means that bit 50 is set or reset, depending on the state of the tested one Function). The next generation address generation (NAG) logic 42 included in the CIP 13 uses one of the following five methods to generate the next firmware address: direct address, test and branch, masked branch , Main branch or subroutine return. The direct addressing method is used when an unconditional branch to the next sequential control storage location is carried out. This is achieved by using bits 41 to 51 of the control memory word to form the next address. These bits include the next address (NA) field, which can directly address any of the available control locations. The method of testing and branching is used when a 2-way condition branch (test state fulfilled) is executed within a firmware page (a firmware page is a segment with 128 memory locations within the control memory). This process is carried out by using the control memory bits 41, 42, 43, 44 and 50 to select a test condition or a test condition. Then, depending on the state of the function checked, a branch is made to one of the two memory locations. The branching operation performed using this method is a module 2 operation (which means that the two possible branching addresses are two memory locations apart). The module 2 address is formed as follows: (1) If the test state is fulfilled, bit 9 of the address is set to 1, or (2) bit 9 of the address is set to 0 if the test state is not fulfilled . The masked branch method is typically used when a branch is based on the contents of the Check Register (AR) - 34 or certain other conditions; this leads to a branch to memory locations 2, 4, 8 or 16 within the same firmware page (a firmware page is a segment with 128 memory locations within the control memory). The main branching method is used when the branching takes place within a firmware page (128 words). A CPU / CIP interface routine uses this method to carry out the required 16-fold branching with regard to the content of the function code register 28 . (INB main branch) and other control functions (EOP main branch). The subroutine return method is used to return the firmware to the next odd or even control memory location after a firmware subroutine is executed. The return address is obtained from the return address (RSRA) register 40 ; it must be stored in this register 40 before execution of the designated subroutine.

The internal bus line 14 has a width of 16 bits; it is mainly used to transfer data between the CIP registers, including the memory locations within the register files. The internal bus line receives data from various sources, as illustrated in FIG. 2. The output signals occurring on the internal bus line 14 are output to various registers within the CIP device.

The parity check logic 56 is connected between the bus line 19 and the internal bus line 14 ; it is used to check the parity of the incoming data. The parity generator logic 58 on the other hand is used to generate the correct parity bit for the transmission for the bus line 19 . Bus line request logic 60 and bus line response logic 62 are used for purposes of enabling the CIP device to gain access to bus line 19 and to respond to any requests to gain access to the CIP device. The linking devices 60 and 62 are described in US Pat. No. 3,993,981.

FIG. 5 shows a main block diagram of the RALU device 12 , with all main data transmission paths and control lines being illustrated. The control lines are indicated by dashed lines to facilitate understanding of the operation of the lines concerned. For the sake of simplicity, the description of the RALU device is divided into seven areas: operand register files, ALU input multiplexers and interlocking circuits, arithmetic logic unit, XS6 correction logic, ALU output multiplexers, RALU control logic and various RALU registers. The operand register files RF1 70 and RF2 72 each contain four RAM memory chips, which are used for short-term storage for CIP operands. The addresses for each of the register files are given by two 6-bit address registers RF 1 A 74 and RF 2 A 76 . Bits 0 to 3 of the respective address register supply the address of the memory location within the associated register file, while the low-order bits are provided for the byte and number selection at the output of the register file. These two address registers can be incremented or decremented by 1, 2 or 4 (ie by digits, bytes or words). As illustrated in Figure 5, the output from each register file is fed to the inputs of two multiplexers (i.e., a pair of multiplexers for each register file) which make a selection between the zone and digit information. The selection is effected by bits 4 and 5 of the associated address register. Bit 4 selects whether bits 0 through 3 or eight through 11 (from the register file) are applied to the output of 2-to-1 multiplexers 78 or 80 , while bit 5 is used to select the register file bits which form the digit which is fed to the output of the 4-to-1 multiplexer 82 or 84 . The various registers and multiplexers are connected in such a way that they are controlled via the various control lines, which are illustrated by broken lines; These control lines include, for example, control lines 71, 73, 75 and 77 . A third 2-to-1 multiplexer 86 is used to select whether the content of the product counter (CPRC) 88 intended for the current product or the number is output by the RF1 device to the A latches 90 . This multiplexer is controlled by the ALMR register 92 . The ALU input latches, A latches 90 and B latches 106 receive both the zone information and the digit information from the ALU input multiplexers and latch the data into register files during write operations. The outputs of the locking circuits deliver the zone and digit information to the left side or to the right side of the ALU device. The product counter (CPRC) for the product at hand is a 4-bit up / down decimal counter, which is mainly used during the execution of the decimal multiplication and division operations. The multiplication register (MIER) 94 is a 4-bit up / down binary counter used primarily during decimal multiplication and division operations. The ALU operation control register (ALMR) 92 is a 6-bit control register which is used to control all ALU operations. Register file 1 address register (RF1A) 74 is a 6-bit address register that performs two functions: (1) providing addresses for register file 1 ( 70 ) and (2) controlling two of the three ALU input multiplexers that are associated with the register file 1 . Register file 2 address register (RF2A) 76 is a 6-bit address register that performs two functions: (1) providing addresses for register file 2 ( 72 ) and (2) controlling the ALU input multiplexer associated with register file 2 . All operations of the arithmetic logic unit (ALU) 100 are carried out either in decimal mode or in binary mode. Decimal mode is used when working with decimal digit information while binary mode is used for byte (alpha) operations. The two modes also control the excess 6-XS6 correction logic 102 and the input signals for the transmit flip-flop. In decimal mode, the carry flip-flop for the carry is loaded by the low-order 4 bits of the ALU device, while in binary mode it is loaded with the carry by the eight bits of the ALU device for subsequent arithmetic operations. The carry flip-flop is loaded under micro program control when a carry must be forwarded for subsequent operations. In addition, the carry flip-flop can be loaded from the MSR register and set or reset under micro program control. The XS6 correction logic 102 has a 32-bit to 8-bit PROM memory chip and the associated control logic for correcting the high order three bits of the digit output signal of the ALU device. The XS6 correction is performed if (1) the ALU device operates in decimal addition mode and a decimal carry is included, or if the digit output of the ALU device 100 is greater than 9, and (2) in decimal subtraction mode if borrowing is included (ie in the absence of a carry from the digit portion of the adder). The PROM chip has five address lines. Three of these lines comprise the three high order bits from the digit output of the ALU, while the other two address lines indicate the type of operation being performed (ie addition correction, subtraction correction or no correction). The coded content of the PROM chip is given by the three higher-order corrected bits of the digit, the corrected decimal carry and the digit state, which is less than 2. The ALU output multiplexer 104 selects between the upper four bits of the adder output and the corrected decimal zone bits for delivery to the internal bus line. The configuration of the zone bits (for decimal mode) depends on whether ASCII or EBCDIC data is used (which means that when using ASCII data the zone bits are given a value of 3 , while when using EBCDIC- Data of the zone bits is given a value of F ).

The RALU control devices include registers RF 1 A 74 , RF 2 A 76 and ALMR 92 plus various microinstructions belonging to the RALU device. In addition, the ALU carry flip-flop is under micro program control.

The carry flip-flop can (if necessary) be pre-cleared or preset by the appropriate microinstructions, and it can also be loaded: (1) by the 4-bit digit carry for decimal operations, (2) by the 8-bit Binary transfer for binary operations or (3) through bit 0 of the MSR register 22 during the execution of conversion commands or instructions. The ALMR register 92 , which controls all of the ALU operations, is loaded by the control memory bits 2-7. Bit 0 determines whether the ALU device works in decimal mode or binary mode, which means that the carry output signal of the ALU device comes from bit 4 (digit transfer) or from bit 0 (binary transfer). Bit 0 also controls both the ALU correction ( XS 6 ) for decimal operations and the ALU output multiplexer 104 ; the multiplexer determines whether the four high-value bits of the ALU device or the supplied zone bits are forwarded to the internal bus line 14 . Bits 1, 2 and 3 are used to control operations within the ALU. Bit 4 determines whether the zone bits have a value of 3 or F (for ASCII data, the zone bits have a value of 3; for ADCDIC data, the zone bits have a value of F ). Bit 5 determines whether the selected digit from the register file 1 or the content of the product counter 88 currently being used is forwarded to the locking circuits 90 which are associated with the left-hand side of the ALU device. Register RF 1 A supplies the address and the control signals for register file 1 and the associated ALU input multiplexers. Register RF 2 A supplies the addresses and control signals for register file 2 and the associated ALU input multiplexers.

The control file 16 is divided into two areas: the upper area (bits 0 to 7) and the lower area (bits 8 to 23). Each area of the control file can be loaded as follows: Lower area RFC from the internal bus line (bits 0 to 15), upper RFC area from the internal bus line (bits 0 to 7), lower RFC area from the internal bus line (bits 0 to 15) and upper RFC area from the bus line address register 18 (bits 0 to 7). The functions used to perform the above operations are associated with an address that corresponds to the memory location RFC 16 that is being loaded. This address has its origin either in the function code register 28 or in the control memory 10 . Thus, the RFC address is directly related to the type of data that is output from the CPU 11 , or it is indicated by the function code.

The CIP firmware word is divided into 14 different fields. Although different fields appear in identical bit positions within the firmware word format, their functions differ according to the particular operation that is performed during the current firmware cycle. The 14 fields used for the CIP firmware word are: (1) RALU , (2) BI , (3) BE , (4) MSC 1 , (5) CTRS , (6) C 2 R , (7) CONST , ( 8) MAR / MASR , (9) RFCAD , (10) RFCWRT , (11) MISC 2 , (12) MPSR , (13) BR and (14) NA . Here, only the BR and NA fields shown in FIG. 6 are important for the next generation address generation logic of the present invention.

The branch type (BR) field contains bits 37 through 40 of the firmware word. This field determines the type of branch to be executed as a result of a specific test condition. The address field (NA) relating to the next address contains bits 41 to 51 of the firmware word.

This field is either used to (1) one direct address for the next firmware memory location to deliver, or (2) to specify the test condition, the while generating the next firmware address is used, along with its relative Address.

The next ROS address is generated as a function of the BR and NA fields of the control memory word. Decoding these fields results in the following six microinstructions (plus associated arguments) that actually generate the next address: BUN - unconditional branch, BTS - branch on test condition, BMA main branch, RAS - return to subroutine, BRM - masked Branch and BRMEX - masked branch extended.

The next generation address generation logic (NAG) 42 is illustrated in Figures 7A through 7F; it contains multiplexers, PROM memory chips, registers and associated logic devices which, in conjunction with the following ROS data (RD) register fields, generate a control memory (ROS) address. Such data register fields include (1) the branch field (RD 37 BR to RD 40 BR ) and (2) the next address field ( RD 41 NA to RD 51 NA ). These data register fields derive their special functions from the firmware word. The multiplexers perform the following functions together with the specific registers: (1) the address data from one of the lists listed below are selected, (2) the next 11-bit address field is formed from this data (NEXA 00 to NEXA 10 ) and (3) this field is supplied to control store (ROS) 10 to select a specific control store word. The sources from which the address data are selected are as follows:
(1) Check or Analysis Register (AR) 34 , (2) Extended Mask Branch Register 700 with its following inputs: (a) Micro Program Switch Register (MPSR) 36 , (b) Operation Code Register (CIOPR) 704 , (c) Counter-1 and Counter 2 decoder (CTR1 46 and CTR2 48 ), (d) Counter 3 (CTR3) 50 and (e) two sign status indicators ( NEGSNF and ILLSNF ) or indicator register 32 , (3) End of Operation Branch PROM (EOPMB) 706 , (4) initial main branch PROM (BINMB) 708 , (5) ROS return address register (RSRA) 40 , (6) ROS address field (NEXA) 710 , (7) ROS page register (RSRGR) 730 and (8 ) ROS data register (RD) 38 . The exact manner in which the NAG logic generates an address is described below. In the following, a functional description of the registers and PROM memory is given, which are directly connected to the NAG logic. The test register (AR) 34 is a 16-bit register, which is mainly used with a masked branch (BRM) instruction to effect the required microprogram branches within the control memory (ROS) 10 . The AR register is also used to perform the punch-byte decoding / coding operation. Data from the internal bus line ( BI ) is available to the AR register with the execution of a BARFBI microinstruction, which means that AR is loaded from BI . Data from the AR register 34 (or from the extended mask branch register 700 ) is selected and output to the AR test state field ( AR 00 TC to AR 15 TC) through the RD register 38 bit ( RD 37 BR) .

Extended mask branch register 700 is a 16-bit register. It is used only with the extended mask branch (BRMEX) instruction or instruction to transfer the functional data of the associated commercial instruction process (CIP) from selected registers and counters to the AR's output test state field (AR 00 TC to AR 15 TC) Registers 34 to be used for control memory address modification or generation. The selected registers and counters are as follows:
(1) micro program switch register 36 ; this register supplies the applicable microprogram control indicators (MPSR 00 to MPSR 03 ) for the firmware query, (2) operation code register 704 , which holds the disposable or applicable CIP instruction word operation code field (CIOPR 0 to CIPR 5 ), (3) counter 1 46 and counter 2 48 - decoding; these counters provide the test conditions for special microprogram test and branch conditions, (4) counter 3 50 (bits 6 and 7) - counter 3 (bits 6 and 7) is used for offset checking, and (5) sign conditions that provide the negative sign (NEGSNF) and the allowed sign (ILLSNF) codes.

If a main branch (BMA) or a masked branch (BRM) instruction is executed, the control signal RD 37 BR is false or zero. This blocks the transfer of the foregoing functions (posters 1 through 5 ) to the extended masking branch register and enables delivery from the AR register. Then, decoding an extended mask branch (BRMEX) instruction causes the RD 37 BR signal to be asserted as a 1 signal, thereby disabling the output from the AR register and releasing the output from the extended mask branch register.

The microprogram switch register 36 ( MPSR ) is an 8-bit register, which uses each bit individually or collectively as a group of bits as an identifier for microprogramming or for firmware test and branching operations. The output signal from the MPSR register is distributed to the extended masking branch register and the binary multiplexers 712 to modify or generate a control memory address. In addition, selected output signals from MPSR register 36 are distributed to the following CIP logic elements to perform the designated functions: (1) Punch Decoding / Coding Logic 52 , where (a) MPSR 01 sets the operand sign ( 0 = positive (+) Sign; 1 = negative (-) sign), and (b) MPSR 04 specifies the type of decoding / coding operation ( 0 = decoding operation; 1 = coding operation); (2) Data status accumulator : MPSR 05 forms the address for the status accumulator PROM ; (3) RALU : MPSR 07 is used for the multiplexer 10's PROM during MIER loading .

The data output into the MPSR register 36 are obtained from the (RD 32 MS to RD 36 MS) field of the ROS data (RD) register 38 provided for various controls and are controlled by this field. The RD 32 MS signal provides the firmware data for the MPSR input lines. The signal in question is made available to the relevant MPSR output line by a 3-bit binary code on the select (SEL) input lines for the register. This 3-bit binary code is provided by the firmware via the various RD control signals ( RD 33 MS to RD 35 MS) . The actual data transmitted to the selected output line occurs when the signal RD 36 MS is a single signal and when there is a negative transition from MPSREN- on the clock input line C for the register.

The operation code register 704 is a 6-bit register ( CIOPR 0 to CIOPR 5 ), which holds an operation code from a CIP instruction word for the final address modification of a control memory address. This opcode is contained in the hexadecimal code field (bits 10 to 15) of the instruction word. The operation code register monitors bits BI 10 to BI 15 on the internal bus line for this field. When the opcode register receives this field, it is passed to the extended masking branch register 700 and to the end-of-operation PROM memory 706 , in which the field in question is used in the course of generating the next address field ( NEXA ). The data on the internal bus line is keyed into the opcode register 704 for the positive signal jump on the clock input line (C) by the LCIOPR signal. This signal is generated by decoding the output of RD register 38 if: (1) the decoder input address field (RD 17 KT to RD 19 KT) has a binary value 8 , (2) if one BI load operation on the RD register is not handled (which means that the discharge signal ULKNST occurs at a low level) and when (3) the positive signal jump of the next clock pulse 1 occurs.

The three 8-bit counter configurations, designated Counter 1 (CTR1) 46 , Counter 2 (CTR2) 48, and Counter 3 (CTR3) 50 , provide the NAG logic with the following four test states, which are necessary for the execution of certain Test and branching operations described below are used: Less than eight (CTR 3 L 8 ), less than four (CTR 1 L 4 ), CTR 2 L 4 and CTR 3 L 4 , less than two ( CTR 1 L 2 , CTR 2 L 2 and CTR 3 L 2 ) and zero ( CTR 1 E O , CTR 2 E O and CTR 3 E O ). This basic configuration is the same for each of the three counters. The following counter description is thus limited to counter CTR1 46 .

The internal bus line bits 00 to 07 represent the source data for the respective meter configuration. The five data bits with the lowest value of byte 0 of BI (BIDT 03 to BIDT 07 ) or all eight BI data bits of byte 0 (BIDT 00 to BIDT 07 ) can be added be loaded into the counter at any time, the time in question being determined by the firmware. The firmware selects 5-bit loading or 8-bit loading via the RD register constant (KT) field bits RD 16 KT to RD 23 KT . The counter is incremented or decremented by a negative pulse on its corresponding up-count or down-count input line while the other or opposite line is held high. The data from the counter 1 are used to decode one of the previous test conditions from the associated PROM memory. The selected information is then distributed to the extended mask branch register 700 and to the binary test collection multiplexers 712 , where it is used to form the next address field (NEXA) .

The ROS Return Address Register (RSRA) 40 is an 11 bit register which is used to store a micro program return address. This return address is contained in the next address field (NEXA 00 to NEXA 10 ) for the control memory . If this address is stored in the RSRA register, it can only be accessed by returning after a subroutine instruction (RAS) . The data from the next address field are keyed into the RSRA register for the positive signal transition on the clock input line (C) by the signal MISRAD.

The binary test logic 54 comprises four multiplexers and the associated logic logic; it is used only with a BTS instruction to branch to a test. The link arrangement in question selects one of 32 possible firmware test states and forwards the selected test status signal (RSTSTT) to the address generation logic 42 , which is used for the next address generation, to be used when generating a control memory address. The actual test selection is carried out by the four most significant bits of the RD register address field containing the next address, ie ( RD 41 NA to RD 44 NA) and RD 50 NA . For example, to select less than four states from the CIP counter 2 ( CTR 2 L 4 ), the firmware encodes this NA field with a binary 3 (indicating the return to RD 43 NA and RD 44 NA and the shutdown of RD 41 NA and RD 42 NA and also the switching on RD 50 NA means). As a result, the test results are transmitted from the microprogram switch register bit 7 (MPSR 07 ) and from CTR 2 L 4 to the multiplexer output signal lines RSTST 0 and RSTST 1 . The corresponding wired OR output signals RSTSTE and RSTSTD are activated by the signals or lines RSTST 0 and RSTST 1 . The signals RSTST 2 and RSTST 3 are blocked because the signal RD 41 is switched off. The signal RD 41 is fed to the enable input of the multiplexers via an inverter 713 , in accordance with RSTST 2/3 . When the RD 50 NA signal occurs as a 1 signal, however, further transmission of the output signal RSTSTE by the AND gate 717 is blocked or prevented since the RD 50 NA signal is inverted by means of the inverter 719 and because the negated signal is an input signal to the Logic gate 717 is supplied while the transmission of the output signal RSTSTD by the AND gate 715 is enabled. This activates the RSTSTT signal for the next generation address generation logic . This releases the signal RSTSTT , which reflects the actual state or the incorrect state of CTR 2 L 4 .

A control store address is generated by using NAG address generation logic 42 in conjunction with the address lines to control store ROS . The NAG logic is designed in such a way that the important or associated information technology is collected from the selected CIP sources, that this information is formed for a next 11-bit address field (NEXA 00 to NEXA 10 ) and that the relevant address field is on the corresponding control memory ROS address lines is delivered. The selection and forwarding of this information is triggered and controlled by the following six CIP branch instructions: unconditional branch (BUN) , branch to test state (BTS) , return to subroutine (RAS) , main branch ( BMA) , masked branch (BRM) and extended masking branch (BRMEX) . All branch instructions are encoded in the RD register branch field ( RD 37 BR to RD 40 BR) . It should be noted that in view of the fact that the RD register receives firmware information from the control memory, this information is also referred to as the control memory word. The manner in which each instruction and the NAG logic perform their assigned task to form a control store address is described below. It should be noted here that the term firmware side is defined as a 128 word segment within the control memory.

An unconditional branch instruction (BUN) is used to address the next sequential memory location in control memory 10 . The firmware forms this address in the RD register address field (NEXA) provided for the next address. The RD register branch field (RD 37 BR to RD 40 BR) is set to zero for the BUN instruction. When the NAG logic decodes this instruction, the next address control signals (NEXAS 0 and NEXAS 1 ) and the RAS instruction control signal (NEXRAS) are preserved as zero signals. As a result, a zero is output to the selection input lines (SEL) of the BUN multiplexers which, in conjunction with the associated logic logic, formulate and send out the above next address field for the control memory. In addition, when the control signal NEXAS 1 appears as a zero signal, the most significant four bits of the next address field (NEXA 00 to NEXA 03 ) are keyed into the page selection register 730 for the positive signal jump on the clock input line (C) by the signal RSPGCK. The page selection register puts the firmware page number into the control memory for subsequent use in connection with the BTS, BRM or BRMEX instruction.

An instruction (BTS) for executing a branch on a test state is used to execute a 2-way branch within a firmware page. This is done with bit 9 of the next address field (this is NEXA 09 ). The relevant bit 9 describes the 1/0 status of one of 32 possible test conditions which are selected by the binary test logic 54 . The relevant bit is used to modify the page address generated by the firmware when it is formed in the next address field (NEXA) and sent to the control memory . The RD Register BR field is set to a binary 1 (which means RD 40 BR is set) in response to the BTS instruction. The four most significant bits of the NEXA field (RD 41 NA to RD 44 NA) must contain a four-bit binary value in order to select the desired test results. If the NAG logic of this instruction is decoded, the NEXA control signal NEXAS 1 actually occurs or as a 1 signal, and the NEXA control signals NEXAS 0 and NEXAS 1 are retained as zero signals. This sets a binary signal 1 on the select (SEL) input line for the BTS multiplexer, and further releases the page select register and associated logic to form the next address field above and send it to the control memory.

The instruction to return after a subroutine (RAS) is used to return to either an odd or an even control memory location corresponding to the address stored in the RSRA register, the return after the execution of a firmware Subroutine is done. The return address is obtained from the return address register 40 ; it must be stored in this memory before the firmware subroutine is executed. Execution of the RAS instruction results in the transfer of this address from the return address register (RSRA) to the NAG logic to form the next address field (NEXA) for the control store address. The RD Register BR field is set to binary 10 for the RAS instruction. If the NAG logic decodes this instruction, then the NEXA control signals NEXAS 0 and NEXAS actually appear or as 1 signals. The control signal NEXAS 0 causes a binary 2 to appear on the selection (SEL) input line of the RAS multiplexer for the six least significant bits from the RSRA register (ie for RSRA 04 ) from the RSRA register via the NAG Linking logic free. The four RSRA register bits (RSRA 00 to RSRA 03 ) of the highest value are released if the signal RD 39 BR occurs on the selection (SEL) input line for a second RAS multiplexer or is present as a 1 signal. This measure forms the NEXA format for a control memory address.

In the course of the following description of the main branch (BMA), mask branch (BRM) and extended mask branch (BRMEX) instructions, it is assumed that the check and page selection registers contain the disposable address data necessary to form a next address field (NA) are required. The BMA, BRM and BRMEX instructions use the same NAG logic as the previous three instructions (these are the BUN, BTS and RAS instructions) to generate and format their next address fields. The firmware selects and executes one of the three branch instructions by coding both fields with the code that can be issued (instruction / data source). When the NAG logic decodes an instruction, it checks both fields (BR / NA) to determine the type of branch instruction and its data source; it then sets the logic or logic arrangement. For example, if the firmware triggers a BMA instruction using the initial main branch PROM 708 as the main data source, then the RD register branch field is encoded with a binary 5, and further the bits that can be output in the ON field, as set out above, set to zero. When the NAG logic decodes this instruction, it encodes (1) a binary 3 (NEXAS 1 / NEXAS 1 present or 1) on the BMA multiplexer select (SEL) input line for data from the initial main branch. PROM memory, releases (2) the output signal from the page selection register (NEXAS 1 or 1) and bit 45 (RD 45 NA) from the RD register (NEXRAS wrong or 0) and (3) selects ENBMA) , the initial main branch PROM memory from the RD 40 BR + signal. The next address field for a control memory address is thereby formed, as was shown in the previous illustration of the instruction format BM-NA . It should be noted that the initial branch PROM memory is selected via a main branch decoder 732 which is enabled when the RD register bits 41 to 44 are set to zero, as described above.

The masked branches BRM and BRMEX are very similar in property. The only difference between the two branches is that the BRM branch is based on the content of check register 34 shown in FIG. 7B, while the BRMEX branch, which is the extended masking branch, is based on the content of the extended one Masking branch register 700 is based, to which some specified CIP control hardware signals are supplied as input signals. For both branches BRM and BRMEX , the signal RD 38 of register 38 ( RD 38 BR ) must be present or a 1 signal, and to distinguish between branches BRM and BRMEX , bit RD 37 is switched off for the BRM branch and for the BRMEX branch switched on. For the purpose of a simple explanation, only the BRM branch is explained here, whereby analogous explanations apply to the BRMEX branch and to its associated hardware.

If the RD38 signal is present or occurs as a 1 signal, the hardware decodes this branch instruction as a BRM branch. The BRM branch is based on the content of check register 34 , which is a 16-bit register, as has already been described. This register 34 can be interpreted as containing four digits, that is the digits 0, 1, 2 or 3, the digit 0 having bits 0 to 3, while the digit 3 having bits 12 to 15. During execution of the BRM instruction, bits 39 and 40 of the RDBR facility control the digit selection of the check register. For example, if the signals RD 39 and RD 40 are given by zero and 1, respectively, the number 1, that is bits 4 to 7 of the test register, would be selected for a test process. Upon selection of the relevant bits 4 to 7 for a test process, as the name suggests, a mask is provided for these bits in order to hide or mask the bits to be tested. By masking these bits, the BRM instruction has the ability to branch on a 2-way branch, on a 4-way branch, on an 8-way branch, or on a full 16-way branch, provided all four bits of the relevant selected digit are tested.

The mask that controls the bits to be tested in the test register is provided by RD 41 NA to RD 44 NA . For example, if bits 4 and 5 of test register 34 were to be tested, bits RD 39 BR and 40 would be 0 bits and 1 bits, respectively, and bits RD 41 NA and 42 would both be present or only 1 Bits, while bits 43 and 44 are absent or 0 bits. This would result in a mask of 1100, a hexadecimal address (Hex) C , which indicates that bits 4 and 5 of the test register are to be tested. This is effected via the multiplexers 734 and 736 according to FIG. 7B. The multiplexer 734 receives as input signal the 16 bits AR 00 TC to AR 15 TC , which are basically a hard-wired OR function of either the outputs of the test register 34 or the outputs of the extended masking branch register 700 . Bits RD 39 BR and RD 40 BR are present at the selection input of such a multiplexer 734 . The selected four bits or the selected digit of the check register will appear at the output of multiplexer 734 , controlled by RD 39 and RD 40 .

The mask contained in RD 41 NA to 44 controls whether the bit selected from the digit of the check register or the corresponding bit of RDNA 46 to 49 is used to generate the NEXA field for the next address . This selection by masking the corresponding bits in the examination register referred to here as the test register is carried out by the multiplexer 736 according to FIG. 7B. As illustrated in FIG. 7B, the selection is controlled by bits RD 41 through RD 44 and the selection is made between the output of multiplexer 734 , NEXAR 0 through NEXAR 3 , and the corresponding bits from RD 46 NA through RD 49 NA . The corresponding bits of the NEXA field are selected such that, if mask bits are present or set, the corresponding bit of the selected digit of the check register is used to generate the NEXA field. If the corresponding bits of the mask in RD 41 NA to 44 are switched off, then the corresponding NEXA bit from the field RD 46 NA to 49 is used.

These four bits, which are the result of the BRM or BMA microinstructions, are used to generate bits NEXA 05 through NEXA 08 . Assuming, for example, the generation of NEXA 05 , NEXA 05 would be present if RD 41 NA is present, and the selected bit of the digit, basically NEXARO , would be present or a 1-bit. If RD 41 NA were not present or was a 0 signal, the RD 46 NA bit would be selected to generate NEXA 05 . As a result, this microinstruction BRM , like the microinstruction BRMEX, has the property of branching either to a 2-way branch by testing only one bit or, at the other extreme, to a 16-way branch by checking all four bits of the selected digit will.

The extended masking branch is very similar to the BRM branching, with the exception that instead of taking the output of the test register as the selected digit, a group of the groups of test conditions is selected from the extended masking branch register 700 . The end result of multiplexer 736 , which is the result of the masked branch, NEXMK 5 through NEXMK 8 , is ORed with appropriate bits for the initial branch from PROM memory 708 and for the end-of-operation branch from PROM- Memory 706 subjected. The main branch BMA is also similar to branches BRM and BRMEX , except that it requires masking where all bits RD 41 through 44 are zeros. Bits RD 39 and 40 select one of four possible branch PROM memories for the BMA states via decoder 732 to generate the next address. In the case of the BMA state, this is always an unconditional 16-way branch. Bits RD 46 NA to RD 49 NA are not used during the BMA operation. However, if additional main branch connections were required, these bits could be used to encode more BMA states.

The subroutine execution mechanism of the CIP device will now be described. Referring to FIG. 8 of the main process uses starting in block 801, the Busroutine in the blocks 841, 842, etc. multiple times, wherein the main shoot begins in block 871st To make multiple use of a subroutine between two or more main line firmware processes, a return address must be stored before proceeding to the subroutine. This firmware return address is stored in the RSRA 40 register under the control of the microinstruction storage return address ( SRA ) used to clock the RSRA 40 register. When the SRA micro-instructions are executed, the eleven bits of the next address are inserted into the register RSRA under clock control. Assuming, for example, from the flow which begins in block 801, then the SRA micro instruction is executed in block eight hundred and first This microinstruction stores the address of the next sequential memory location in the firmware, e.g., address 400 , for block 800 , as illustrated. Depending on the case, block 802 implements an unconditional branch or a test branch to the subroutine of block 841 . The subroutine is now executed by starting at block 841 and proceeding to block 842 , etc. until the end of the subroutine is reached at block 843 . A return after the subroutine (RAS) microinstruction is then performed, as illustrated in block 843 . This microinstruction causes the NEXA field to match the content of the RSRA register. While the return is being performed because the address 400 is kept in the RSRA register, the low order bit of the address in question in the RSRA register is inverted by means of the inverter 880 to correspond to the address 401 . The NEXA address then corresponds to memory location 401 and the firmware returns to the memory location of block 803 which memory location has address 401 . This only inverts the low-order bit of the RSRA register in order to get to the corresponding return address position after the subroutine.

In the same analogy, the firmware routine beginning in block 871 executes the SRA instruction, and block 872 , which has an address 503 , has temporarily stored such an address 503 in the RSRA register. At block 872 , an unconditional branch or test branch is made to the subroutine of block 841 . The subroutine is executed until it completes, that is, up to block 843 , whereupon a (RAS) microinstruction following the relevant subroutine is executed. At this time, the RSRA register contains address 503 and the low valued bit, bit 10, of the register in question is a binary 1 that is inverted into a binary 0, which corresponds to an address 502 . When the RAS instruction is executed, the return address is now 502 and the return is to block 873 , which has address 502 .

Thus, regardless of the content of the RSRA register Time of execution of the return one bit lower The value of the RSRA register is inverted by the corresponding one Return address point for the RAS microinstruction to build. With such a design or Realization is therefore the low valued bit for uses a subroutine handling mechanism. The one in question Bit leads to two address pairs, which is the exit point and the entry point after execution of the subroutine. If necessary, a to invert another bit, bit 8 or Bit 9 or any other weight bit inverted as long as an inverted bit must be provided to the two corresponding memory locations for the subroutines unwinding mechanism within the CIP facility to provide. This mechanism avoids the use of an incrementer in the next generation address generation logic. The use of such an incrementing device represents a conventional method to Subroutines run in machines controlled by firmware allow. In a normal firmware machine for example, the next address is incremented nominally, and this incremented value is in a return Address register kept, this register to do so is used, the execution of the concerned Return after execution of the subroutine microinstruction to handle. In the present invention, the Demand for such an incrementing device completely avoided, which is why an incrementer is no longer required for addressing  through firmware. Rather, it is only necessary invert a bit to the subroutine mechanism to make it effective.

This one intended for handling subroutines Mechanism can also be extended to, if required to nest subroutines. To form the nesting mechanism a file of RSRA registers would be provided. If, for example four levels of nesting subroutines then four such RSRA registers are to be provided provided within a register file or in a microcircuit, where the last signal entered the first signal output is. This nested subroutine register file would include a pointer that increments each time would be provided if a retention return address to the last saved return address shows so that when a subroutine return is performed becomes the same sequence that has been arrested.

The advantage of using the ROS side register 730 is that it provides four high order address bits for the next address of the firmware. If the ROS page register were omitted, it would be necessary to increment the firmware word by four bits to provide the higher four bits of the next address. Since the four bits of the next address according to the exemplary embodiment of the present invention are provided by the ROS page register, the corresponding four bits of the RDNA field, that is to say bits RDNA 41 to RDNA 44 , can provide further control for the branch microinstructions . For example, in the BTS microinstruction, these bits are used to encode the state that requires checking in this microinstruction. In the case of the BRM and BREX microinstructions , these bits, that is to say bits RDNA 41 to RDNA 44 , provide the 4-bit mask by which the bits of the examination or test register to be checked are controlled.

The firmware side in the arrangement according to the present invention comprises 128 words which are basically derived from the seven bits of low significance of the next address, which corresponds to bits RDNA 45 to RDNA 51 . These bits correspond to bits NEXA 04 to NEXA 10 . The firmware is divided into 128 word pages, the philosophy of these 128 words per page being that in branches such as branches BTS, BRM, BRMEX and BMA, the four bits of high value of the next address field directly from the four bits of the ROS -Page registers. Since the next address field is eleven bits, the seven least significant bits of the next address remain which are generated as a result of the address generation logic according to these branch microinstructions. Since the four high-value bits of the next address are constant during the execution of these microinstructions and originate from the ROS page register, only seven bits remain which are to be used or manipulated for the next address generation. Accordingly, the seven bits correspond to the 128 words of the address base that can be manipulated for these microinstructions. In the present arrangement, for example, 16 such pages with 128 words are provided (2⁷), which leads to a total address base of 2048 words of the firmware. The basic savings that result from using the ROS page register are that the control memory need not be expanded to include the bits corresponding to the ROS memory address and their next address field. If the depth of the control memory is, for example, that in the CIP device, two separate PROM memory chips would be required, which is considerably more expensive than a chip for the ROS page register.

The characteristic of the BRMEX instruction lies in an extension of the masked branching (BRM) microinstruction. Typically, the BRM microinstruction provides a branch characteristic with reference to more than one bit at a time, the relevant bits being selected from the contents of the check register. If the BRMEX property were not available and if it were necessary to test more than one link function in the firmware at the same time, then it would be necessary to load these link states into the examination or test register, from which the relevant states can be loaded using the BRM microinstruction could be tested. This would take place each time these link states change and are tested. By providing the BRMEX property, there is the ability to test more than one function at the same time, for example up to four functions, without having to load them into the examination or test register. These linking functions are systematically arranged in such a way that groups of four functions correspond to the different digits of the check register. These groups of four states are selected based on the layout design and their needs in the same group. This hardware 16544 00070 552 001000280000000200012000285911643300040 0002003000107 00004 16425 states to be tested simultaneously, similar to testing BRM , are available in the extended mask branch latch circuit 700 of FIG. 7B. In fact, the latch circuit 700 (or the relevant register) is a buffer, in particular a so-called tri-state buffer, which can be set in three states (which means that the relevant buffer hangs freely and basically for disconnected states is used by the rest of the hardware). Otherwise , the buffer in question is enabled or blocked for the selection of a BRMEX or BRM microinstruction.

The selection between the BRMEX buffer 700 and the BRM check register 34 is controlled by the bit RD 37 BR . The specific bit or 1-bit goes directly to the test register enable line, and the same bit RD 37 is inverted by means of the inverter 739 , the output signal of the relevant inverter being delivered to the enable pin of the BRMEX buffer 700 .

As already explained, the selection of the main branch or the check register branch BRM or BRMEX takes place under the control of the bits RDNA 41 to 44 . If these four bits are 0, then the BMA microinstruction is enabled. This zero detector logic is provided in block 731 of FIG. 7B. Decoder 732 is used to take advantage of bits RD 39 and RD 40 , which are encoded so that one of the four possible main branches is selected. In the present arrangement, only two of the four possible branches are used, namely ENBMA 0 and ENBMA 1 . These branches correspond to the EOP main branch PROM memory 706 and the initial main branch PROM memory 708, respectively.

Is shown in FIG. 7c with respect to the description of the counter 1, which is illustrated in detail above, that the output signals CTR 100 are supplied to the PROM chip 47 to 107 of the relevant counter CTR 1. On the output side, this PROM chip carries the states of counter 1 which are zero ( CRT 1 E 0 ), which are less than 2 ( CRT 1 L 2 ) or which are less than 4 ( CTR 1 L 4 ). This PROM chip is provided twice for each of the other two counters, namely counter 2 ( 48 ) and counter 3 ( 50 ). Basically, the PROM chip takes over all eight bits of the counters and decodes them to determine whether their values are 0, less than 2, less than 4 or, in the case of counter 3, less than 8. One reason for using a PROM chip for this linkage instead of a typical gate arrangement is that it saves physical space. If this decoding logic were provided using typical hardware (ie, small integrated factor integrated circuits such as AND and OR gates), about three logic chips per counter would be required to decode the values in question. By using the PROM chip for this decoding, a considerable amount of assets (physical space) has been saved.

FIG. 7A illustrates the final-selection of the bits 00 to NEXA NEXA 10 which are passed over the ROS address device 710 to the control memory 10 through. The control functions NEXAS 0 and NEXAS 1 , which are widely used in the link arrangement shown in FIG. 7A, will be explained with reference to the table of values shown in FIG. 9. The value table shown in FIG. 9 illustrates the generation of the two control functions NEXAS 0 and NEXAS 1 . In this value table, the second column contains the different values of bits RD 38 BR to RD 40 BR . Column 3 contains the possible codes for the control signals NEXAS 0 and NEXAS 1 and the corresponding microinstructions that are generated. For example, the signal NEXASA is present or a 1 signal if the bit RD 38 BR is present or a 1 bit or if the bit RD 39 BR is present or a 1 bit. This corresponds to the codes shown in column 3 for 100, 101, 110 and 111 and also for 010 and 011. The first four codes, which start with 100 to 111, are generated for the three micro instructions BRM, BRMEX and BMA , and code 010 is generated for the microinstruction RAS . For these four instructions BRM , BRMEX, BMA and RAS the signal NEXAS 0 is available or a 1 signal. The negated NEXAS 0 signal is present or a 1 signal for the two codes 000 or 001. This corresponds to the micro instructions BUN or BTS .

A corresponding explanation regarding the generation of the NEXAS 1 signal will now be given. The NEXAS 1 signal is present or a 1 signal if the RD 38 BR bit is present or a 1 bit or if the RD 40 BR bit is present or a 1 bit. This corresponds to codes 100 to 111 and 001 and 011. The first four codes correspond to microinstruction BRM, BRMEX and BMA . Code 001 corresponds to microinstruction BTS . It should be noted that code 01 is not used at all. Correspondingly, the negated signal NEXAS 1 occurs for the code 000 or 010 or as a link signal 1, which corresponds to the micro instructions BUN or RAS .

These functions NEXAS 0 and NEXAS 1 together with their negations, the negated function signals NEXAS 0 and NEXAS 1 are used to a large extent to control the multiplexer selection according to FIG. 7A. A detailed explanation of FIG. 7A is now made, in which the generation of the signals NEXA 00 to NEXA 10 is illustrated, which are used for the control memory addressing .

The four bits NEXA 00 to NEXA 03 of high value have a possibility of three input signals, these input signals either directly from RD 41 NA to RD 44 NA or from the ROS return address register RSRA 00 to RSRA 03 and ultimately from the ROS side Registers RSPG 00 to RSPG 03 can originate. The selection from RD 41 NA to RD 44 NA applies to the BUN microinstruction, which is the unconditional branch, whereby the data is taken directly from the ROS data register. The selection of the signals RSRA 00 to RSRA 03 , ie from the ROS return address register, applies to the microinstruction ROS . The selection of the signals or bits RSPG 00 to RSPG 03 , ie the ROS base register, applies to all other microinstructions which are the instructions BRM, BRMEX and BMA . The choice between RD 41 NA to RD 44 NA and RSA 00 to RSRA 03 is made via the 712 multiplexer. The selection from RD 41 to RD 44 is made for the microinstruction BUN , which is controlled by the negative signal RD 39 BR . If the RD 39 BR signal is positive, that is, it is occurring, then the multiplexer output is selected by the ROS return address register. The output signal of this multiplexer is designated NART 00 to NART 03 . The final selection from NART 00 to NART 03 and RSPG 00 to RSPG 03 takes place via the enable lines in the multiplexer 712 and via the register 730 , which is the ROS page register already explained earlier.

Returning to Fig. 9, in which the table of values is shown, it should be noted that this table of values illustrates that NEXAS is 1 or a 1 signal, which corresponds to micro-instructions BTS, BRM, BRMEX or BMA , while the presence of the negated one Signal NEXAS 1 corresponds to the micro instructions BUN or RAS . Signal NEXAS 1 thus controls the enabling and disabling of multiplexer 712 and register 730 . If the NEXAS 1 signal is present, ie, is a 1, meaning that either an instruction BTS, BRM or BRMEX is being processed, then the ROS page register 730 is enabled by the negative value function NEXAS 1 (negative) . If the signal or the function NEXAS 1 (negative) is present, which corresponds to the microinstructions BUN or RAS , then the negative signal NEXAS 1 enables the multiplexer 712 . The outputs of elements 712 and 730 are connected to each other by wiring according to an OR gate , and the final output signal form the four low-order bits of the next address, that is bits NEXA 00 to NEXA 03 .

The signal NEXA 04 is controlled by the two AND gates 714 and 716 . The output signals of these AND gates , namely NEXA 04 B or NEXA 04 A , form the address NEXA 04 through proper wiring of the relevant logic outputs . The two possible sources of the address NEXA 04 are either the ROS return address register or directly the ROS data register RD 45 NA . Bit 4 of the ROS return address register RSRA is enabled by the NEXAS function that is generated for the RAS microinstruction. If the function or the signal NEXRAS is present or is present as a 1 signal, then the output signal of the AND gate NEXA 04 B follows the content of the RSRA bit 4; it is used to generate the output signal NEXA 04 . In contrast, in the event that the negated signal NEXRAS is present, the output signal NEDA 04 A is released; it follows in the content of RD 45 A. These two hard-wired OR functions NEXA 04 A and NEXA 04 B together form the NEXA 04 bit of the next address.

The control of the last six bits of low value of the next link address , that is the bits NEXA 05 to NEXA 10 , is carried out via the multiplexer 718 . This multiplexer is a 1-out-of-4 multiplexer; it is controlled via the two control lines NEXAS 0 and NEXAS 1 , which can have the values 00, 01, 10 or 10 . These values are indicated in the diagram of the multiplexer 718 as selection code 0, selection code 1, selection code 2 or selection code 3. The selection code 0 is in the case that the negated signal NEXAS 0 is present and that the negated signal NEXAS 1 is present. This corresponds to the case of the BUN microinstruction, which is an unconditional branch. In this case, the contents of RD 46 NA to RD 51 NA , which are contents directly from the control memory word , are released at the output in order to form the signals NEXA 05 to NEXA 10 . The next case is when the "Selection 1" signal is present, which means that the negated signal NEXAS 0 is present and that the signal NEXAS 1 is present. In this case, the BTS microinstruction is released. In the case of the BTS microinstruction, the six lines, which are lines RD 46 NA to RD 49 NA , and the final output of test multiplexer 712 , as illustrated in FIG. 7E, are the or wired as the output Outputs of elements 715 and 717 together with signal RD 51 NA released in the relevant order at outputs NEXA 05 to NEXA 10 .

Selection 2, which is when there is one of the NEXAS 0 signals and when the negated signal NEXAS 1 is present, corresponds to the microinstruction RAS , which is the return microinstruction after a subroutine has been executed. In this particular case, bits 05 to 09 of the ROS return address register and the negated output signal of the ROS return address register RSRA 10 are released at the outputs NEXA 05 to NEXA 10 . The final selection output control signal 3 is present in the event that the two signals NEXAS 0 and NEXAS 1 are present or are present as 1 signals. This is the case for the micro instructions BRM, BRMEX and BMA . In this case, the signals NEXM 05 to NEXM 08 , which are the output signals of the multiplexer 736 according to FIG. 7B, are released together with the signals RD 50 NA and RD 51 NA at the outputs NEXA 05 to NEXA 10 . Thus, the multiplexer 718 controls the output signal for NEXA 05 to NEXA 10 for the next address generation .

Finally, these eleven bits NEXA 00 through NEXA 10 are passed from the ROS address, as indicated in block 710 , to the control store to complete the next address.

Claims (9)

1. Micro program addressing device in a data processing system with a link device ( 12 ) which performs link operations on the basis of data, these link operations comprising a first and a second micro program routine, with a control memory device ( 10 ) with a large number of stored micro-instructions which the link device in question ( 12 ) to enable the execution of the operations in question in a manner determined by the micro-instructions concerned, with an address generation device ( 42 ) which allows the control storage device ( 10 ) to be addressed, with a control storage data register ( 38 ), with an interrupt device ( 54 ), which allows the execution of the first microprogram routine to be interrupted for the purpose of executing the second microprogram routine, and with a securing device ( 40 ) which ensures an address ( RSRA ) which is associated with the last microinstruction of the first microprogram routine, the address in question comprising a plurality of bits, each having either a first state or a second state, characterized by the provision of state changing means ( 880 ) which upon return of allowing the second microprogram routine to resume execution of the interrupted first microprogram routine to invert the state of a bit of the relevant bits of the address associated with the relevant last microinstruction before returning to execution of the first microprogram routine. 2. Device according to claim 1, characterized in that the relevant one bit the least significant bit which is the bits forming the address. 3. Device according to claim 1, characterized in that the second microprogram routine is a subroutine that is executed by the first routine and other routines can be used multiple times is. 4. Device according to claim 1, characterized in that the securing device ( 40 ) is a register. 5. Device according to claim 1, characterized in that the state changing device ( 880 ) for changing the state of the relevant one bit is an inverter. 6. Device according to claim 1, characterized in that the securing device ( 40 ) and the state changing device ( 880 ) are connected to one another in such a way that the address actually stored by the relevant securing device is the address of the next instruction following the relevant last instruction. 7. Device according to claim 1, characterized in that the securing device ( 40 ) is a register with a plurality of bit positions, that the state changing device ( 880 ) is an inverter and that a connecting device is provided which connects the inverter with a location of the relevant register connects in such a way that the state of the relevant bit can be changed. 8. Device according to claim 7, characterized in that each registry office of the registry in question has an input and an output and that the Inverter with the input side of the relevant register connected is. 9. Device according to claim 7, characterized in that each registry office of the registry in question has an input and an output and that the relevant inverter connected to the output side is.