CA1138118A - Next address generation logic in a data processing system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

In a data processing system whose operation is under the control of firmware words stored in a control store, a technique is provided by which a routine which has been temporarily suspended may be returned to. The address of the last instruction executed in such routine prior to such suspension is stored and the routine is returned to by the use of such stored address with one bit thereof changed in state by use of an inverter.
The control store is addressed by means of next address generation logic which includes a first multiplexer utilized to address the control store, which multiplexer has several inputs, One of such inputs is received from a latching mechanism which allows more than one test condition to be simultaneously utilized for addressing the control store on a free flow basis. These test conditions, as well as information from an addressed control word, are utilized in a multiplexed arrangement as one input of the first multiplexer. By use of other inputs of such first multiplexer, the control store may be addressed by use of branch address information, as well as other test condition information.
A page register provides the page address, to a plurality of pages included in this control store with the locations in each such page addressed by use of the above noted multiplexer combination.

Description

113811~

The present invention relates to data processing systems and more particularly to control ~tore addressing architecture associated therewith.
Most data processing systems now include control stores which include so-called f~rmware in order to control the operation of such systems. Included in such firmware are several main line routines and, in addition, subroutines which are shared by the main line routines. When switching ; from a main line routine to a subroutine or when suspending the operation of a routine for any reason, the address of the next location or instruction in such routine must be saved in order to insure return to the proper instruction ' of the routine which has been suspended. One of the techniques used in the prior art includes the implementation of an address incrementer and a return address register. Using this implementation, when a subroutine entry is performed, the incremeDted address is saved in the return address register as the address for the control store upon return from the subroutine. As can be seen, this prior art apparatus requires incrementer logic, as well as associated control logic, which, although adequate, does consume physical space and increases the cost in the manufacture of the particular system.
The control stores are addressed based upon the contents of control store words as well as other inputs depending upon the operation being executed in the ~ata processor. In such 113811~

next address generation logic it is i~portant that the status of more than one test condition be simultaneously utilized to address the control store. If this were not provided, it would require loading of each one of these status or test conditions into, for example, a register on a clocked cycle basis. This would have to be done each time these test conditions change. It is accordingly desirable to test more than one such function, up to four such functions for example, simultaneously without having to load them into a clocked register. By providing such capability, the addressing of such control store is faster, and, accordingly, the overall performance of the data processor is increased.
It is accordingly an object of the present invention to provide an improved control store addressing mechanism for use in a data processing system.
According;to the present invention, there is provided data processing apparatus comprising:
A. logic means for performing logical operations on data, including the performing of a first routine and a second routine;

B. storage means having a plurality of instructions stored therein, said instructions-for enabling said logic means to perform said operations in a manner determined by said instructions;
G. means for addressing said storage means;

. .

- -1131~

D. means, included in said logic means, for executing said first routine;
E means for suspending said execution of said first routine in order to execute said second routine;
F. means for saving an address associated with the last instruction of said first routine which was executed at the time oi the suspension of the execution of said first routine, said address including a plurality of bits, each bit having either a first state or a second state; and G. means for changing the state of one of said blts of said address associated with said last instruction prior to returning to the execution of said first routine, in order to address the next instruction o$ said first routine which next instruction foilows said last instruction.
The invention further provides a data processor comprising:
,~. a control store having a plurality of locations, each said location for storing a control word for use in controlling the operation of said processor;
B, first means ~or receiving a plurality of signals indicative of status information of said data processor;
C. second means for receiving an instruction indicative of address information i'or use in addressing said control store;

.

::
. ~ ~

, . .. ..

D. third means for receiving a first portion of an addressed one of said control words;
E. iirst multiplexer means having an output for coupling to said output either said signals indicative of said status information or said selected portion of said addressed one of said control words;
F, means for decoding said iniormation received by : , sa~d second means for receiving;
G. means for selecting either said signals or said selected portion at said output of said first multiplexer means:or for selecting said information received by said second means for receiving as decoded by said means for : decoding;
~` H. second multiplexer means having an output and a ; 15 plu~al~ty ol' inputs, a iirst one of said inputs coupled : to said means i'or selecting and a second one of said inputs coupled to receive a second portlon of an addressed one oi said control words from said control store; and I. means, cc.upled to said output of said second :20 multiplexer means, for addressing said control store by means of one of said inputs received by said second multiplexer means.
In a preierred embodiment, a data processing system includes a control store having a plurality of locations, each of such locations for storing a contr~l word for use in ' ~

11381$~

controlling the operation of the processor. Apparatus is also included for receiving a plurality of signals indicative of status information of the data processor, for receiving an instruction indicative of address information for use in addressing the control store, and apparatus for receiving a first selected portion of~ an addressed one of the control words. A first multiplexer apparatus is also provided, which has an output, which first multiplexer apparatus enables the coupling to the output thereof, such signals indicative of the status information or the first selected portion of the addressed one of the control words. Apparatus is also provided for decoding the information received by the apparatus for receiving the instruction indicative of such address information. A third apparatus is provided for selecting either the signals or the first selected portion at the output of the first multiplexer apparatus or for selecting the inlormation received i'rom the apparatus for decoding. Second multiplexer apparatus is provided having an output and a plurality of inputs, a first one oi' the inputs coupled to the apparatus for selecting and a second one of the inputs coupled to a second portion-of an addressed one oi' the control words from the control store. Further apparatus is provided for addressing the control store by means of one ofthe~inputs received by the second multiplexer apparatus.

The data processing system includes logic for performing logical operations on data, including the performing of a first routine and a second routine, a storage device having a plurality of instructions stored therein, wherein the instructions are utilized for enabling the logic to perform such operations in a manner determined by such instructions, apparatus for addressing such storage means, apparatus included in the logic for executing such routines, apparatus for suspending the execution of the first routine in order ; 10 to execute the second routine, and apparatus for saving an address associated with the last instruction of the first routine which was executed at the time of the suspension of the execution of such first routine. Such address includes a plurality of bits, each bit having either a first state or a second state. Further apparatus is provided for changing the state of one of such bits of the address associated with the last instruction prior to returning to the execution of the first routine, in order to address the next instruction oi' such i'irst routine, which next instruction follows such last instruction of the first routine.
Arrangements according to the invention will now be described by way of example with reference to the accompanying drawings, in which:-.~:

1~3811~

f-' .5 Figure 1 illustrates the overall system configura-tion which incorporates the present invention;
,: .
. Figure 2 is an operational sequence state diagram : of the processor of the present invention;

- Figure 3 is a block diagram of the processor of the present invention:

Figure 4 illustrates the contents of one of the registers of the processor of thé present invention;

Figure 5 is a detailed block diagram of the arithmetic unit of the present invention;
; 15 Figure 6 depicts a portion of the contents of the control store word used in conjunction with the present invention;
Figures 7A through 7F illustrate the details of the next address generation logic of the present invention;

Figures 8A and 8B illustrate the details of the subroutine logio of the present invention; and Figure 9 is a truth table illustrative of the opera-tion of the logic of Figure 7A.

.. .

:: , .

, ~ ' i138118 ,.. ~"~. ffr ~ q , The purpo4e o~ thc CIP 13 is to expand the CPU 11, sht>wn in the system confi~ura~ion of Figure 1, instruc^
tion sctca~abilities by u~in~3 a powerful set of com-mercial type instructionC;. These instruction types allowthe CPU, via the CIP, to process decimal and alphanumeric data; the instruction types are listed as follows: Decimal, Alphanumeric, Data Conversion and Editing. CIP communi-cation with the CPU and main memory 17 is over a common sy8tem ~us 19. The CIP operates as an attachment to the CPV and receivcs instructions and o~erallds as transfers from the CPU and/or memory. The CIP execute~ the commercial instructions as they are sent over the bus 19 by the CPU 11. The CPU obtains these instructions from main memory, examining each fetched instructlon specifi-cally for a commercial instruction. Receipt of each commercial instruction by the CIP is usually concurrent with the CPU, as the CPU extracts and decodes each instruc-tion from memor~. However, CIP instruction execution is asynchronous with CPU operatiois. Any attempt to execute a commercial instruction when a CIP is not installed in the system causes the CPU to enter a specific trap condi-tion.
The CIP receives infonndtion from the CPU and main memory via the bus 19, and processes this information in a logical sequence. This sequence consists of four CIP
operational states as follows: idle state, load state, busy state and trap state.
As shown in Figure 2, the CIP enters block 200 and remains in the idle state (block 202) when not processing information, and must be in the idle state to accept a , .

- ~` ' '~
:, :

; ~ ~
11381~ .
q,, ~,~ .. .

co~mand ~i.e., a CL~ ins~ruction or an I/O command) from the CPU. On receipt of a command (block 204), if legal lblock 205), the CIP enters the load state (block 206) and remains in thc load state until all associated com-mand information is received. When this information issuccessfully received ~block 208), the CIP enters the busy state (block 210) to process the information. Any further attempts by the CPU to communicate with the CIP
while in its busy state are not acknowledged by the CIP
until it returns to the idlc state again. CIP processing incl~des the communication activity with main memory that occurs when fetching the necessary operand~s). Thc CIP
enters the trap state ~block 212) only when specific illegal events occur ~block 214), such as detection of an illegal operand len~th or an out of sequence command.
Return is made to the idle state if the operation has been completed (block 216).
All pertinent instruction transfers to the CIP
are performed jointly by the CPU and CIP. They are decoded and sent by the CPU to thc: C~P along with all of ; ~ the pertinent information requirecl for execution of the instruction. When the transf~r of the information is completed, the CPU and CIP continue to process their re~pective instructions. ~ach CIP instruction contains a 16-bit wide instruction word th~t is immediately followed with up to six additional descriptive type words ~also 16-bits wide), called data descriptors and labels.
The instruction word contains the CIP op-code that is sent to the CIP for processing. The data descriptors describe the operand type, size, and location-in memory;
the label provides the address of a remote data descriptor.

:
~, , .

, ,. . ~

113811~

Both the data descriptor and the label are processed by the CPU; related information derived by this action, such as an operand type and memory address, is sent to the CIP for processing. The CPU accomplishes the precoding by analyzing the op-code that is contained in each instruction. When the CPU detects a CIP
instruction (i.e., if the CIP is in the idle state), the CPU sends the instruction op-code and the related infor-mation in the following manner: (i) The CPU sends the op-code (i.e., the first word of the commercial instruc-tion) to the CIP. The CIP enters the load state when it accepts the op-code; (ii) The CPU fetches the first data descriptor and interrogates the address syllable to generate the effective address; (iii) The CPU sends the following information: the 24-bit effective byte address of the first operand, the contents of the pertinent CPU data register, if applicable, and the data descriptor of the first operand, updated to reflect a byte (eight bits) or half-byte (four bits) digit position within a word; and as second and third operands are encountered, the CPU performs the applicable procedures in steps ii and iii.
At this point, the CIP is loaded with all of the necessary information required to execute the commercial instruction and enters the busy state to execute the instruction. When necessary, the CIP communicates directly with main memory to obtain the applicable operand(s). Howe~er, it should be noted that the CIP
never directly accesses any CPU registers. It only uses information sent to it by the CPU. Hence, no CPU
registers are modified by the CIP and the CPU continues to process the next and each succeeding CPU instruction until one of the ' ~ 11381~3 ,z ~ .

followintJ cot)ditions occurr-i: (i) The CIP, via a trap vector (TV), noti~ies the cru that an illegal event occurred during the ~xecution of the current commercial in~trUCtiOn; or (ii) an internal ~r external interrupt si~nal is detected by the CPU.
When an interrupt sic3nal is detected by the CPU, the CPtJ performs the following. The CPU determines whether or not the last commercial instruction was com-pleted by the CIP. The CPU waits for completion of the last commercial instruction. When the last commercial instruction i9 completed, the CPU determines if it resulted in a trap request. If it did, the CPU honors the trap ; re~uest before pérforming the interrupt. This results in a typical context save/restore operation to store all relevant CPU and CIP status information, as required.
With the completion of the CPU operations required to process a CIP trap request, or when there is no trap request and a CIP instruction is available for proce~sing, the CPU performs thc following. The CPU updates its pro-gram counter to point to the con~ercial instruction it was a~tempting to initiate. The CPU defers the attempt to proce~s thc commercial instruc~io;- until the current interrupt is serviced. The CPU honors and services the interrupt caused by the external device.
As the CIP executes an instruction, all CPU regis-ters, including those referenced by the current commercial instruction, can be altered by a program via CPU instruc-tions. However, the software must not modify the operand for a commercial instruction until the CIP is through pro-cessing that instruction; otherwise, unspecified results will occur. Branch instructions included in the CIP
instruction repertoire are executed synchronously by the CPU and the CIP.

.

1138~118 The three types of data that make up the data words processed by the CIP are Alphanumeric Data, Binary Data and Decimal Data. Each data type is classified into units of binary information. By definition this unit, when used to reference alphanumeric and binary data characters, equals eight bits (one byte); when used to reference decimal data characters, it equals four bits (half byte) for packed decimal data and eight bits (one byte) for string decimal data. Also, single precision binary numbers consist of two units (two bytes) and double precision binary numbers consist of four units (four bytes).
Figure 3 is a major block diagram of the commercial instruction processor 13 of the present invention, showing all of the major data transfer paths between the processor's registers.
The control storage 10 is comprised of a plurality of locations, one for each control store or firmware word. These firmware words directly or indirectly control the processor sequences, data transfer paths, and bus operations.
The operand register files and arithmetic logic unit (RALU) 12 primarily includes two register files, an arithmetic logic unit (ALU) and the associated multi-plexers and control registers. Included in the RALU 12are the operand register files (RF1 and RF2), each containing sixteen sixteen-bit locations that are used to buffer operands for execution in the ALU. The ALU
input multiplexers and latches are comprised of the following: three 2-to-1 multiplexers (zone selection), two 4-to-l multiolexers (digit selection), and two 8-bit latches (byte latches). These muItiplexers and latches are used to deliver data ~L381~f3 ... .
from the opcrand rcgister fi1cs to the ALU. Data can also bc transferred from thc currcnt product counter to Lhe left side of the ALU or from operand register file 2 to the multiply regi~ter. Thc ~-~it ALU (which is com-priscd o~ two 4-bit ALU chips, a carry look-ahead chip, and a carry in/carry out flip-flop) is capable of per-forming the following opcrations between the left (1) and right (2) inputs: Binary Add, Binary Subtract Input 1 from Input 2, Binary Subtract lnput 2 from Input l, Logical OR, Logical AND, Exclusive OR, Set ALU Output Equal to FF, and Clear ALU Output to 00. The RALU is discussed in detail with respect to Figure 5.
The excess 6 (X56) correction logic of the RALU
lS enabled whenever the ALU is in decimal mode, and is used to change the binary output from the adder to the correct decimal digit while moBifying the carry output for subsequent operations. XS6 correction is accomplished by using a 32-bit by 8-bit PROM chip, which encodes the corrected three high-order bits of the digit and generates the corrected carry. A digit less than two function is also availa~l~ on the output of the PROr~ chip for other controls. The ALU output multiplexer is used to feed either the upper four bits of the adder output or the correct decimal zone bits to thc internal bus 14, depend-ing on whether the ALU is operating in binary or decimalmode, respectively. The RALU control logic consists of three registers, which are as follows: RFlA - Register File l Address Register, RF2A - Register File 2 Address Register and ALMR - ALU Mode Control Register. These registers, in conjunction with several microinstructions, control all operations within the RALU. Besides the ,: ' ~ '~

113~

registers and control described previously, there are two other registers that are classified as RALU registers.
These registers are the current product counter (CPRC) and the multiplier register (MIER), to be discussed hereinafter.
The control file 16, also referred to as register file C (RFC), is a 16 location by 24 bit RAM that is primarily used to store all instruction-related informa-tion that originates from the CPU 11 (e.g., task words, data descriptors, effective addresses, etc.). The control file also contains several work locations which are used by the processor (CIP) firmware. The control file 16 receives bits 0-7 from either internal bus 14 or bus address register (MAR 18 via OR logic multiplexer 21.
The bus address register (MAR) 18 and address adder logic 20 shall now be discussed. The MAR register 18 is a 24-bit address register that is primarily used to address the system bus 19. It is comprised of an 8-bit, two-input multiplexer register on the low end and a 16-bit incre-mentor/decrementor on the high end. The multiplexedinput into the lower eight bits is from either the control file 16 or the output of the address adder 20. The address adder 20 is an 8-bit two's complement adder unit that is primarily used for incrementing or decrementing the contents of the bus address register 18. The-inputs to the address adder 20 are the low-order eight bits of the bus address register and the 8-bit shift register (MSR) 22.
The shift register (MSR) 22 is an 8-bit universal shift register that can be loaded from the internal bus 14 and is capable of shifting left or right by one bit (i.e., open-end shift with zero-fill). The shift register functions as an input to the address adder 20 for ~38118 incrementing or decrementing the bus address register 18.
In addition, bit 0 of the shift register 22 can be loaded into the ALU carry-in flip-flop, which is useful during execution of the conversion instructions.
The bus output data register (OUR) 24 is a 16-bit data register that is used to transfer data onto the bus l9 data lines. It is loaded from the internal bus 14 with either the lower or upper byte or the entire 16-bit word. The bus input data register (INR) 26 is a 16-bit data register that is used to receive data from the bus 19 data lines. The contents of the input data register can be unloaded onto the internal bus 14.
The input function code register (BFCR) 28 is a 6-bit register that is used to store the function code when the CIP accepts any bus l9 input or output command.
Subsequently, firmware examines the contents of the function code register 28 and executes the specified command. The input address bank register (INAD) 30 is an 8-bit register that is used to store the high-order eight memory address bits that are received over the bus l9 address lines. The high-order eight address bits contain the memory module address and are transmitted by the CPU ll as the result of a so-called IOLD command or an output effective address function code. The low-order 16-bits of the memory address are received over the bus l9 data lines and are strobed into the INR
register 26, forming the required 24-bit main memory address.
The CIP indicator register 32 is an 8-bit storage register in which each bit can be individually set or reset. The indicator register bit configuration is shown in Figure 4. The TRP and TRP line indicators are 1~3811~

used by the CIP 13 for internal proaessing only and are not software visible. The TRP line (CIP trap line) indicator is used to inform the CPU 11 of an existing CIP trap condition and is transmitted over the bus 19 via the external trap signal. When set, the TRP (CIP
trap) indicator allows the CIP to accept only input commands from the CPU.
The analysis register (AR) 34 is a 16-bit register that is primarily used to control microprogram branches (masked branches) and the over-punch byte encode/decode logic. This register is loaded with the entire 16-bit word from the internal bus 14. The microprogrammable switch register (MPSR) 36 is an 8-bit register in which each bit can be individually set or reset under micro-program control. Each bit within the MPSR register 36is used as a flag to facilitate microprogramming (i.e., firmware can test each of the register bits and perform branch operations, depending on the test results).
Some of these bits are also used to control certain CIP
13 hardware functions.
The ROS data register (RD) 38 is a 52-bit storage register that is used to store the control store output (firmware word) for the current firmware cycle. The microprogram return address register (RSRA) 40 is an ll-bit register that is loaded from the out ut of the next address generation (NAG) logic 42 and is used to store the microprogram return address when executing a firmware subroutine. The register file C address multi-plexer/selector (RFCA) 31 is a 4-bit, 2-to-1 selector that is capable of addressing one of the 16 locations contained within register file C (i.e., control file) 16.

113811~

This selector 31 selects a combination of the function code register 28 and either counter (1) 46 or selected bits of the ROS data register 38. The CIP counters 44 include three 8-bit up/down counters 46, 48 and 50 that are defined respectively as Counter l (CTRl), Counter 2 (CTR2), and Counter 3 (CTR3). These counters are loaded/
unloaded via the internal bus 14. The contents of each counter are available for test and branch operations.
The overpunch byte decode/encode logic 52 includes two 512-location by 4-bit PROM chips that are used to decode/encode the contents of the analysis register (AR) 34. The byte being decoded is obtained from AR bits 1 through 7 and the digit being encoded is obtained from AR bits 4 through 7. The decode/encode operation is accomplished by using AR bits 1 through 7 to address a specific PROM location. The contents of the specified PROM location are coded to conform to either: (1) the decoded digit, its sign, and its validity, or (2) the encoded overpunched byte. The MPSR 36-bit 4 specifies whether a decode or encode operation is erformed, while MPSR bit 1 indicates the sign of the digit being encoded.
Also, the output of the overpunched byte decode/encode logic is available on both halves of the internal bus 14.
The CIP test logic 54 selects one of 32 possible firmware test conditions for input to the next address generation logic 42. The true or false condition of the function being tested controls bit 50 of the control store next address field (i.e., sets or resets bit 50, depending on the condition of the tested function). The next address generation (NAG) logic 42 included in the CIP 13 uses one of the following five methods to generate 1138~8 the next firmware address: direct address, test and branch, masked branch, major branch, or subroutine return. Direct Address: this method is used when an unconditional branch is performed to the next sequential control store location. This is accomplished by using bits 41 through 51 of the control store word to form the next address. These bits comprise the next address (NA) field, which can directly address any of the available control store locations. Test and Branch: this method is used when a 2-way conditional branch (test condition satisfied) is performed within a firmware page~(a firm-ware page being a 128-location segment within the control store). This is accomplished by using control store bits 41, 42, 43, 44 and 50 to select a test condition. Then, depending on the condition of the tested function, a branch is performed to one of two locations. The branch operation performed under this method is modulo 2 (i.e., the two possible branch addresses are two locations apart).
The modulo 2 address is developed as follows: (1) if the test condition is satisfied, bit 9 of the address is set to a one, or (2) if the test condition is not satisfied, bit 9 of the address is set to a zero.
Masked Branch: this method is normally used when branching on the contents of the analysis register~(AR) 34 or certain other conditions, and provides branching to 2, 4, 8 or 16 locations within the same firmware page (a firmware page being a 128-location segment within the control store). Major Branch: this method is used when branching within a firmware page (128 words). A CPU/CIP interface routine uses this method to perform the required 16-way branch on the contents of the function code register 28.
(INB Major Branch) and other control functions (EOP

li3~
. . ~

¦ Major ~ranch). Subroutine Return: this method is used to return the firmware to the next odd or even control store location after execution of a firmware subroutine. The return address is obtained from the return address (R,SRA) ' 5 register 40, and must be stored in this register 40 prior to execution of the specified subroutine.
The internal bus 14 is 16-bits wide and is pri-I marily used to transfer data between CIP registers, including locations within the register files. The internal bu~ receives data from several sources as shown in Figure 2. Outputs from the internal bus 14 are fed to ¦ various registers within the CIP.
The parity checking logic 56 is coupled between the bus 19 and internal bus 14 and is used to check the parity of the incoming data. The parity generator logic 58, on the other hand, is used to generate the correct parity bit for transfer over the bus 19.
The bus reque~t logic~60 and the bus response log$d 62 are utilized for the purpose of enabling the CIP to gain access to the bus 19 and to respond to any reguests to gain acces~ to the CIP. Logic 60 and 62 are described in U. S. Patent No. 3,993,981.
Pigure 5 is a major block diagram of the RALU 12, showing all major data transfer paths and control lines.
The control lines are shown as dashed lines for ease of understanding its operation. For convenience, the des-cription of the RALU is divided into seven areas: Operand Regi~ter Files, ALU Input Multiplexers and Latches, ¦ Arithmetic Logic Unit, XS6 Correction Logic, ALU Output Multiplexer, ~ALU Control Logic, and Miscellaneous RALU
Registers. Operand register files RFl 70 and RF2 72 each conslst of fourRAM chips that are used as temporary storage for CIP operands. Addresses for each of the register files are supplied by two 6-bit address registers (RFlA 74 and RF2A 76, respectively). Bits 0 through 3 of each address register supply the address of the location within the associated register file, while the low order bits provide for byte and digit selection at the output of the register file. Both of these address registers can be incremented or decremented by 1,

2 or 4 (i.e., by digits, bytes, or words). As shown in Figure 5, the output from each register file is fed to the inputs of two muItiplexers (i.e., a pair of multi-plexers for each register file) that select between zone and digit information. The selection is accomplished by bits 4 and 5 of the associated address register. Bit 4 selects whether bits 0 through 3 or 8 through 11 (from the register file) are fed to the output of the 2-to-1 multiplexers 78 or 80 respectively, while bit 5 selects the register file bits that comprise the digit being fed to the output of the 4-to-1 multiplexers 82 or 84 respectively.
The various registers and multiplexers are coupled for control by various control lines, shown as dotted lines, and including, for example, control lines 71, 73, 75 and 77. A third 2-to-1 muItiplexer 86 is used to select whether the contents of the current product counter (CPRC) 88 or the digit from RFl is delivered to the A latches 90. This muItiplexer is controlled by the ALMR register 92. The ALU input latches, A latches 90 and B latches 106, receive both zone and digit information from the ALU input muItiplexers, and latch the data into the register files during write operations. The outputs from the latch circuits feed the zone and digit information to the left and right sides of the ALU, respectively.
The current product counter (CPRC) is a 4-bit decimal up/down counter that is primarily used during 113811~

execution of decimal multiply and divide operations.
The multiplier register (MIER) 94 is a 4-bit binary up/down counter that is primarily used during decimal muItiply and divide operations. The ALU mode control register (ALMR) 92 ia a 6-bit control register that is used to control all ALU operations. The register file 1 address register (RFlA) 74 is a 6-bit address register that performs two functions: (1) provides addresses for register file 1 (70), and (2) controls two of the three ALU input muItiplexers associated with register file 1.
The register file 2 address register (RF2A) 76 is a 6-bit address register that performs two functions:
(1) provides addresses for register file 2 (72), and (2) controls the ALU input multiplexers associated with register file 2. All arithmetic logic unit (ALU) 100 operations are performed in either the decimal or binary mode. Decimal mode is used when operating with decimal digit information, while binary mode is used for byte (Alpha) operations. Both modes of operation also control 20 the excess 6 (XS6) correction logic 102 and the inputs to the carry flip-flop. In decimal mode, the carry flip-flop is loaded with the carry from the low-order four bits of the ALU, while in binary mode, it is loaded with the carry from the eight bits of the ALU for subsequent arithmetic operations. The carry flip-flop is loaded under microprogram control when a carry must be propagated for subsequent operations. In addition, the carry flip-flop can be loaded from the MSR register, and set or reset under microprogram control.
The XS6 correction logic 102 has one 32-bit by 8-bit PROM chip and the associated control logic to correct the high-order three bits from the digit output of the ALU. XS6 correction is performed if: (1) the ALU
is in decimal add mode and a decimal carry is encountered 1138~

or the digit out~ut of the ALU 100 is greater than 9, and (2) in the decimal subtract mode, if a borrow is encountered (i.e., absence of a carry from the digit portion of the adder). The PROM chip has five address lines. Three of these lines consist of the three high-order bits from the digit output of the ALU, while the other two address lines indicate the type of operation being performed (i.e., add correction, subtract correc-tion, or no correction). The coded contents of the PROM
chip are the three high-order corrected bits of the digit, the corrected decimal carry, and the digit less than 2 condition.
The ALU output muItiplexer 104 selects between the upper four bits of the adder output and the corrected decimal zone bits for delivery to the internal bus. The configuration of the zone bits (for decimal mode) depends on whether ASCII or EBCDIC data is being used (i.e., if ASCII data is being used, the zone bits are forced to a value of 3; if EBCDIC data is being used, the zone bits are forced to a value of F).
The RALU controls consist of registers RFlA 74, RF2A 76, and ALMR 92 plus various RALU related micro-instructions. In addition, the ALU carry flip-flop is under microprogram control. The carry flip-flop can be precleared or preset (as required) by the respective microinstructions, and can be loaded from: (1) the 4-bit digit carry for decimal operations, (2) the 8-bit binary carry for binary operations, or (3) bit 0 of the MSR
register 22 during execution of conversion instructions.
The ALMR register 92, which controls all ALU operations, is loaded from control store bits 2 through 7. Bit 0 specifies whether the ALU operates in decimal 113811~

or binary mode; i.e., whether the carry out of the ALU
is from bit 4 (digit carry) or bit 0 (binary carry).
Bit 0 also controls both the ALU correc*ion (XS6) for decimal operations and the ALU out ut muItiplexer 104;
the multiplexer determines whether the high-order four bits of the ALU or the forced zone bits are gated to the internal bus 14. Bits 1, 2 and 3 are used to control operations within the ALU. Bit 4 specifies whether the zone bits are forced to a value of 3 or F (i.e., for ASCII data, the zone bits are forced to a value of 3;
for EBCDIC data, the zone bits are forced to a value of F). Bit 5 specifies whether the selected digit from register file 1 or the contents of the current product counter 88 are gated to the latches 90 associated with the left side of the ALU. Register RFlA provides the address and controls for register file 1 and the asso-ciated ALU input multiplexers. Register RF2A provides the addresses and controls for register file 2 and the associated ALU input multiplexers.
The control file 16 is divided into two sections:
the upper section (bits 0 through 7) and the lower section (bits 8 through 23). Each section of the control file can be loaded as follows: RFC lower from the internal bus (bits 0 through 15), RFC upper from the internal bus (bits 0 through 7), RFC lower from the internal bus (bits 0 through 15), and RFC upper from the bus address register 18 (bits 0 through 7). The functions used to implement the above operations have an address associàted with them, which address corresponds to the RFC 16 location being loaded. This address originates from either the function code register 28 or the control store 10. Thus, the RFC address is directly related to the type of data being delivered by the CPU 11, or as indicated by the function code.

~,,, il3811~

The CIP firmware word is divided into 14 distinct fields. Although several of the fields occur in identical bit positions within the firmware word format, their functions differ according to the particuIar operation being performed during the current firmware cycle. The 14 fields used for the CIP firmware word are: (1) RALU, ~2) BI, (3) BE, (4) MSCl, (5) CTRS, (6) CIIR, (7) CONST, (8) MAR/MSR, (9) RFCAD, (10) RFCWRT, (11) MISC2, (12) MPSR, (13) BR, and (14) NA. Only fields BR and NA, shown in Figure 6, are pertinent to the next address generation logic of the present invention.
The branch type (BR) field includes bits 37 through 40 of the firmware word. This field determines the type of branch performed as the resuIt of a specific test condition. The next address (NA) field includes bits 41 through 51 of the firmware word. This field is used to either: (1) provide a direct address for the next firm-ware location, or (2) specify the test condition used during generation of the next firmware address, along with its relative address.
The next ROS address is generated as a function of the BR and NA fields of the control store word. A decode of these fields provides the following six microinstruc-tions (plus associated arguments) that ~erform the actual generation of the next address: BUN: Branch Unconditionally, BTS: Branch on Test Condition, BMA: Major Branch, RAS:
Return After Subroutine, BRM: Masked Branch, and BRMEX:
Masked Branch Extended.
The next address generation (NAG) logic 42 is shown in detail in Figures 7A through 7F and includes multi-plexers, PROM chips, registers, and associated logic that, in conjunction with the following ROS Data (RD) register fields, generate a control store (ROS) address. Such ~ 113811!~
.
. 2.~, ~ .

, data register fields include the (1) branch field (RD37BR
through RD40BR), and ~2) the next address field (RD41NA
through RD51NA). These data register fields derive their specific functions from the firmware word. The multi-plexers along wit~h the predetermined registers. (1) selectaddress data from one of the sources listed as follows, (2) form this data into an 11-bit next address ~NEXA00 through NEXA10) field, and (3) route this field to con- -trol store ~ROS) 10 for selection of a specific control store word. The sources from which address data is selected are as follows: (1) analysis regis~er (AR) 34;
(2~ extended mask branch register 700 with its following inputs: (a) microprogram switch register (MPSR) 36, (b) op-code register (CIOPR) 704, (c) counter 1 and counter 2 decode (CTRl 46 and CTR2 48), (d) counter 3 (CTR3) 50, and (e) two sign status indicators (NEGSNF and ILLSNP) or indicator register 32; (3) end operation branch PROM (EOPMB) 706; (4) initial major branch PROM (BINMB) 7C8;
(5) ROS return address reyister (RSRA) 40; (6) ROS addres~
: ~o field (N~XA) 710; (7) ROS page register (RSRGR) 730; and (8) ROS data register (RD) 38. The precise manner in which the NAG logic generates an address is described hereinafter.
The following provides a functional ~escrlption of the registers and PROMs that are directly associated with the NAG logic. The analysis register (AR) 34 is a 16-bit register thatis primarily used with a masked branch (BRM) instruction to provide the necessary microprogram branches within the contro store ~ROS) 10. The AR register is also used to implement the overpunch byte decode/encode operation. Data from the internal bus (BI) i5 available to the AR register with the execution of a BARFBI microinstruction (i.e., load AR from BI). Data from the AR register 34 (or the ~ ' .

~138~

, 2~

extended mask branch register 700) is selected and gated onto the AR test condition (AROOTC through AR15TC) field by RD register 38 bit (RD37BR).
` The extended mask branch xegister 700 is a 16-bit register. It is used exclusively with the extended mask ; branch (BRMEX) instruction to transpose pertinent com-~'i mercial instruction processor (CIP) functional data from selected registers and counters to the AR register 34 ~- outp~ut test condition (AROOTC through ARlSTC) field for control store address modification or generation. The selected registers and counters are as follows:
(1) microprogram switch register 36: This register provides - the applicable microprogram control flags (MPSROO through MPSR03) for firmware interrogation, (2) op-code register ~ 15 704: This register retains the applicable CIP instruction ; word op-code (CIOPRO through CIOPR5) field, (3) counter 1 46 and counter 2 48 decode: These counters provide test conditions for specific microprogram test and branch con-ditions, (4) counter 3 5~ (bits 6 and 7): counter 3 (bits 6 and 7) provide for offset checkout, and (5) sign condi-tions: The sign conditions provide the negative sign (NEGSNF) and the illegal sign (ILLSNF) codes.
When a major branch (BMA) or a masked branch (BRM) instruction is executed, control signal RD37BU is false.
Thisdisables the transfer of the preceding functions (items 1 through 5) into the extended mask branch register and enables the output from the AR register. Subsequently, the decode of an extended mask branch (BRMEX) instruction makes signal RD37BR true, disables the output from the AR register, and enables the output from the extended mask branch register.
.

. .:

....
z,~ ' ~ .

The microprogram switch register 36 (MPSR) is an 8-bit register that uses each bit individually or groups of bits collectively as flags for microprogramming or for firmware test and branch operations. The output from the ~PSR is distributed to the extended mask branch register and the binary collector multiplexers 712 to modify or ' generate a control store address. In addition, selected outputs from the MPSR 36 are distributed to the following CIP logic elements to perform the indicated functions:
10 (1) overpunch decode/encode logic 52; wher,e (a) MPSR01 defines the operand sign (zero = positive (+) sign; one =
nesative (-) sign) and (b) MPSR04 defines the type of decode/encode operation (zero ~ decode operation; one =
encode operation); (2) data status accumulator: MPSR05 forms the address to status accumulator PROM; and (3) RALU:
MPSR07 is used for the multiplexer 10's complement PROM
' during MIER loading.
' Data sent into the MPSR 36 is obtained from and ' , con,trolled by the ROS da,ta (RD) register 38 miscellaneous ~ 20 co,ntrol (RD32MS through RD36MS) field. Signal RD32MS
,, provides the firmware data for the MPSR input llnes. It ; - is made available to the respective MPSR output line by a 3-bit binary code on the select (SEL) input lines to the register. This 3-bit binary code is provided b~ firmware via RD miscellaneous control (RD~3MS through RD35MS~
signals. The actual data transferred to the selected output line occurs when signal RD36MS is true and with the negative transition of MPSREN- on the clock (C) input line to the register.

The op-code register 704 is a 6-bit register (CIOPR0 through CIOPR5) that holds an op-code from a CIP instruct1on , .

.

,.i 113811 2q .
' ' .
word for ultimate,address modification of a control store address. This op-code resides in the hexadecimal c~de field (bits 10 through 15) of the instruction word. The op-code register monitors internal bus bits BI10 through BI15 for this field. When the op-code register receives this field, it is sent to the extended mask branch register 700 and to the end operation PROM 706 where it is used in the generation of the next address (NE.YA) field.
Internal bus data is strobed'into the op-code register 704 on the positive transition of its clock (C) input line via signal LCIOPR. This signal is generated by decoding the output of the RD register 38 when: (1) the decoder input addrèss field (RD17KT through RDl9~T) equals a binary 8, (2) an RD register to BI load operation is not in progress (i.e., the unload (ULKNST) signal is low), and (3) with the positive transition of the next clock 1 pulse.
Three 8-bit counter configurations called counter 1 (CTRl) 46, counter 2 (CTR2) 48, and counter 3 (C~R3) 50 'provide the NAG logic Wit}l the following four test con-ditions that are used for specific test and branch operations described hereinafter: less than 8 (CTR3L8), less than 4 (CTRlL4), CTR2L4, and CTR3L4, less than 2 (CTRlL2, CTR2L2, and CTR3L2, and equal to o (CTRlE0, CTR2E0, and CTR3EO). The baslc configuratlon for each ~f the three counters,is the same. Hence, the follo~ing .
counter description is confined to CTRl 46.
' Internal bus bits 00 through 07 provide source data for each counter configuratlon. The least significant five data bits of byte 0 of BI
(BIDT03 through BIDT07) or all eight BI data bits of byte 0 (~IDT00 through BIDT07) can be loaded into the counter at any one time as determined by the firm-ware. The firmware selects the 5-bit or 8-bit load :. .

' ~3811~

3C) ,.;; . , , via the RD register constant (KT) field bits RD16KT
through RD23KT. The counter is incremented or decre-mented by a negative-going pulse on its respective count-up or count-down input line while the opposite line is held high. Data from counter 1 is used to decode one of the preceding test conditions from its associated PROM. The selccted information is then dis-tributed to the extended ma~k branch register 700 and the binary test collector multiplexers 712 where it is used to ~orm the next address (NEXA) field.
The ROS return address register (RSRA) 40 is an ll-bit register that is used to store a microprogram return address. This return address is contained in the next address (NEXA00 through NEXA10) field to con-trol store and, when stored in the RSRA register, can only be accessed by a return after subroutine (P~AS) instruction. Data from the next address field is strobed into the RSRA register on the positive transi-tion of its clock (C) input line via signal MISRAD.
The binary test logic 54 consists of four multi-plexers and the associated c;ating logic, and is used exclusively with a branch on test (BTS) instruction.
Thc logic selccts one of 32 possible firmware test conditions and routes the selected test status ~RSTSTT) signal to the next addres, generation logic 42 for use in the generation of a control store address. Actual test selection is performed by the mo:,t significant four bits of the RD register next address field, i.e., (RD41NA through RD44NA) and RD50NA. For examplc, to select the less than four status fro:n CIP counter 2 (CTP~2L4), the firmware encodes this NA field with a binary 3 (i.e., t~lrns on RD43NA an~
RD44NA, and turns off RD41NA and RD42NA, and also 3l turns on RD50NA). This transfers the test results from microprogram switch registcr bit 7 (MPSR07) and CTR2L4 to multiplexer output signal lines RSTST0 and RSTSTl, respec-tively. RSTST0 and RSTSTl in turn activate the corresponding wired OR output signals RSTSTE and RSTSTD. RSTST2 and RSTST3 are disabled due to RD41 being off. RD41 is fed through an inverter 713 to the ena~le lnput of the multiplexers corres-ponding to RSTST2/3. However,with signal RD50NA true, further transmission of output signal RSl'STE is inhibited by the AND gate 717 since RD50~A is inverted by inverter 719 and the negation thereof is fed as one input of gate 717, while transmisslon of output signal RSTSTD is enabled by the AND gate 715 to activate signal RSTSTT to the next address generation logic. This enables signal RSTSTT to reflect the true or false state of CTR2L4.
A control store address is generated by using the next address generation (NAG) logic 42 in conjunction with the address lines to the control store (R~S). The NAG logic is designed to collcct pertinent information - 20 from selected CIP sources, form this information into an -c ll-bit next address (NEXA00 through NEXA10) field, and route the field to thc corresponding control store (ROS) address lines. Selecting and routing this infor~ation is initiated and controlled by the following six CIP
branch instructions: ~ranch Unconditionally ~BUtl), aranch on Test Condition (BTS), Return After Subroutine ~R~S), Major ~ranch ~B~), Masked Branch ~BRM), and Extended Mask Branch ~BRMEX). All branch instructions are encoded in the RD register branch ~RD37BR through RD40BR) field.
Note that bccause the RD register receives firmware infor-mation from the control store, it is also called the control store word. The manner in which each instruction and the NA~, logic performs its assigned task to form a control store address is described as follows, it being 11381~3 noted that the term firmware page is defined as a 128-word segment within the control store.
An unconditional branch instruction (BUN) is used to address the next sequential location in the control store 10. The firmware forms this address in the RD
register next address (NEXA) field. The RD register branch (RD37BR through RD40BR) field is set to zero for the BUN instruction. T.~hen the NAG logic decodes this instruction, the next address control (NEXAS0 and NEXAS1) signals and the RAS instruction control (NEXRAS) signal remain false. This places a zero at the select (SE l) input lines to the BUN multiplexers, which in conjunction with the associated gating logic, formulates and sends the above next address field to the control store. Also, with control signal NEXASl false, the most significant four bits from the next address (NEXA00 through NEXA03) field are strobed into the page select register 730 on the positive transition of its clock (C) input line via signal RSPGCK. The page select register pro-vides the firmware page number in control store 10 forsubsequent use with a BTS, BRM, or BRMEX instruction.
A branch on test condition (BTS) instruction is used to perform a 2-way branch within a firmware page.
It accomplishes this with bit 9 of the next address field (i.e., NEXA09). Bit 9 describes the true/false status of one of 32 possible test conditions selected by the binary test logic 54, and is used to modify a firmware-generated page address as it is formed in the next address (NEXA) field and sent to control store 10. The RD register BR field is set to a binary 1 (i.e., RD40BR is on) for the BTS instruction. The four most significant bits of the NEXA (RD41NA through RD44NA) field must contain a 4-bit binary value to select the desired test results. When the NAG logic decodes this instruction, NEXA control signal NEXASl ~_ 113811~

~ , , goes true and the NEXA contxol signals NEXAS0 and NEXASl remain false. This sets a binary l at the select (SEL) input line to the BTS multiplexer, and - enables the page select register and the associated gating logic to form and send the above next address field to the control store.
The return after subroutine (RAS) instruction is used to return to either the odd or even control store location, which corresponds to the address saved in the RSR.~ register, after the execution of a firmware subroutine. The return address is obtained from the return address register 40, and must be stored into this register prior to execution of the firmware subroutine.
Execution of the RAS instruction transfers this address from the return address register ~RSRA) to the NAG logic to form the next address (NEXA) field for a con~rol store address. The RD register BR field is set to a ~inary ~0 for the RAS instruction. When the NAG logic decodes this instruction, NEXA control signals NEXAS0 and NEXRAS
are true. Control signal ~lEXASO sets a binary 2 on the select (SEL) input line of the RAS multiplexer for the six least significant bits from the RSRA register (i.e., RSRA05 through RSRA10). Control signal NEXRAS enables bit 4 ~RSRA04) from the RSRA register through the NAG
gating logic. The four most significant RSRA register bits (RSRA00 through RS~.03) are enabled with RD39BR
true on the select (SEL) input line to a second RAS
multiplexer. This action forms the NEXA format for a control store address.
The following description for the major branch (BM~), masked branch (~R~), and extended mask branch (BRM~X) instructions assumes that the analysis and pa~e .

811~ `-select registers contain the applicable address data required to form a next address (NAl field. The BMA, BRM and 8RMEX instructions use the same NAG logic as the preceding ~i.e., BUN, BTS and RAS) three instructions to generate and format their respective next address fields. The firmware selects and executes one of the three branch instructions by encoding both fields with the applicable code (instruction~data source). When the NAG logic decodes an instruction, it examines both fields (BR/NA) to determine the type of branch instruction and its data source; it then conditions the logic. For example, when the firmware initiates a BMA instruction, using the initialmajor branch PROM /08 for its primary data source, it encodes the RD register branch field with a binary 5 and sets the applicable bits in the NA field, outlined above, to zero. When the NAG logic decodes this instruction: (1) it encodes a binary 3 (NEXAS0/NEXASl true) on the ~MA multiplexer select (SEL) input line for data from the initial major branch PROM, (2) it enables the output from the page select register (NEXAS1 true) ` and bit 45 (RD45NA) from the RD register (NEXRAS false), and (3) it selects (ENBMA) the initial major branch PROM
via signal RD40BR+. This forms the next address field for a control store address as shown in the preceding BMA-NA instruction format illustration. Note that the initial branch PROM is selected through a major branch decoder 732, which is enabled when RD register bits 41 through 44 are set to zero as previously described.
' ' :

.~ ': `

3811~

~3S

The BRM and BR~EX masked branchcs are very similar in nature. The only diffcrence between the two being - that the BRM is based on the contents of the analysis register 34 of Figure 7B, and the BRMEX branch, which is the extended mask branch, is based on the contents of the extended mask branch register 700 which has as its inputs some dedicated CIP control hardware. For both the BRM and BRMEX branches, RD38 of register 38 (nD38BR) has to be true, and for distinguishing between BRM and B~ ~X bit RD37 is off for BRM and on for BRMEX.
For ease of explanation, only the BRM branch will be explained here and the analogy will be made with the BRMEX and its associated hardware.
With RD38 true, the hardware decodes this branch instructlon as a BRM. The BRM is based on the contents of the analysis register 34, which is a 16-bit register described previously. This register 34 can be inter-preted as including four digits, digits 0, 1, 2 or 3, digit O
being bits O to 3 and digit 3 being bits 12 to 15.
'O While executing the BRM instruction, bits 39 and 40 of RDBR control the digit select of the analysis register.
For example, if RD39 and RD40 were O and 1 respectively, - then, digit 1, that is, bits 4 through 7 of the analysis register, would be selected for testing. Now that bits 4 through 7 have been selec~ed for testing, as the name applies, ~ mask has to be provided for these bits to mask out the bits to be tested. By being able to mask these bits, the B-RM has thc capability of branshin~ on a two-way branch, a four-way branch, an eight-way branch or an en~ire ~ixteen-way branch, if all four bits of that selec ed digit are being tested.

;~ :

.;
1138~
.
~3~

The mask which controls the bits to be ~ested in . the analysis register is provided by RD41NA through RD44NA. Now, for example, if bits 4 and 5 of ~he analysis.register.34 were to be tested, then bits RD39BR and 40 would be O and 1 respectively, and bits RD41NA and 42 would both be true, whereas bits 43 and 44 would be false, thereby giving a mask of 1100, a hexidecimal ~hex) C, indicating that bits 4 and S of the analysis register are to be tested. This is accomplished 10 via the multiplexers 734 and 736 of Figure 7B. The multipiexer 734 has as its inputs the 16 bits AROOTC
through AR15TC, which is basically a wired OR function of either the outputs of the analysis register 34 or the outputs of the extended mask branch register 700. On the select input of such multiplexer 734 are the bits RD39BR and RD40BR. Produced at the output of the multi-plexer 734 are the selected four bits or selected digit of the analysis register controlled by RD39 and RD40.
; . The mask which is contained in RD4lNA through 44 controls whether the bit selected from the digit of the analysis register or the corresponding bit from RDNA46 through 49 is to be taken to generate the NEXA for the next address. This selection by the mask of the corres-ponding bits in the analysis register is accomplished by the multiplexer 736 in Figure 7B. As shown in such Figure, the selection is controlled by bits RD41 throu~h 44 and the selection is between the output of the multi-plexer 734 NEXARO through NEXAR3, or the corresponding bits from RD46NA through RD49NA. The corresponding bits . 3n of the NEX~ field are selected such that if the mask bit is on, then the corresponding bit of the selected digit of the analysis register is taken to generate the NEXA

113Z~3~18 field. If the corresponding bits of the mask in RD41t~A through 44 are off, then the corresponding NFXA
bit is ta~en from the field RD46NA through 49.
These four bits, which are the result of the BRM
or B.~A microinstructions, are used to generate the bits NEXh05 through NEXA08. Taking, for example, the genera-tion of NEXA05, NEXA05 would be true if RD41NA is true and the selected bit of the digit, basically NEXAR0, is true. Or, if RD41NA is false, then the bit RD46NA would be selected to generate NEXA05. Thereby, this micro-instruction BRM, as well as the BRMEX, have the capability of branching either on a two-way brOnch by testing only one b~t, or to the other extreme, a sixteen-way branch by testing all four bits of the digit selected.
- 15The extended mask branch is very similar to the B~5 branch, except that instead of taking the output of ;~ the analysis register as the selected digit, it selects one of the groups of test conditions out of the extended mask branch register 700.- The final output of the multiplexer 736, which i.s the result of the masked branch, NEX~'~5 throu~h NEXMK8, is wire ORed with the corresponding bits for the initial branch from the PROM 708 and the End Operation branch from PROM 706. The major branch BMA is also similar to the B~ and the BRMEX, except that it requires mask in RD41 through 44 to all zeros. The bits : RD3g and 40 via decoder 732 select one of four possible branch PROMs of BMA conditions to generate the next address. In the case of the BMA, it is always an uncon-ditional sixteen-way branch. Bits RD46NA through RD49NA
are not used during the B.~A operation, however, if further major branch conditions were necessary these bits could have been used to code more BMA conditons.

' ' ' ' ::

.
` 1138'1~8

3~
~ .

The subroutining mechanism of the CIP shall now be described. With reference to Figure 8, the main line - process starting in block 801 shares the subroutir~e in blocXs 841, 842, etc., with the main line process starting in block 871. In order to share a subroutine between two or ~r.ore main line firmware processes, a return address has to be stored before going to the subroutine. This firmware return address is stored in the register RSRA 40 under control of the microinstruction save return address (SR~) which i5 used to clock the register RSRA 40. At the execution of the SRA microinstruction;, the 11 bit~ of the next address are clocked into the register RSR~. For exam.ple, taking the flow starting in block 801, in block 801 the SRA microinstruction is executed. This micro-instruction saves the address of the next sequential location in firmware, for example address 400, as shown for block 802. At block 802 an unconditional branch or a testing branch, whatever the case may be, is made to the sllbroutine of block 841. The subroutine is now executed, starting in block 841, and then 842, etc., untiI the end of the subroutine at block 843. A return after subroutine (RAS) microinstruction is then executed, as shown in the block 843. This microinstruction forces the NEXA to corre~pond to the contents of the RSRA
reqister. While making the return, since address 400 is saved in the RSRA register, the low order bit of that address in RSRA is invertcd via inverter 880, to corres-pond to the address 401. The NEXZ~ address then corres-ponds to location 401 and the finnware returns to the ~o location of block 803 which has the address 401. Thus, only th~ low order bit of the RSRA register is inverted to get to the corresponding return address point after the subroutine.

' 1~38118 ~_ i..,~,., ~..
. ~,.`. .
3'~ ' ... .. . ' ' ' In the same analogy, the firmware routine start-ing in block 871 execules the SRA instruction and block 872, which has an address of 503, has such'address 503 saved in the RSRA register. At block 872 an unconditional branch or a testing branch to the subroutine'of block 841 is made. The subroutine is executed to its comple-tion until block R43, where a return after subroutine (RAS) microinstruction is executed. This time the RS~A
register contains address 503 and the low order bit, bit 10, of 'hat register, being a binary l is inverted to a binary 0 to correspond to an address of 502. At the execution of RAS, the return address is now equal to 502 ' and the return is made to block 873 which has the address of 502.
Thus, irrespective of what the contents of RSRA
were at the time the return is made, the low order bit of that RSRA is inverted to form the corresponding return address point for the RAS microinstruction. In such implementation, the low order bit is thereby used for a ! ? subroutining mechanism and gives two address pairs which are the exit from and entry ~to after the execution of ' ; the subroutine. If it is necessary to invert a different - ~ bit, the bit 8 or 9 or any other weight bit, so long as there is one bit inverted to make two corresponding locations for the subroutining mechanism inside the CIP.
This mechanism eliminates the usage of an incrementer in the next address generation logic which is the con-ventional method of subroutining in firmware driven machines. For example, in a normal firmware machine, nominally the next address is incremented and this incremented value is saved in a return address register and this register is used to return to at the execution .

:., . ~ .

~138118 -4C~ .

of the return after subroutine microinstruction. In the ~esign of this invention, the need for such incre-mentPr is completely eliminated and thus an incrementer is r.o longer necessary for firmware addressing. Only one ~it needs to be inverted to make the subroutine mechanism operative.
This subroutining mechanism can also be expanded for the nesting of subroutines, if necessary. In order to make the nesting mechanism, there would be a file of !0 RSRA registers. For example, if there are to be four levels ~f nesti~g subroutines, then there will be four such RSRA registers which could be inside a register fi~e or a last in first out register microcircuit.
Associated with this nested subroutine register file would be a pointer which would be incremented each time a save return address was made pointing to the last return address saved, so that when a subroutine return , is made it will go back in the same sequence as it was saved.
The advantage of having the ROS page register 730 -` is that it provides four high order address bits for the next address of the firmware. If the ROS page register - was eliminated, it would require that the firmware word be increased by four bits to provide the high order 2; 4 bits of the next address. By the present invention, since the 4 bits of the next address are provided by the ROS page register, the corresponding 4 bits of the RDNA
field, that is RDNA41 through RDNA44, can provide further control for the branch microinstructions. For example, in the BTS microinstruction, these bits are used to encode the condition which needs to be tested in this microinstruction, or in the case of the BRM and BR.'~X microinstructions, these bits, bits RDNA41 throu~h RDN~44, provide the 4 bit mask to control the bits of the analysis register to be tested.

1138~
. . . .

4~ .
The firmware page in the apparatus of the inven-tion is 128 words which arc basically derived from the low order 7 bits of the next address, which correspond to bits RDNA45 to RDNA51, which, in turn, correspond to NEXA04 to NEXA10. The firmware is divided into pages o~ 128 words, the philosophy of this 128 words per page is that in branches like the BTS, BRM, BRMEX and 8MA, the high order 4 bits of the next address field are directly coupled from the 4 bits of the ROS page register. Since the next address field is 11 bits, that leaves 7 low order bits of the-next address which are generate~ as a result of the address generation logic corresponding to these branch microinstructions. Since the high order 4 bits of the next address are constant during execution of these microinstructions and are from the ROS page register, it leaves only 7 bits to be manipulated for next address generation. Thus, the 7 bits correspond to the 128 words of address base which can be manipulated for these microinstructions.
In the present apparatus, there are, by way of example, 16 such pages of 128 words (2 to the power of 7) thereby giving a total address base of 2048 words of firmware.
The basic savings derived from using the ROS page register is that the control store does not need to be expanded to include the bits corresponding to the ROS
page address and its next address field. If the depth of the control store is, for exa~ple, like in the CIP
it would require two extra chips of PROM which are much more expensive than one chip of the ROS page register.
2; The ~RM~X feature is an extension of the masked branch (BRM) microinstruction. Normally, the BRM
microinstruction provides a capability of branching on more than one bit at the same time, which bits are selected from the contents of the analysis register.
3~ If the BRMEX capability did not exist, and it was neces-sary to test more than one lo~ic function simultaneously in the firmware, it would require a load of these logic :

~Z

.
conditions into the analysis register from where they could be tested with the BRM microinstruction, and this would have to be done each time these logic conditions change and are tested. By providing the BRMEX capability, there exists the ability to test more than one function, up to iour functions for example, simultaneously without having to load them into the analysis register. These logic functions are systematically arranged in such fashion that groups of four correspond to different digits of the analysis register. These groups of four conditions are selected on the basis of the design and their need to be in the same group. These hardware conditions which need to be tested simultaneously, similar to the test BRM, are available in the extended mask branch latch 700 of Figure 7B. Actually, the latch - (or register) 700, is actually a buffer, and more par-ticularly a tri-~tate buffer, (i.e., it is free flowing and is basically used for isolating conditions from the rest of the hardware), which is enabled or disabled for selection of a BRMEX or a B~ microinstruction.
The selection between the BRMEX buffer 700 and the BRM analysis register 34 is controlled by bit RD37BR.
The assertion goes directly to the analysis register enable line and the same bit RD37 is inverted through the inverter 739 and the output of that inverter is gated into the enable pin of the buffer BR~X 700.
As discussed hereinbefore, the selection of the major branch or the analysis register branch BP'I or BRMEX is under control of bits RDNA41 through 44. When 30 these 4 bits are zero, the B.~A microinstruction is enabled. This zero detection logic is block 731 of ; Figure 7B. The decoder 732 is used to decode bits ` . 113~
, , ~ ~ .

:. ' ' .
RD39 and RD40 which are encoded to select one of the four possible major branches. In the present apparatus, only two of the four possible branches are used, i.e., ENB.V~0 and E~BMAl, which correspond to EOP major branch PROM 706 and the initial major branch PROM 708 respec-tively.
With reference to Figure 7C, and with respect to ; ~ the description of counter 1, which is shown in detail, the outputs of the counter 1 being CTR100 through CTR107 are coupled to the PROM chip 47. This PROM chip has on its output th~ conditions of counter 1 equal to 0 (CRTlE0), counter 1 less than 2 (CRTlL2), and counter 1 less than 4 (CTRlL4). This PROM chip is duplicated for each one of the other two counters, namely counter 2 (48) and counter 3 ~50). ~asically, the PROM chip takes all the ~ ~its of the counters and decodes them to determine whether their values are equal to 0, less than 2, less than 4, or in the case of counter 3, less than 8. One reason for using a PROM chip for this logic instead of a typical gating structure, is that it saves physical space. If this decode logic was provided by use of typical hardware (i.e., small scale integrated circuits such`as AND and OR gates) it would have taken about three chips of logic per counter to decode their resp~c-tive values. By using the PROM chip for doing this decode, a significant amount of real estate (physlcal space) was saved.
Fi-gure 7A depicts the final selection of NEY~00 through NEXA10 which, via the ROS address 710, are coupled for transfer to the control store 10. The control func-tions NEX~S0 and NEY~Sl, which are widely used in the logic of this Figure 7A, are explained in the truth table . :: . . .:: :
. : .: . . .
. . :.
: . ~ , .

~ ~ :
':

' 113~
.
~' of Figure 9. Figure 9 is a truth table for generation ` of the two control functions NEXAS0 and NEXASl. In this truth table, the second column contains the different values of bits RD38B~ through RD40BR.

5~ Column 3 contains the possible codes for the control signals NEXAS0 and NEXASl and the corresponding micro-instructions which are generated. For example, NEX~S0 is true, if RD38BR is true, or if RD39BR is true, this corre-:ponds to the codes shown in Column 3 for 100, 101, llO and 111 and also 010 and 011. The first four codes starting at 100 to lll are generated for the three microinstructions BRM, BRMEX and B~, and the code 010 is generated for the microinstruction RAS.
For these four microinstructions BRM, BRMEX, BMA and RAS, NEXAS0 is true. NEXAS0 negation is true for the two codes of 000 or 001, which correspond to the micro-instructions ~UN and BTS respectively.
A similar explanation for NEXASl generation will now be made. NEXASl is true for bit RD38BR being true, or RD40BR being true. This in t~rn corresponds to the codes of 100 through 111 and 001 and Oll. The ~irst - four codes correspond to the microinstruction BRM, BRMEX and BMA, and the codc of 001 corresponds to the microinstruction ~TS. It should be noted that the code 011 is not used at all. Similarly, NEXASl negation is true for the code of 000, or a OlO, which corresponds to the microinstructions BUN and ~AS respectively.
These functions NEXAS0 and NEXASl, along with their negations, NEXAS0 negation and NEXASl neg~tion, are used extensively to control thc multiplexer selection in Figure 7A. A more detailed explanation of Figure 7A, which depicts the generation of NEXA00 through NEXA10 to be uscd for the control store address, will now be made.

: .
.

r , _ :

- ~ , The high order 4 bits, NEXA00 through NEXA03, have a possibility of three inputs and these inputs could ~e either directly from RD41NA through RD44NA, or from the ROS return address register RSRA00 through RSRA03, and lastly from the ROS page register RSPG00 through RSPG03. The selection of RD41NA through RD44NA
is for the microinstruction BUN, which is the uncondi-tional branch, taking the data directly from the ROSdata register. The selection of the ~SRA00 through RSRA03, that is from the ROS return address register, is for the microinstruction RAS. The selection of RSPG00 through RSPG03, that is the ROS base register, is for all other microinstructions which are BRM, BRMEX
and BMA. The selection between RD41NA through RD44NA
and RSRA00 through RSRA03 is accomplished through the - multiplexer 712. The selection of RD41 through RD44 is provided for the microinstruction BUN, which is controlled by RD39BR negative, and when RD39BR is positive, that is it is true, the output of the ~UX is selected from the ROS return address register. The output of this ~SUX is called NART00 through NART03.
The final selection of NART00 through NAR~03 and RSPG00 2; through RSPG03 is accomplished by the enable lines on the multiplexer 712 and the register 730 which is the ROS page register explained earlier.
Referring again to Figure 9, which is the truth table, it shows that NEXASl being true corresponds to the microinstructions BTS, BP~, BRMEX or BMA, whereas NEXASl negation being true corresponds to the micro-instructions BUN or RAS. Hence, NEX~Sl controls the .

:, ::: :
:- -,: ~ :
.~ ., ~ :: ~:
' ' ' '; ', ~ ~ : ' :
' - ~ ' :

rl 1138~8 ~ .

enabling and disabling of the multiplexer 112 and the register 730. If NEXASl is true, that is, there i;
either a BTS, BRM or BRMEX in process, then the ROS~
page register 730 is enabled by the function NEXASl (negative) going negativc. If NEXASl (negztive) is true, which corresponds to microinstructions BUN or RAS, NEXASl going negative enables the multiplexer 712.
The outputs of elements 712 and 730 are wire ORed together and the final output is the low order 4 bits of the ~ext address NEXA00 through NEXA03.
NEXA04 is controlled by the two AND gates 714 and 716. The outputs of these AND gates NEXA04B and NEXA04A
; respectively are wire ORed together to form the address NEXA04. The two ipossible sources of NEXA04 are either the ROS return address register or directly from the ROS
data register R~45NA. The ROS return address register RSRA bit 4 is enabled by the function NEXRAS which is generated for the RAS microinstruction. When NEXRAS
- is true, the output of NEXA04B follows the contents of RSRA bit 4, and is used to generate the output NEXA04.
Whereas if NEXRAS (negation) is true, then the output NEXA04A is enabled and it follows the contents of RD45NA.
These two wire ORed functions NEXA04A and NEXA04B
together form the bit NEXA04 of the next address.
q'he control of the fir.al lo~ order six bits of the next address logic, NEXA05 through NEXAl0 is accom-plished via the multiplexer 718. This mul~iplexer is a l out of 4 multiplexer and is controlled by two control lines, NEXAS0 and NEXASl, which can have values 00, 0l, 10 and ll respectively. These are depicted in the diagram of the multiplexer 718 as being the select code 0, select code l, select code 2 and select code 3. The 4~

select code 0 i~ the casb where NEXAS0 negation is true and NEXASl negation is true. That correspo~ds to the case of the BUN microinstruction which is the unconditional branch. In this case, the contents of RD46NA throuqh RD51NA which are directly from the con-trol store word are enabled on the output to form NEXA05 through NEXA10. The next case when select 1 is trUe, that is NEXAS0 negation is true and NEXASl assertion is true, is the case where the ~TS microinstruc-tion is nabled. In the case of the BTS microinstruction, the six lines which are RD46NA through RD49NA and the final output of the test MUX 712 shown on Figure 7E, as the output of the wire ORed output of elements 715 and 717, along with RD51NA in that order are enabled on the output NEXA05 through NEXA10.
The selection 2, which is the case with any NEXAS0 assertion being true and NEXASl negation being true, . .
corresponds to the microinstruction RAS, which is the return after subroutine miGroinstruction. In this par-- 20 ticular case, the ROS return address register, bits 05 ; through 09, and the ROS return address registe, RSRA10 negation, is enabled on the output NEXA05 through NEX~10.
The final select output control 3 is the case where NEXAS0 and NEXASl are both true. This is the case for the ~25 microinstructions BRM, B~X and B~'~. In this case, the ! NEXM05 through NE~108, which are the outputs of the mutliplexer 736 of Figure 7B, along with RD50NA and RDSlNA, are enabled onto NEXA05 through NEXA10. Thus, the multi-plexer 718 controls the output for NEXA05 throush NEXA10 for the next address generation. Finally, these 11 bits, NEXA00 through NEXA10, from the ROS address as depicted in the block 710 are coupled to the control store for completion of the next address.

:: :

': -' ' :

Claims (10)

CLAIMS:-

1. Data processing apparatus comprising A. logic means for performing logical operations on data, including the performing of a first routine and a second routine;
B. storage means having a plurality of instruc-tions stored therein, said instructions for enabling said logic means to perform said operations in a manner determined by said instructions;
C. means for addressing said storage means;
D. means, included in said logic means, for executing said first routine;
E. means for suspending said execution of said first routine in order to execute said second routine;
F. means for saving an address associated with the last instruction of said first routine which was executed at the time of the suspension of the execution of said first routine, said address includ-ing a plurality of bits, each bit having either a first state or a second state; and G. means for changing the state of one of said bits of said address associated with said last instruction prior to returning to the execution of said first routine, in order to address the next instruction of said first routine which next instruc-tion follows said last instruction.

2. Apparatus as in Claim 1 wherein said one of said bits is the least significant bit of said bits com-prising said address.

3. Apparatus as in Claim 1 wherein said storage means is a control store and wherein said instructions are firmware words.

4. Apparatus as in Claim 1 wherein said second routine is a subroutine which may be shared by said first routine and other routines.

5. Apparatus as in Claim 1 wherein said means for saving is a register.

6. Apparatus as in Claim 1 wherein said means for changing the state of said one of said bits is an inverter.

7. Apparatus as in Claim 1 wherein said means for saving and said means for changing are coupled so that the address actually saved by said means for saving is the address of the next instruction following said last instruction.

8. Apparatus as in Claim 1 wherein said means for saving is a register having a plurality of bit posi-tions, said means for changing is an inverter, and further comprising means for coupling said inverter to one said position of said register in order to change the state of said one of said bits.

9. Apparatus as in Claim 8 wherein each of said positions has an input and an output and wherein said inverter is coupled to said input.

10. Apparatus as in Claim 8 wherein each of said positions has an input and an output and wherein said inverter is coupled to said output.