DE2952151C2 - Circuit arrangement for the electronic locking or unlocking of security devices, in particular as anti-theft protection in a motor vehicle - Google Patents

Description

State of the art

40

The invention relates to a circuit arrangement of the type mentioned in the preamble of claim 1.

For the electronic unlocking of door locks, it is known that one of a signal transmitter emitted pulse train, which represents a pulse code that can trigger unlocking if it is in a assigned signal receiver is received correctly. Such devices have the functions of mechani see keys. They have the particular advantage that a wide variety of key combinations can be generated purely electronically in one such variety that unlocking by trying code combinations is practically impossible.

Safety devices with status switches are known and commercially available or as the Microtronic Robert Bosch GmbH according to their prospectus WEB 1 AAW 12 15.79. Such safety devices work through the alarm they trigger. she are locked and unlocked with a mechanical key so that the authorized person has access to the Object protected by an alarm is given by the fact that the alarm readiness is switched off. As a result of that these alarm-triggering safety devices armed with a mechanical key or are turned off, there is the disadvantage that the associated mechanical key can be copied relatively easily and that due to the electromechanical Construction is complex to manufacture and the service life is limited.

If a motor vehicle is protected with such safety devices, it has the disadvantage that multiple, separate installations are required, which increases costs.

The invention is based on the object of creating a circuit arrangement which, while retaining the advantages of an electronic key system, has disadvantages of previous safety devices Avoids alarm signaling and which has the advantages that it can be manufactured at low cost and is practically maintenance-free and has a long service life.

The object is achieved according to the invention by the features of the characterizing part of the main claim. The essence of the invention is that a Combination of electronic key and electronic alarm device as a security device in a single circuit arrangement and the functions of signal reception for the Unlocking and monitoring of the status switch are nested in one another so that parallel operation is possible. Because it must not happen that with an advantageous combination of the previous circuit arrangement arises as a new disadvantage that during a Unlocking process, the alarm-issuing protective devices are switched off. That would result have that by using a wrong signal transmitter the unlocking device with reception and

Checking the pulse code is so busy that the Safety devices no longer monitor the status switch. Just putting together an alarming one Safety device with status switches and an electronic key in the way it is the Specifying solution according to the invention can eliminate the previous disadvantages without having new disadvantages.

Advantages of the invention

10

The use of only one circuit arrangement has the advantages of convenient operation, low cost, Convenient installation and a high level of security, as there are no additional connecting lines between different Facilities are necessary.

By stimulating the monitoring of status switches with each received pulse of the pulse code and alternative excitation from a clock generator when the pulses of the pulse code fail, has the The advantage that the status switches are monitored at a very high frequency. Because the allotted time, after which the clock generator takes over the query depends on the pulse intervals of the transmitter. It is unthinkable that there should be means or procedures that work within the short intervals at which the Status switches are not monitored, put the safety devices out of operation.

With the use of the longest of the three pulses of the pulse code as a synchronization signal for the Receiving the pulse train in the signal receiver has the advantage that this synchronization signal with is recognized with great certainty.

The assignment of twice as long pulse intervals for the 1 information compared to the zero information has the advantage that the information bits in the receiver are particularly safe and simple can be distinguished.

The fact that the clock generator is designed so that in the pulse intervals of the output from it Pulse repetition frequency, the pulses of the pulse code fall, it is advantageously achieved that the circuit arrangement from impulses emitted by the transmitter reacts quickly Would there be a possibility that the impulses of the Pulse codes emitted by the transmitter can be assigned a frequency which is a harmonic of the is the pulse frequency emitted by the clock generator, it would be conceivable that all synchronizing pulses and so that the key function is lost.

By inserting a time circuit that examines the pulses of the pulse code for a minimum width, so all short interference pulses are advantageously masked out, so that only pulses of the pulse code have an effect can come.

The monitoring of the status switch in a time interval in which there is no pulse of the pulse code is received, has the advantage that interference pulses that occur during this time are not taken into account. Such glitches can occur despite the lock for too short pulses that from any Interference source longer pulses than provided by the transmitter are emitted.

According to the features from the characterizing part and the features of the subclaims, it is possible a circuit arrangement according to the invention not only with discrete logic elements but also with a highly integrated one Build the mold using a single chip processor, which is a particularly advantageous one Embodiment of the invention leads.

drawing

Further features and advantages of the invention emerge from the following description of two Embodiments, on the one hand using discrete logic elements and on the other hand using a single-chip microprocessor. It shows:

F i g. 1 is a block diagram of a signal generator using discrete logic elements,

2 shows a functionally identical signal generator below Use of a single-chip microprocessor,

F i g. 3 shows a program flow diagram for a signal transmitter with a microprocessor,

Fig.4 using a signal receiver discrete logic elements,

5 shows a signal receiver with the same function using a single-chip microprocessor,

F i g. 6 is a flow diagram of the program stored in the microprocessor of the signal receiver.

In the transmission device according to FIG.], A switch 1 is connected via a line 2 to an input 3 of an initialization circuit 4. An output 5 of the initialization circuit 4 leads via a line 6 to the reset input 7 of a counter 8 and also to the reset input 9 of a flip-flop 10. A transmission output 11 of the counter 8 is connected to the set input 13 of the flip-flop 10 via a line 12. An output 14 is connected to a blocking input 16 of an amplifier 17 via a line IS. An output 18 of the initialization circuit 4 is connected to an input 20 of an OR gate 21 via a line 19. An output 22 of the OR gate 21 is connected to a set input 23 of a timing element 24 via a line 25. An output 26 is via a line 27 with an input 28 of an OR gate

29 and is also connected to the reset inputs

30 and 31 of the counters 32 and 33 are connected. An output 34 of the OR gate 29 is via a line 35 with an input 36 of a pulse shaper 37 is connected. An output 38 of the pulse shaper 37 is via a Line 39 is connected to an incremental input 40 of counter 32. A transmission output 41 of the counter 32 is connected to an incremental input 43 of the counter 33 via a line 42. A carry output 44 of the counter 33 is connected to an input 46 of a pulse shaper 47 via a line 45. A Output 48 of the pulse shaper 41 is via a line 49 to an input 50 of the OR gate 21 and with an incremental input 51 of the counter 8 is connected. An output 52 of the pulse shaper 37 is via a Line 53 is connected to an input 54 of amplifier 17. An output 55 of the amplifier is via a Line 56 is connected to a light emitting diode 57. Outputs 58 of the counter 30 are connected via lines 59 Inputs 60 of a diode matrix 61 connected. Outputs 62 of the counter 33 are connected via lines 63 Inputs 64 of the diode matrix connected. Outputs 65 of the diode matrix are connected via lines 66 Inputs 67 of an OR gate 68 connected. An output 69 of the OR gate 68 is via lines 70 connected to an input 71 of an inverter 72 and to a set input 73 of a timing element. A Output 75 of the inverter is connected to a set input 77 of a timing element 78 via a line 76. An output 79 of the inverter 74 is connected to an input 81 of the OR gate 29 via a line 80. An output 82 of the timing element 78 is connected to an input 84 of the OR gate 29 via a line 83

tied together. An output 85 of the pulse shaper 37 is connected via a line 86 both to a set input 87 of the timer 78 and to a set input 88 of the timer 74.

The function of the circuit is as follows:

When switch 1 is actuated, a signal is sent to input 3 of the initialization circuit, which then emits a pulse that resets both counter 8 and the flip-flop via line 6. Another pulse of the initialization circuit arrives via the line 19 through the OR gate 21 on the line 25 and thus on the set input 23 of the timer 24. This has a running time of 20 msec. At its output 26 a correspondingly long pulse arises which resets the counters 32 and 33 via the line 27 and also causes the pulse shaper 37 via its input 36 to emit a pulse at its output 52. This pulse has a width of about 100usec and is a pulse of the pulse code to be output, namely the start pulse. The pulse generated by the pulse shaper 37 reaches the amplifier 17 via the line 53 and drives the light-emitting diode 57 via the line 56. This emits a light pulse whose length corresponds to the pulse duration of the pulse shaper 37 a set signal to the timers 74 and 78. Only one of the two can be set, according to the logic state at their set inputs 73 and 77. For the start or synchronization step of the pulse code, the pulses emitted by these timers fall within the running time of the timer 24, so that they do not come into effect. Likewise, this first pulse of the pulse code cannot be used to advance the counter 32, since this counter is held reset by the pulse of the timer 24 via the reset input 30.

After the period of time specified by the timer 24 has elapsed, the pulse shaper 37 triggered again. It now emits an impulse that triggers one of the timing elements 74, 76 with its leading edge with its trailing edge, the counter 32 advances from the initially held 0 position to the 1 position In addition, a signal of the pulse code is sent out for the amplifier 17 and the light-emitting diode 57 which indicates the end of the synchronization interval

Which of the two timing elements 74, 78 was triggered depends on which set input 73, 77 had the level that is necessary for switching on the timing elements Counters 32 * 33 is controlled line by line and column by column. Sitting in the intersection of the row and column lines of the counters 32-33 in the diode matrix is a diode, it is through the OR gate 68 and the inverter, the timer is activated, having the longer duration, it immediately occurs a rising edge, in turn, the Pulse shaper 37 could trigger again via its input 36. However, since the pulse shaper 37 is still running, this edge remains ineffective for a pulse generation in the pulse shaper 37. The pulse shaper 37 is only addressed again by the trailing edge of the pulse that is generated by the addressed timing element. Another pulse of the pulse code results. At the same time, the counter 32 is incremented via the incremental input 40. As soon as it emits a carry signal at its output 41, the counter 33 is incremented via the incremental input 43. The individual crossing points of the diode matrix are addressed one after the other by the outputs 58, 62 of the counters 32, 33 and, in turn, control one of the timing elements 74, 78 via OR gates 68 and inverter 62 the pulse intervals vary between 2 and 4 msec according to the bit pattern predetermined by the diode matrix 61, depending on which of the two

! ο timing elements 74,78 was addressed.

Finally, a signal emerges at the carry output 44 of the counter 33 which triggers the pulse shaper 47 via the line 45. A pulse supplied by it switches the counter 8 further and starts the timer 24 again via the OR gate 21 and the line 25, so that the 20 msec long pulse pause occurs for the synchronization step.

The timing elements 74, 78 and the pulse shaper 37 thus act together as a variable clock generator for the pulses of the information part of the pulse code. The timing element 24 cooperates with the pulse shaper 37 and the counters 32, 33 and the pulse shaper 47 to generate the synchronization step of the pulse code.

The output of pulses continues until the

Progress input 51 of counter 8 leads to an overflow of the same. A pulse on line 12 sets flip-flop 10, so that amplifier 17 is blocked via its output 14 and line 15 from now on. A transmission of light pulses via the light-emitting diode 57 does not take place, irrespective of whether the clocking and counting processes continue within the transmission processes. The main power consumer is switched off with the light-emitting diode
Another embodiment of the transmission device according to the invention is shown in FIG. 2, a key 90 is connected to a reset input 92 of a microprocessor 93 via a differentiating device 91. Outputs 94 of microprocessor 93 are connected to a quartz 96 via lines 95.

Port outputs 97 are connected to inputs 99 of a diode matrix 100 via lines 98 . Outputs 101 of the diode matrix are connected to port inputs 103 of the microprocessor 93 via lines 102 . A port output 104 of the microprocessor 93 is connected to an input 106 of an amplifier 107 via a line 105 . An output 108 of the amplifier 107 is connected to a light-emitting diode 109 .

The function of the circuit arrangement according to FIG. 2

This is controlled by the program of the microprocessor 93. Such programs run sequentially in time, so that interlocks, which are necessary for circuits without a microprocessor, can be omitted here. This considerably simplifies not only the circuit complexity, but also the structure of the program.

The following register assignments are made in the microprocessor 93:

SP Stack pointer, A accumulator, B ₁ C time counter, D cycle counter, E shift register, H register pointer for the storage registers £ ', C. D', £ ", // '.

3 shows a flow chart of the microprocessor program. The function of the program is as follows:
With a pulse on the reset input 92 of the microprocessor 93 , the program jumps to the starting point. This starts the initialization process a, which consists in fixing the stack pointer and setting the cycle counter D to a number that corresponds to the number

corresponds to the desired transmission cycles. The initialization program ends at the DSTi node. The program part b sets the shift register f to zero and the register pointer H so that it points to the register B ' , in program part c the registers B', C, D ', f, H' are filled with the contents of the diode matrix 100, that the diode matrix is addressed line by line and each byte of its lines is recorded in one of the registers. A pulse of the pulse code is then emitted with the subprogram pulse (UP pulse). The pulse duration of ΙΟΟμββΰ is achieved with a suitable number of NOP commands. This is followed by the synchronization pause of 20 msec in program part e. For this purpose, the register pair B, C is loaded with a number such that the desired time interval results when the subsequent counting down to zero. After each decrementing step for the register pair B, C it is therefore checked whether zero has already been reached. The program node DST2 is then reached.

After the synchronization pause, another pulse of the pulse code is emitted in the program part / by calling the UP pulse. In program part g , the content of shift register E is loaded into the accumulator and the carry bit is set the first time E is still zero. Thereafter, the accumulator is rotated and its bit pattern saved as a new state of the shift register in the register E then enters a logical link a between the addressed by the register pointer H storage register (B ', C, D', E ', H') and the accumulator. This means that there is a bit in the accumulator at the end of program part b if a diode was set. Otherwise the accumulator is zero. Accordingly, the accumulator is checked for zero in program part h and either a time interval of 2 msec at zero or a time interval of 4 msec at 1 is generated. These time intervals are generated in accordance with the synchronization pause in that the registers B, C serving as time counters are set to corresponding values in order to then be counted down to zero.

In the program part /, after these time intervals, the shift register E is queried as to whether the bit entered with the carry bit has been pushed all the way through the register, i.e., for example, in the case of left rotation, a check is made to determine whether 80 H is in the register. If this is not the case, the program runs back to node DST2. The result is a program loop that runs until the shift register E , which serves as a mask, has read out the content of one of the storage registers B '.. C, D' .. E '.. H' during its multiplication (via the accumulator). Each loop then begins after the node DSTX with the delivery of a pulse. The pulses of the pulse code thus follow one another at time intervals which correspond to the set diodes of the diode matrix 100 in each row.

Once shift register E has run through, register pointer H is incremented by 1 in program part K. Program part 1 then checks whether register pointer // still points to one of storage registers B ', C, D', E ', //' is that still the case, the shift register e is reset to zero in Programmtefl m to the next from the elevated register pointer // addressed memory register query bit. The program continues via node DST2 .

If the register part // has run beyond the memory register, 40 pulse pauses with a length of 2 or 4 msec have been generated. In the program part η the cycle counter D is increased by 1. A further pulse is output in program part t , which serves as the end of the time interval of the fortieth bit of the pulse code. In the subsequent program part q it is queried whether the cycle counter has already reached the number 10. If this is not the case, the program jumps back to the node DST2 and a new sequence of pulses of the pulse code is emitted. If the cycle counter has reached the number 10, the program goes into a »halt« loop.

In the receiving device according to FIG. 4, a switch 201 is connected to an initialization circuit 202. An output 203 of the initialization circuit 202 is via a multiple branching connection 204 with an input 205 of an AND gate 206 and an input 207 of an OR gate 208 and a blocking input 209 of a timer 210 and an input 211 of an OR gate 212 and a Blocking input 213 of an actuation circuit 214 is connected. An output 215 of the OR gate 208 is connected to a blocking input 217 of a timing element 218 via a line 216 . An output 219 of the OR gate 212 is connected via a line 220 to a blocking input 221 of a theft monitoring circuit 222. An output 223 of a receiving amplifier 224 is connected via a connection 225 both to an input 226 of a timing element 227 and to an input 228 of the OR gate 206 . An output 229 of the timing element 227 is connected to an input 231 of the AND gate 206 via a line 230 . An input 232 of the AND gate 206 leads via a line 233 to an output 234 of the theft monitoring circuit 222. A multiple connection 236 is connected to an output 235 of the AND gate 206. A pulse output 237 of a clock generator 238 is connected to an input 240 of an OR gate 241 via a line 239. An output 242 of the OR gate 241 is connected via a connection 243 both to an input 244 of an OR gate 245 and to an input 246 of an OR gate 247 . An output 248 of the OR gate 247 is connected to an input 250 of the theft monitoring circuit 222 via a line 249. A blocking input 251 of the clock generator 238 is connected to an output 253 of an OR gate 254 via a line 252 . An input 255 of the OR gate 254 is connected to a status output 256 of the timing element 210 via a line 257 . Another input 258 of the OR gate 254 is connected to a status output 260 of the timing element 218 via a line 259 . The connection 236 combines the output 235 of the OR gate 206 with an input 261 of an AND gate 262 and an input 263 of an AND gate 264 and an input 265 of the OR gate 247. An output 266 of a flip-flop 267 is over a line 268 is connected to an input 269 of the AND gate 264 . An output 270 which is complementary to the output 266 of the flip-flop 267 is connected to an input 272 of the AND gate 262 via a line 271 . A reset input 273 of the flip-flop 267 is connected to an output 274 of the OR gate 245 via a line 275 . A set input 276 of the flip-flop 267 is connected to a pulse output 278 of the timing element 210 via a line 277 . An input 279 of the OR gate 245 is via a line 280 with a

Output 281 of a pulse shaper 282 connected. An input 283 of the OR gate 245 is connected to a pulse output 285 of the timing element 218 via a line 284 . The pulse output 285 is at the same time also connected to an input 286 of the OR gate 247 via the line 284 . An output 287 of the AND gate 264 is connected to a set input 289 of the timing element 210 via a line 288 . An output 290 of the AND gate 262 is connected via a multiple connecting line 291 to a set input 292 of the timer 218 and a set input 293 of the timer 294 and an input 295 of an OR gate 296 . The output 278 of the timer 210 is connected via a line 297 to both a reset input 298 of a counter 299 and a reset input 300 of a flip-flop 301 and an input 302 of an AND gate 303 . A status output 304 of the timer 294 is connected to a control input 306 of a shift register 307 via a line 305 . A clock input 308 of the shift register 307 is connected to an output 310 of the OR gate 296 via a line 309 . The output 310 of the OR gate 296 is connected to a clock input 312 of the counter 299 via a line 311. An overflow output 313 of the counter 299 is connected to a switchover input 315 of the flip-flop 301 via a line 314. A status output 316 of the flip-flop 301 is connected via a line 317 to a blocking input of an incremental generator 319. A pulse output 320 of the increment generator 319 is connected to an input 322 of the OR gate 296 via a line 321. Status outputs 323 of counter 299 are connected to inputs 325 of a decoding circuit 326 via connecting lines 324. Outputs 327 of decoding circuit 326 are connected via lines 328 to inputs 329 of a diode matrix 330 which internally has a level converter 331. Outputs 332 of level converter 331 are connected via lines 333 to inputs 334 of a comparator 335. Inputs 336 of the comparator are connected to status outputs 338 of the shift register 307 via lines 337. A result output 339 of the comparator 335 is connected to an input 341 of an AND gate 342 via a line 340. A status output 343 of the flip-flop 301 is via a line 344 both with a blocking input 345 of a pulse shaper 346 and with a trigger input

347 of the pulse shaper 282 and a reset input

348 of a flip-flop 349 connected. An output 350 of the decoding circuit 326 is connected to a trigger input 352 of the pulse shaper 346 via a line 351. An output 353 of the pulse generator 346 is connected to an input 355 of the AND gate 342 via a line 354. An output 356 of the AND gate 352 is connected to a set input 358 of the flip-flop 349 via a line 357. A status output 359 of the flip-flop 349 is connected to an input 361 of the AND gate 303 via a line 360. An output 362 of the AND gate 303 is connected via a line 363 both to the set input 364 of the actuation circuit 214 and to an input 365 of the OR gate 208 and an input 366 of the OR gate 241. A status output 367 of the actuation circuit 214 is connected to an input 369 of the OR gate 212 via a line 358. The pulse output 281 of the pulse shaper 282 is connected to an input 370 of the AND gate 303. Outputs 371 of the theft monitoring circuit 222 are connected to status switch 372 , which in turn are connected to ground. Outputs 273 of the theft monitoring circuit 222 are connected to signaling devices 374.
To illustrate the function of the circuit, the function is divided into the following sections:

1. Initialization function

2. Reception function

3. Basic clock function

4. Function of theft monitoring circuit

5. Synchronization function

6. Detection function

1. The initialization function starts when the receiver circuit is switched on (FIG. 2) via switch 201 with which the supply voltage is also applied to all components of the circuit. An initialization pulse occurs at output 203 of initialization circuit 202, which initiates the transition of the entire circuit to a basic state via connection 204. For this purpose, the initialization pulse runs over the line 204 to the input 205 of the AND gate 206 and blocks it so that no received pulses can pass through it. The initialization pulse runs through the input 207 of the OR gate 208 and blocks the timer 218 through the blocking input 217 , so that it falls back into its basic state. The same is effected for the timer 210 via the blocking input 209. Via the input 211 of the OR gate 212, the pulse arrives at the blocking input 221 of the theft monitoring circuit, so that it falls into an initial state. The same happens via the blocking input 213 with the actuation circuit 214. After the timers 210 and 218 have gone into the basic state, no signal can come to the blocking input 251 of the clock generator 238 via the OR gate 254 with its two inputs 255 and 258. This then begins to generate clock pulses that emerge at its pulse output 237 and also come via line 243 to the input 244 of the OR gate 245, from the output 274 of which via the reset input 273 of the flip-flop 267 of this flip-flop put back. With its complementary outputs 266 and 270 it acts via the inputs 269 and 272 of the AND gates 263 and 262 so that the AND gate 264 is a closed switch for pulses on the line 236 and the AND gate 262 is an open switch for the same impulses.

The basic state is thus established. The two AND gates 264 and 262 operate via the flip-flop 267 in such a way that a received pulse first reaches the timing element 210. Furthermore, the clock generator 238 is in operation in the basic state. After the reset process, which can last a few hundred msec, the reset pulse disappears so that the previously forcibly reset circuits are ready for operation again and can react to signals acting on them.

2. The signals sent by a suitable transmitter consist of a pulse train. They have Pulses of constant width, but different distances. After an initial impulse comes one Synchronization pause with one opposite the following Pulse intervals of excessive duration. To this Pulse pause of about 20 msec, the information pulses follow, with their intervals either 2 msec or 4 msec. 2 msec corresponds to one

O-Bit., 4 msec, an I-Bit.

The signals of the pulse code picked up by the receiving amplifier 224 are emitted as pulses at its output 223 . A received pulse triggers via the input 226 of the timer 227, which has an expiration time of slightly less than the intended pulse width (approx. ΙΟΟμβεο). The timing element 227 interacts with the AND gate 206 via its output 229 in such a way that it does not allow any signal pulses to pass through the AND gate 206 during its running time. These signal pulses, which are fed to the input 228 of the AND gate 206 via the line 225 , must therefore be longer than the running time of the timer 227. If they are not, then it is probably interference pulses. These are masked out by the action of the AND gate 206. Only sufficiently long pulses of the pulse code are allowed to pass to the output 235 of the AND gate 206. If pulses are received during the time of the initialization function, they will find an AND gate 206 blocked via input 205 and remain ineffective. The pulses also remain ineffective if, during the function of the theft monitoring circuit 222, a blocking signal occurs at its output 234, which is fed to the input 232 of the AND gate 206 via the line 233. This ensures that received pulses that come immediately after the arrival of a received pulse are suppressed. Since the theft monitoring circuit has a working time of about 600 μβεο. this means that all received pulses are masked out that are a shorter distance than a 600 μβεΰ. to have. Such pulses must also not occur, since the shortest pulse interval is two msec.

The reception function is used to monitor the time of the pulses so that only presumably meaningful pulses with sufficient width and sufficient pulse spacing from the rest of the Receiving circuit are supplied.

3. The clock generator 238 is the one clock generator, from which declares the main claim it emits a pulse train, which causes a pulse is generated in a predetermined by the clock generator 238 time interval in any case which abuts the anti-theft control circuit 222 via the input 250 This is a theft monitoring is triggered periodically. The pulses of the clock generator 238 also run on the input 244 of the AND gate 245, from where they act on the reset input 273 of the flip-flop 267 via its output 274 . The flip-flop 267 is thus held in an idle state.

The clock generator 238 via the inhibit input 251 can be switched off and maintained in a quiescent state while the remainder of the circuit operates as for the synchronization function or the detection function In both cases, either the timer 210 or the timer 218 are turned on, their status outputs 256 and 260 from the OR Gates 254 are combined and deliver a lock signal to the lock input 251 of the clock generator 238. The basic clock function is then switched off until the blocking signal at the blocking input 251 disappears again.It should be noted that a brief disappearance of the blocking signal does not lead to a pulse output at the pulse output 237 of the clock generator 238 , but rather that a certain lead time is necessary in the clock generator achieves that the locking signal may briefly disappear without the clock generator 238 starting again.

4. The function of the theft monitoring circuit is triggered by a pulse on the input 250 of the theft monitoring circuit 222. This pulse can come from four different sources which are combined by OLER gate 247. Received pulses arrive at input 265 of the OR gate. The theft monitoring circuit thus works every time pulses of the pulse code have been received. The pulses from the clock generator 238 arrive at the input 246 of the OR gate 247. The theft monitoring circuit 222 therefore works every time the clock generator 238 emits a pulse via its pulse output 237. The output pulse of the timer 210 arrives at the input 375 of the OR gate 247, so that the theft monitoring always works when a pulse occurs at the pulse output 278 of the timer 210 after the latter has expired. At the input 286 of the AND gate 247, a pulse occurs when the timer 218 expires from its pulse output 285 . The theft monitoring circuit 222 is then also activated.

The theft monitoring circuit 222 queries the status switches 372 connected via its inputs 371 in parallel or in series. The state of this switch status stored for the rest state of the status switch in the interior of the theft monitoring circuit 222 is carried out a comparison between the bit pattern corresponding to this idle state, and the actual position of the status switch 372nd If there is no match, the anti-theft device responds, ie the theft monitoring circuit 222 excites the signaling devices 274 via the outputs 273. Since the theft monitoring circuit can be triggered in a variety of ways via the OR gate 245 , there is a frequent comparison between status switches and the specified bit pattern so that there is no chance of circumventing the theft surveillance from that point on. The theft monitoring circuit 222 can be switched off immediately via the blocking input 221. This takes place via the OR gate 212 under two circumstances, namely once when the initialization function is running and the second when the actuation circuit 214 responds. The actuation circuit 214 responds every time there is a match between the received pulse code and a corresponding one Bit pattern has been determined in the receiving device. Then the object secured with the receiving device may be actuated by the apparently corrected one who was able to send the correct pulse code. But if a correct pulse code is sent, and z. B. if the status switch is changed by opening the doors, the theft monitoring circuit 222 responds and would give an alarm via these signaling devices 374. This is because the pulse code, which consists of many pulses, requests the monitoring function of the anti-theft device 222 several times during its reception. If the correct code is now received, these signaling devices 374 must switch off again immediately. This is done by the reset signal from actuation circuit 214 via line 368.

5. The synchronization function monitors the Start step of the pulse code. This starting step draws

net is distinguished by an excessively long pulse interval compared to the subsequent information pulses. the The synchronization function is triggered by a receive pulse that hits the timer 210 That is only possible if the flip-hop 267 has switched on the AND gate 264 in such a way that the from The switch represented by AND gate 264 is closed. When the timer 210 is switched on, a Blocking pulse from its status output 256 via the OR gate 254 to the clock generator 238, which then stops and in turn does not give any new trigger pulses to the theft monitoring circuit 222 The timing element 210 can be retriggered with respect to signals at its input 289. That means his The running time starts all over again as soon as another pulse occurs during this running time achieves that the timing element 210 does not emit a pulse acting as an end signal at its pulse output 278 can, as long as there is not actually an excessively long pulse interval. However, the timer 210 can expire, for which about 17 msec are provided, occurs a pulse at its output 278. With this pulse, the flip-flop 267 is over the line 277 the set input 276 is set. The AND gates 262, 264, which act as switches, switch over, so that now the following pulses of the pulse code no longer to the. Time element 210 but get on line 291. This end pulse from the pulse output 278 acts via the input 375 of the OR gate 247 as The impetus for a new anti-theft monitoring function. This is quite possible in terms of time since the next correct pulse of the pulse code may not appear until 3 msec later, so that for the 600 usec. Working time of theft monitoring circuit 222 leaves enough time The final pulse from the timer 210 also acts as a reset signal on the counter 255 and the flip-flop 301 and the lock signal on the AND gate 303. When the flip-flop 301 is reset, a signal from a status output 343 occur in such a way that the same is triggered via the trigger input 347 of the pulse shaper 282 and Via its output 281 an interrogating pulse is sent to the input 369 of the AND gate 303 A triggering of the actuation circuit 214 takes place via the AND gate 303, which of course not Therefore, the AND gate 303 remains blocked for the resetting operation of the flip-flon 301 when the timer 210 falls back into its idle state, the blocking signal, which consists of a? Status output 256 exits as a blocking signal for the clock generator 238 removed. He can again start to oscillate, but only deliver a pulse to its pulse output 237 after a while. Normally but in the meantime a new pulse of the pulse code, namely a first pulse of the series of information pulses and a new blocking of the Make clock generator 238 via timing element 218.

6. After the synchronization function, the detection function usually starts when the Synchronization pauses Connect pulses of the pulse code, which are referred to as information pulses. you The distance is much shorter than that of the first two pulses, which include the synchronization pauses. It are two different pulse lengths that are assigned to the bits of information.

After passing through the gate 262, each of the information pulses acts on the two timing elements 218 and 294 as well as after passing through the OR gate 296 to the shift register 307 and the counter 299. With the Pulse from the timer 210, which occurs at the end of the synchronization pause, are the counters 299 and the flip-flop 301 reset and the AND gate 303 locked for the duration of the reset pulse and for the effect of the pulse shaper 282, possibly when the flip-flop 301 is reset can be initiated via its trigger input 347. The starting edge of one of the impulses of the

ίο Impuiscodes switches the via clock input 308 Shift register 307 further. Which bit is then entered depends on the potential at control input 30 < of the shift register 307. This control input 3Of is from the output 304 of the timer 29 ^ controlled that is triggered with the trailing edge of a pulse from the pulse code. That means dat at the time of the clock edge at the clock input 308 the state of the output of the timer 294 is present de: dai is determined by the running time of the timer 294 from the trailing edge of the previous pulse is triggered. If the timer 294 is running, which has a “running time of about 3 msec at the time de! the next following pulse of the pulse code, so trit this pulse with a short distance on the previous, on. There will be an O-bit in the slide control ster registered. If, on the other hand, the running time is de; Time element 294 has expired, the next fol A 1-bit is entered in the next pulse. With every impulse! of the pulse code, the counter 299 is also passed on

switches the carry over after 41 impulses and thus via the switchover input 315 of the flip-flop! 301 this switches its status output 343 has an effect the flip-flop 349, the pulse shaper 282, the pulse shaper 346 and the increment generator 319. Dei Incremental generator 319 is turned on and gives a high frequency pulse train through its Pulse output 320 from.

The blocking input 345 of the pulse shaper 346 now receives such a potential that the pulse shaper 346 does not more is locked. The trigger input 347 de: pulse shaper 282 can with the status edge that bein Switching of the flip-flop 301 did not occur initially and remains silent. The reset input 348 de: After switching the flip-flop, flip-flops 349 receive:

301 no more reset signal, so that the flip-flop ii another state can be brought.

The high-frequency pulse train output by the incremental generator 319 has an effect the OR gate 296 as well as information pulses au Shift register 307 and counter 299. Here is however, it does not matter which signal is present at the control input 306 of the shift register 307. That leg in him Reception of the information bits registered binary pattern is with each pulse from the increment generator 319 shifted towards the end of the shift register 307 At the status outputs 338, from which the status « of the oldest bits in the shift register 307 exit, the comparator 335 is connected. To the Statusaus inputs 323 of the counter 299 is the decoding circuit 32 ( connected, which takes over the control of the Diodenmatri) 330, line by line. The bit states of each row of the diode matrix 330 are picked up by the level converters 331 and via dii Lines 333 to the inputs 334 of the comparator 33!

fed. The comparator 335 compares the bit u states of the shift register 307 with those in de • Diode matrix 330 are stored. Depending on the result of the comparison tirtt at the result output 339 de

! Comparators 335 a logic state which, if necessary, the AND gate 342 for a pulse from the Pulse shaper 346 can make permeable. Bit pattern in shift register 307 and bit pattern agree one row of the diode matrix 330, the s AND gate 342 remains blocked no match is found, a pulse from the pulse shaper 346 passes through the AND gate 342 to the set input 358 of the flip-flop 349. The Pulse shaper 346 always emits a pulse when both a blocking input 345 and his Trigger input 362 allow this. Accordingly, the first pulse already emerges when the counter 299 after The flip-flop 301 is switched to its zero position. The further pulses are emitted when! 5 so many pulses have been emitted by the time generator 319 that a next row of the diode matrix 330 is addressed by the counter 299 via the decoding circuit 326. A line-by-line reading of the Diode matrix 330 and a comparison with the respective shifted bit pattern of the shift register 307 instead.If no match is found in any of these steps, this will be Flip-flop 349 set

After another 241 pulses, the counter 299 outputs an overflow signal on the line 314, whereby the Flip-flop 301 switches back As a result, the incremental generator 319, the pulse shaper, is blocked is blocked By a suitable connection of the flip-flop 349 this is not immediately, but reset with a slight delay. Therefore its status output 359 remains for a short time. During this time, a pulse emerges from the pulse shaper 282 via its trigger input 347 was triggered by the switching back of the flip-flop 301. This pulse from the pulse shaper 282 serves as the Interrogation pulse for the status output of the flip-flop 349 via the AND gate 303. If the flip-flop 349 not switched during the working time of the incremental generator 319, a pulse through the AND gate 303 pass through and thus trigger the actuation circuit 214 via its set input 364. This is recognized by the actuation circuit 214 that a valid pulse code was present, so that a Authorized access to the protected property. This is then in front of the actuation circuit 214 set in motion. At the same time, a signal emerges from the status output 367 of the actuation circuit 214, the possibly ongoing theft monitoring by acting on the blocking input 221 of the so Theft monitoring circuit 222 breaks off. If the code comparison is successful, the line 363 also a pulse to the blocking input of the timer 218, so that this falls back without a Output pulse from its pulse output 285. Via the same line, a pulse from the OR gate 241 arrives, which via the OR gate 245 the flip-flop 267 resets so that a next following pulse of a pulse code the AND gate 264 in a such a condition occurs that this pulse can come to the timing element 210 as a synchronization signal. If there is no code match, the next synchronization interval must be used be switched. For this purpose, the pulse querying the flip-flop 349 via the AND gate 303 comes out the pulse shaper 282 also to the OR gate 245 and thus sets the flip-flop 267 so that a next pulse of a pulse train as synchronization Impulse on the Zeitgiied 210 can act. These Processes are repeated as long as signals are emitted by the receiving amplifier 224. If that is no longer the case, the two timing elements 210 and 218 expire and thus output via the OR gate 254 the blocking input 251 of the clock generator 338 free, so that this again pulses via the OR gate 247 on the input of the theft monitoring circuit 222 can give. If this is no longer blocked by the actuation circuit 214, the Status switch 374 re-examined for its prescribed rest position

The inventive circuit of the receiving device can also be used according to FIG a microprocessor, for which an embodiment is given in the following. A Microprocessor 381 is connected to an oscillating circuit 383 via line 382. An input 384 of the Microprocessor 381 is via a line 385 to an output 386 of the receiving circuit 387 tied together. Port inputs 388 of microprocessor 381 are connected to status switches 389. Port outputs 390 are connected to signal and actuation devices 391 via driver stages 392. Port outputs 393 and test inputs 394 are connected to a diode matrix 397 via lines 395 and 396. A power pack 398, which supplies the supply voltage for all components of the circuit via lines not shown is via a line 399 is connected to the reset input 400 of the microprocessor 381.

The functional description of this further exemplary embodiment is divided into functional groups The functional sequence according to the flowchart is similar to that of exemplary embodiment 1. There are differences as a result on that the operation of a microprocessor consists in the serial processing of program steps Es therefore, several processes cannot run at the same time. This creates differences in the Monitoring of irregularly arriving signals for a circuit arrangement with a microprocessor no separate component is provided. On the other hand, mutual interlocking of circuits due to the serial program sequence is used Use of a circuit arrangement with a microprocessor is unnecessary, since only one function is implemented at the time can be.

1. When the power pack 398 is switched on, the line 399 leads to the reset input 400 of the Microprocessor 381 for a short period a signal generated in the power supply unit 398, that the program of the microprocessor sets to a starting point. Not several Functions can be executed at the same time, a start for the functional sequence is thus defined. the The next program steps of the microprocessor consist of the signal and actuation devices 391 turn off. The circuit arrangement mentioned is thus at a starting point.

2. The signals picked up by the receiver 387 reach the port input 384 of the via line 385 Microprocessor 381. Depending on the type of microprocessor, signals 384 are either stored, and are thus available to the program for a longer period of time, or they have to be while they are waiting be adopted by the program. Pulse width monitoring is carried out by the program in that, with step a 1, port input 384 of the microprocessor 381 is queried for the presence of an input signal. Is the input signal

does not exist, the program continues to other parts of the program. If a signal is present, the input port 384 of the microprocessor 381 is queried again after a few program steps a 2, which are only used for the time delay reacts to its further processing or goes to other parts of the program that also include monitoring of received signals. Depending on the microprocessor used, the port state must be brought to a rest position after an interrogation of the input port 384 , in order then to be switched from a new or pending received signal, or if the input port 384 has no memory effect, such a process is not necessary. Since the signals received by the receiver as a pulse-code having a length of only about lOOjxsec, a common possible interrogation of the input port 384 is necessary. Otherwise, input signals are not recognized, since the query occurs either at a point in time when there is no signal, or at a point in time which simulates a signal length that is too short, since the entire signal from the interrogation loop a1, a2 , a3 is detected.

3. The basic clock function has the task of triggering a theft monitoring function of the program from time to time. It consists of a counting program a 4 which, each time a register assigned to this counting program has been decremented to zero, emits a signal in order to switch on the theft monitoring program a 5. The decrement takes place each time the loop a1, a2, a3, a4 is run through, that is to say following a query process of the receive function with a negative result. The register works cyclically so that after zero it comes to FFH. A special register setting after register content zero is therefore not required. The decrement cycle takes about 5 msec. During these times, 256 queries of the input port 384 are made. During the theft monitoring of 0.6 msec there is no query of the input port 384. Now incoming input signals are lost because the runtime of the decrementing cycle is much longer than that of the theft monitoring program and the duration of the former is set up so that there is no synchronization with the If the pulse code occurs at pulse intervals, reliable detection of the signals emitted by the transmitter is ensured. The counter register to be decremented represents the clock generator of which the main claim speaks in its effect on the theft monitoring

4. This function is required several times in the program of the microprocessor and is therefore structured as a subprogram (SR-DIEB), which means that this program only has to be contained once in the program memory of the microprocessor, and that for this part of the program from various points in the rest of the program can be accessed, and that after this part of the program has been processed, the accessing program is continued with its own next program timing steps. The subroutine of the theft monitoring function polls the port inputs 388, which are connected to the status switches 389 , in parallel. The binary pattern present at the port inputs 388 , consisting of the operating voltage of the circuit arrangement or no operating voltage, is compared with a binary pattern that is stored in the program memory of the microprocessor 381. If there is 5 agreement, the subroutine is immediately jumped to the respective calling program. If the binary patterns do not match, the signal and actuation devices 391 are addressed by the program via the port outputs 390 and the driver stages 392. This is done by outputting a bit pattern to the port outputs 390. Then there is a return to the respective calling program. Because of the additional security and monitoring functions that have not been described and that have to be carried out in the course of the subroutine, the same takes about 0.6 msec. During this time the program of the microprocessor only executes the said subroutine of theft monitoring and is not ready for other tasks.

After the successful detection of an input signal by means of the program parts a1, a2, a3, the program for the synchronization function 61 to 6 8 runs. During this function, it is examined whether a next input signal occurs at the input port 384 at such a time interval that this input signal is the end of the synchronization pause and thus means the beginning of the information part of the pulse code.

A program loop 6 1 waits for the input signal to end. Depending on the type of microprocessor, a distinction must be made here again as to whether the input signal is available to the program in a stationary manner by means of storage at the input port 384 or only for a short time during its own duration. In the first case, the state of the input port 384 must be reset within the loop b 1. As soon as the input signal is no longer available, the theft monitoring function is called as a subroutine (program part b2).

This is followed by a dead time of the microprocessor (63) in which nothing more is valid than counting down to zero a counting register set at the beginning of program part b 3. This part of the program takes about 1 msec. Together with program part b 2 , the microprocessor is therefore unable to examine received signals for 1.6 msec. Normally, no received signal should appear during this time. It could just be interference. These are hidden. This has the advantage that the

so theft monitoring function b 2 is not called again immediately after a corresponding program run.

After the dead time (program part b 3) has elapsed, 4 counting registers are set in program part b in such a way that, in conjunction with other program steps, they cause the program to work 17 msec for counting down to zero. This is followed by the program parts 65, b6, 67, which correspond to those of a I, a 2, a 3, but now do not work with a program part a 4, but with a program part 68 which, like the clock generator program a 4, has a duration specifies. Whenever no input signal has been recognized in the receive function 65, 66, 67, the named counting registers are decremented within the program part 68. If the content of the mentioned counting registers is not yet zero, a new program sequence 65, 66, 67 follows. If there is an impulse, so

the program jumps back to program part b 1. A new theft monitoring function bi is called and the synchronization function also starts anew. In this way, a synchronization interval pause must be found in the course of the reception of the pulse code. If the registers used as counters have been switched back to zero in the course of such a pause, a program part b 9 is executed which corresponds to that which was run through after the start to detect an input signal. The theft monitoring function a 5 is called at larger intervals, which are determined by the program part a 4. In between is always with parts of the program A i, A 2, A 3 to the end pulse of the synchronization pause waiting With such an arrangement it is ensured that the anti-theft surveillance and then used again when after the given with the program part b8 delay of 17 msec no input signal occurs, as is conceivable if the impulses of a transmitter are switched off prematurely. Otherwise, the end pulse of the interpulse period is always found, since the counting register in program part a 4 has not yet switched on the theft monitoring.

With the recognition of the end of the synchronization pause the program runs into the recognition function.

At the beginning of this, a register AiATVEC is set to zero in the program part cO. It serves as a Vector register for addressing the memory locations of the bits of the pulse code that are now to be recorded.

In a program part el, a loop waits for the received signal to end. This program part corresponds to program part b 1. This is followed by a program part c2 in which, as in program part b 1, the jump to the theft monitoring subroutine takes place. This means that after each recognized pulse of the pulse code, theft monitoring is carried out. Two registers are then set as counters in such a way that two time intervals are specified with them Absence of pulses in the loop for recognizing the pulse length gets stuck, but may jump back to the start Depending on the type of programming for time generation, one or two registers, each one byte length, are to be used for each of the specified times. These times are 3.5 msec for the length monitoring and 5 msec for the exit from the length monitoring loop.

With the programs cA, c5, c6 the length of the input signal is monitored, as is done with the program part a I, a 2, a 3 and b5, b6, b 7. If an input signal is recognized while the interval monitoring register is still active has not been decremented to below zero, the received signal is taken as an indicator that it includes a pulse interval that corresponds to a zero bit. Bit assigned If the input signal is missing due to a disturbance, the second register used for backup runs to zero, which was set to 5 msec, and thus lets the program jump to the start state.

The recognized zero or 1 bits are stored in a register set which is arranged in the form of a matrix with 5 lines of 8 bits each. This takes place in a program section clO. The matrix is designated with MX \ . The vector register MXVEQ, which is incremented with each entry, shows the position of the register to be filled in. This register also serves as a counter. In the program part, not only is this register incremented, but also a comparison is made to determine whether this register has been increased to 40. As long as this is not the case, the c-loop continues. Further input signals are checked for length and monitored, the bits are recorded and stored in the form of a matrix in MX 1.

If 40 entries of bits have been made, which corresponds to 41 input pulses, then a comparison between the registers storing the bits and the diode matrix 397 is carried out

The comparison is made by calling up the matrix position line by line, with output ports 393 addressing the diode matrix line by line and input ports 394 accepting the bit configuration corresponding to the diode distribution and storing it in a register MX 2 . The individual memory locations of the register arrangement MX 1 are compared with the individual rows of diodes. If the comparison is positive, a flag is set. At the end of the comparison process, the flag is checked. If the flag has not been set, the program jumps back to the start. If the flag has been set, a possibly pending theft signal is switched off via signal and actuation devices 391 and access to the protected object, in this case the motor vehicle, is permitted. This takes place via program part d2.

The program then continues to run for auxiliary and additional programs and then continues to take over monitoring functions.

In addition 6 sheets of drawings

Claims (8)

Patent claims: 1. Circuit arrangement for the electronic locking or unlocking of electronic safety devices, in particular as a door lock and Anti-theft protection in a motor vehicle, with a signal transmitter which has a binary pattern memory that can be read out with a signal transmitter on the output side and one of the security device assigned ι ο Neten signal receiver with downstream comparators and assigned binary pattern memory and an actuation circuit connected downstream of the comparator, the transmission by means of Pulse code takes place, characterized in that the signal transmitter is designed in such a way that it has a pulse sequence of pulses of equal width which represents the pulse code Pulse intervals of three different lengths emits that the signal receiver is to be monitored Status switch (372, 389) and is designed such that each received pulse of the Pulse codes stimulate the safety device for monitoring the status switch (372,389), and that a clock generator (238) is present, the pulses of which have the function of the pulses of the pulse code take over with regard to the safety device if the pulses of the pulse code are not pending for a specified time. 2. Circuit arrangement according to claim 1, characterized in that the signal transmitter is designed is that the longest of the three pulses of the pulse code occurs once in each pulse train, and that the signal transmitter is designed so that these pulses as synchronization signals for receiving the serve information contained in the pulse code. 3. Circuit arrangement according to claim 1, characterized in that the signal transmitter is designed is that the pulses of the pulse code for 1 information of the binary pattern memory twice as Sang are the same as for 0 information. 4. Circuit arrangement according to claim 1, characterized in that the signal transmitter is designed is that the pulses of the pulse code for O information of the binary pattern memory are twice as high long are the same as for 1 information. 5. Circuit arrangement according to claim 1, characterized in that the signal receiver is designed so that the clock generator emits a pulse frequency with such pulse intervals that at least every other pulse of the pulse code falls within the intervals. 6. Circuit arrangement according to claim I, characterized in that the signal receiver has a Time circuit (27) which blocks pulses of shorter duration than those emitted by the signal transmitter. 7. Circuit arrangement according to claim 1, characterized in that the signal receiver is designed so that the safety device Monitoring of the status signals in those time periods in which there is no impulse of the Pulse code is received. 8. Circuit arrangement according to claim 1, characterized in that the transmitter is designed so that the pulses of the pulse code are emitted at a carrier frequency.