DE2855947A1 - PLA ADDING CIRCUIT - Google Patents

Description

Applicant: International Business Machines

Corporation, Armonk N.Y., 10504

ι te / zi

! PLA editing circuit

The invention relates to an adding circuit with a programmable logic arrangement (PLA) according to the preamble
of claim 1 ^.:

The generation logic operations in a matrix ^identical: genetic switching elements, each on clear cutting | point of an input and an output line in one
Arranged in a network of intersecting lines is known. To carry out logical functions, many i

such arrangements of matrices can be used. ■ One of them is called Programmable Logical; Arrangement (PLA) known; it is, for example, in the | U.S. Patent 3,987,287. In this PLA he; ^; input decoding circuits produce so-called min-terms and! enter it into a first matrix (as a product term generator or ¹

J ι

ι referred to as AND matrix), the product terms as functions _: j generated the input signals of the decoding circuits. These j ¹ product terms are fed to a second matrix (as
OR matrix or called the sum of product terms),
which is used to increase the number of functions under; Using these product terms can be achieved without ^{geometrically enlarging the:} AND matrix. The output of the OR matrix is given to latch circuits so that with
this PLA is both sequential and combinatorial
Logic functions can be carried out.

The logical: function performed in these latches is normally the AND function. In certain PLA ¹ s' (see German patent application ..., int. File number KI977OO2J

Po 976 023 909827/0919

the interlocking circuits also implement an exclusive OR function (non-equivalence). In the publication IBM Technical Disclosure Bulletin, May 1975, page 3653 describes an adder circuit that can be used with PLAs of this type is constructed. Such an adder circuit, however, offers compared to PLAs with locking elements with an AND function no benefits.

The present invention therefore has the object of providing an adder circuit using programmable logic Specify arrangements which are more simply constructed than those previously known and in particular with a smaller one Number of product terms.

This object is achieved by the invention characterized in the main claim; Embodiments of the invention are in the Characterized subclaims.

For the addition of two binary numbers, the PLA has a two-bit decoding device, each of which pairs the pairs of bits with the same place value AB of the two binary numbers (with the η bits A _Q , A ₁ , ... A _n-1 and B _Q , B ₁ , ... B _n-1 ) and receives a carry bit C. The decoders generate: an output signal (min-term) on different lines for each of the four possible combinations AB, AB, AB and

On the On _L J- J- j

, AB of the true and inverted bit values in each pair. '' The min-terms of the decoding devices are fed to a matrix (product term generator or AND matrix) which generates the following product terms:

^f p ^{= f} 0 ^(A 0 'V ^USW

The product terms serve as input signals for a second matrix (generator for sums of the product terms or OR matrix). The logical elements of the PLA are a number of

po 976 023 909827/0919

-s- 2Θ55947

Interlock circuits connected downstream. These circuits ¹ each perform an exclusive OR operation in order to generate a Sununenbit S. The sum S_., S ₁ , ... S.,

'1 yJ I II "" 1

'and an output carry bit C. thus arise at the output of the PLA by exclusive-OR linking of two functions that are given by the OR matrix to the input lines: the interlocking circuits. This adding-I circuit, built from PLAs _: with exclusive-OR logic circuits, is more effective than the known circuits whose

J use PLAs AND gates at the output; in particular is the

i Number of necessary product terms reduced.

! An embodiment of the invention will now be based on j drawings explained in more detail. Show it:

j Fig. 1 is a schematic representation of an adding circuit,

FIG. 2 shows an illustration with an adder circuit according to FIG the invention,

Fig. 3 is a table with the logical functions that are included in

the AND matrix of a PLA can be carried out, ; which is acted upon by two-bit decoding circuits,

4 shows an illustration of the sequence of product terms in Adding circuits according to the invention.

Fig. 1 shows two numbers AqA consisting of η bits. ... A- and BB ₁ ... B _- | / ^which are to be added together with an input carry: bit C. by a circuit to form a sum consisting of η bits S _Q S ^ ... S _{n -1} and an output carry bit C. to create. The circuit 8 for performing the addition consists of programmable logic arrangements (PLAs), which are shown schematically in FIG.

po 976 023 909827/0919

In FIG. 2, mutually corresponding bits of the two 8-bit numbers A, Α.,, ... A- and B ₀ , B,., ... B _{7 are} supplied to two-bit decoding circuits 10 in pairs. The decoding circuits 10
each generate a pulse on one of four different ones
Output lines for each of the four possible combinations
of the true and the inverted value of the input bits A. and
B. Each output line of each of the decoding circuits 10 is
with a different input line 11 of an AND matrix
12 connected. The boxes 14 in Fig. 2 each represent the
Intersection of each set of four input lines 11 of a: decoding circuit 10 with an output line 16. Inner-. half of each box 14 contains four possible connections of \ NOR members. These NOR elements connect one or; all input lines 11 of the set with the output line ^! 16, which runs through box 14. The selective connection
of the input lines with the output line allows
in each box 16 different logical functions of the
both input signals A. and B. of the decoding circuits; to be carried out and to the assigned output line
give; this variety is possible through the combination of the decoding devices and the NOR elements within the boxes 14 i.

The different logical functions are in the table
shown in FIG. It represents each of the four columns
represents one of the input lines in set 11 of the AND matrix.
At the top of the columns is the combination of true and / or; the inverted values of the inputs A. and B. indicated, with which the decoder is applied; the decoder then generates a pulse on the input line,
whose value is indicated by the column. The entries of the
16 rows of the table represent all possible functions,
which can be carried out with the two inputs A. and B. of the decoding device. The one at the intersection of a; Row and column each represent a '

PO 976 023 909 8 27/0919

- ¹ ° - 2855S47

The intersection of the input line represented by the column and the output line that runs through the box. The number 1 in each square indicates that a connection must be made between the input line and the output line at this intersection in order to create the puncture shown in the series; the number 0 indicates that no connection has to be established to generate the function. Of the 16 possible functions, only 6 are of interest here when performing the addition. These are in Fig. 3 with G ₁ ; δ \; P ₁ ; Ρ _± ; H _± and H _± . Performing logical operations on matrices and two-bit decoders in this manner is known and can be found, for example, in US Pat. No. 3,987,287.

In FIG. 2, the row of the ÜND matrix represents a product term. For example, row 3 in FIG. 2 contains the product term HgG ₇ , where Hg is a function of the inputs (Ag, Bg) and G _{7 is} a function of (A ₇ , B ₇ ) is. A box 14 without an entry represents a so-called “don't care” condition in the generation of the product term, ie the content of this box is irrelevant. The output line 16 for each line of the AND matrix is connected to an input line of an OR matrix 18. Each box 20 of the OR matrix represents the intersection of one of the input lines of the OR matrix with one of the output lines 21 of the OR matrix. A 1 in one of these boxes represents a connection in the form of a NOR element between the input line and the output line This intersection represents. An empty box 20 means that there is no connection between input and output lines at this point. Thus, each column of boxes 20 in the OR matrix 10 represents the OR function of the sum of the product terms in the AND matrix, which are connected to the output line 21 via the OR gates according to the distribution of ones in the box-

po 976 023 909827/0919

the column is connected. For example, the am ^; .Farthest left column of the OR matrix represents the OR function of the product terms present in rows 25 and 26.:

j i

! Pairs of adjacent OR columns are denoted by |

the interlock circuits 22 (so-called state controlled i

ι, D flip-flops, latches) as an exclusive OR link!

! saves. The outputs of the exclusive OR circuits 22; i share the output signals of the PLAs and the output signals> the adder circuit. The output bit C. is the exclusive i IODER combination of the two leftmost OR columns.

jWith this type of PLA, the adder circuit is constructed in such a way that each output signal is exclusive-ORed
of two functions, each function being the OR 'function of product terms. A product term is a
^: AND operation of functions of the individual bit positions
; the input of the adder circuit and the input carry bits.

Product term =

f _o (AO, B0) .f _{i (} A1, B1) ..... V ₁ (A _n-1 , B ^) -f ^ C ^) (1)

The decoding circuits 10 and the NOR gates in
Functions generated by one of the boxes 14 of the AND matrix at bits A., B. of the n-bit input of the adder circuit that correspond to one another look as follows:
G ₁ = A ₁ -B ₁ G. -A ₁ -IB ₁

P ₁ = A ₁ + B ₁ P ₁ = A ₁ -B ₁ __ _ (2)

H ₁ = A ₁ VB ₁ H _± = A _± VB ₁ = A ₁ VB ₁ = A ₁ VB _±

po 976 023 909827/0919

Each carry bit can be and using the known methods for forecasting the carries on additions Complement can be expressed as follows:

^c i ^{= p} i

- •••• ^{> H} n-2 ' ^G n-1

n-2 n-1

C.

A sum bit can be expressed as a function of the previous one Carry over; so it can also be developed as a function of earlier transmissions.

S. = H. V C. ... = H. * C. ,. + H. ' ι __i 1 + 1 ι 1 + 1 ι

■ V / ^G i ₊ i \

'+ H. Ci

/ i + 1 '^ i + 2

• ^H i + jr ^G i + J

^{II H} i + 2 "

+ H.i

+11 / + H +1 " i + 1 * ^P i + 2 t I. i + j i + H • +1 i ^H i + 2 H . c ρ i + j i ^H i + 2

l V '

PO 976 023

909827/091 9

With the relationship

X (Y V Z) = (X + Y) V (X + Z)

(6)

can equation (5) as an exclusive OR of two Functions are represented, each of which is the OR function of product terms:

^{+ H} i + l ' ^P i + 2

* ^H i + j + l ' ^G i +;

^{+ H} i + _j ^{) v} (»i + i ⁺

i + j

(7)

909827/0919

PO 976 023

■ ^S i ⁼

H ' ⁷ P
¹¹ ■ 'i + 1

^G i + 2 ^P i ₊ 2.

^G i + 2

^H i

9098

PO 976 023

7/091

i ¹¹ I ₊ I i ^'11 X ₊ I

Γ0 976 023

909827/091

+ HZH _{1 + 1} '... Ή · H ^ 2655947

-H ₁ -H _{1 + 1} - ... 'H _{1 +} J _-1 -P ₁₊ J

II. "II.

1 1-

Etc.

'i + 2 ^{= lG} i + 2 ^{+ P} i + 2

A similar expression can be derived for S. and then delivers:

-NS

l ^U i ^P i + 1

^P i + 2

"i + 2 *

⁺ »I" i + 1 ' ^H i + ₂ ' ⁺ »i ^G i + 1 '"·' »- * ^G i + 2

i »i + 1» i + 2 * * * · '

V ¹ I ₊ I ⁺ ··· ⁺ »i + j

PO 976 023

909827/0919

Note that the product terms in the lower half of the upper parenthesized expression in Equation (9), namely H ^ G _{1 + 1} , and so on, agree with some of the product terms in Equation 3. This means that some identical product terms occur in the sum and in the carry over of the same bit position. The same applies to equations (8) and (4). ;

The equations (8) and (9) show that an intermediate carry j can be used for a sequence of several consecutive (that is, in each case; more significant) sum bits. In addition, j only one polarity is necessary for the intermediate carry. At- ; ^; for example, with the intermediate carry C. from equation! I (3), which has positive polarity, the following three '! Sum bits are generated with negative polarity according to equation i (8):

^{+ I} W ^H i-2 * ^P i-1 + H. _ «P. -

It should be noted here that the first sum S _1- , * only requires one additional product term H _1-1 . The second sum requires two additional product terms, namely H _1-2 "P _1-1 and H. * P ._. |. Since negative polarity S _{1-1 was} chosen, the terms H .. come in 'S * * and S _1-2 . The third sum requires five more product terms, four in the left parenthesis and H. ~ in the right parenthesis. A fourth total would require seven additional product terms, the next nine, then eleven, and so on Total number of additional product terms that are used in a sequence of K sum bits

po 976 023 909827/0919

2655947

is necessary is:

1 + 2 + 5 + 7 + ... + (2K-1) = K ² -1 for K> 1 (13)

The additional product terms for the carry over from the high-digit sum bit must be added to this number the consequence are necessary; Here, too, it should be noted that this carryover C., some of the product terms of the superscript Sum of the sequence used. The number of additional product terms required for C., is:

(L + K + 1) - (K-1) = L + 2 (14),

where L = the number of low-order bit positions up to to the current sequence (but does not include this itself).

(L + K + 1) = the total number of

l-κ

borrowed product terms (K-1) = the number of product terms that c. .,

1 — Jv

together with S. _, Has.

The total number of additional product terms T required for a sequence of sums and their output carry, results from the sum of equations (13) and (14):

T = (K ² -1) + (L + 2) = K ² + (L + 1) for K> 1 (15)

Normalized to the size of the sequence K one obtains:

T / K = K + ^ r- for K> 1 (16)

The point at which it is better to move on to the next longer sequence occurs when T / K is for both K and for (K + 1) is equal. Therefore

T / K = T / K + 1 = K + ^ ~ = (K + 1)

so that

L + 1 _ ₁ L + 2
K 'K + 1
and

L = K ² + K - 1 for K> 1 (17)

PO 976 023 909827/09 1 9

i - 19 - '

The transition points at which it is worth going to the next
transition to larger sequence are represented by equation (17); they are listed in the following table:

K - »(K + 1) 2—» 3 3 - ^> 4 4—> 5 5—> 6 6 »7

L 5 11 19 29 41 "■ *

; I.

^ In other words, after five low-digit bit positions i the next sequence is equally efficient on 2 or 3.

■ After eleven bit positions, the next size in the sequence is the same efficient on 3 or 4 etc.

^: The range of the bit positions taken by neighboring sequences

; the same size is covered is: j

. L [at the optimal transition from 6K + 1) to (K + 2) j i

: - L I at the optimal transition j i

Lyon K to (K + 1) J j

. = (K + 1) ² + (K + 1) - 1 - (K ² + K - 1) (18) j

2 (K + 1) for K> 1 \

In other words, if after L bit positions it is determined that the next size of the sequence can be expanded from K to K + 1, two such sequences can be consecutive
assigned before a sequence of K + 2 is warranted
is. The only exception is the first sentence of the three
low-digit sequences of 2. Optimal assignment of the sequence
is therefore: 3 sequences of 2 followed by pairs of sequences
of the nearest whole numbers (2 sequences of 3, 2 sequences of 4 ', etc.).

It should be noted that the transfer C., with negative

ι - κ.

Polarity common product terms with the high-order [ sum bits of the sequence £ 5. . having. Step in a similar way

ι - κ

^{P0 976 O23} 909827/0919

i - ²⁰ -

. common product terms in carryover C., with positive j polarity and the sequence S., the high-digit sum bits with positive polarity. Opposite polarities have no common product terms. Therefore bej adjacent sequences of opposite polarity; the sum bits '' negative polarity are functions of a carry over of positive ; tive polarity and vice versa.

A further reduction in the product terms is achieved with the high-digit sequence. Here is the carry out the sequence C., the output carry of the adder circuit, which can be expressed as an exclusive OR link of two functions that use the highest-digit intermediate carry C that is already available.

PO 976 023 909827/0919

'out

G,

^{+ H} 0 ^G l

^{+ H} 0 ^G l

^HI 0 ^G l

- 21 -

ι η ^c τι · ^β π * r

Hl ₀ H ₁ ... H _q _ ₂ Gq _-1

^Hi 0 ^G l

(lvj _q )

—Κ

^{v (H}

4-H ₀ H,

. * II

q-2 ^U q-1

909827/0919

i> 0 976 023

^G o ^{+ H} o * ^G i

(20)

since (G ₀ -.- H ₀ ) - H ₀ = G ₀ + P ₀

(H ₀ -G ₁ + Ii ₁ ) -H ₁ = G _{1 +} P ₁

Etc.
For a high-digit sequence of positive polarity one obtains:

(21

PO 976 023

i So here only two additional product terms for C. . _ _ _ out

, (namely G _Q and Hq) or for C ₀ - (namely P _Q and H _Q ). The other product terms are common with S _Q and | S_. So the total number of additional product terms required for: the high-order sequence with K is:

! ^T high ^{= r2} " ¹ + ² K ^{2 + 1 for K} > ¹ ( ²² )

j The above equations can now be used to construct an 8-bit adder circuit. The final The equations are shown in FIG.

! It starts with the creation of the product term C., where

I the sequence of the sum bits of positive polarity and their output carry is chosen arbitrarily. If the first (low-digit) sequence is only one bit long, it contains the functions S ₇ and C ₇ , which require three new product terms, namely H ₇ , G ₇ and H ₇ * C _in · For a sequence with 2 ( K = 2) and; L = 0 equation (16) yields a value of 2.59 product terms per bit. This is less than the three new product terms for a single bit sequence. For a sequence with 3 (K = 3, L = O) the value is 3.3 new product terms per bit. The optimal sequence is therefore 2 (S-, S _ß and Cg).

The next sequence is completed r "n. Since L has increased, the optimal size of the sequence is at least equal to the optimum selected for the previous sequence and at most! 1 larger. For K = 2 and L = 2, equation (16) 3.5, while four new product terms per bit are found for K = 3 and L = 2. Therefore, the second sequence also has size 2 (S ₅ , S ₄ and C ₄ ).

The third episode will now be positive. For K = 2, L = 4, equation (16) gives 4.5, while for K = 3, L = 4 the result is 4.7. The third sequence is again size 2 (S ₃ , S ₂ and C ₃ ).

po 976 023 909827/0919

The last episode can only be size 2 to make ÜL,
! £ 3 and C. and comprises five according to equation (22)

; new product terms.

i The general rule is that the procedure is completed when
j the last sequence is equal to or one greater than that
penultimate episode, even if this results in more than two equal high-order episodes. If the last episode is at least two times smaller than the penultimate episode, the
The last sequence is understood as a remainder that can be incorporated into one or more of the preceding sequences. An example of this: You go back to the lower-digit bit positions (shorter sequences) and expand the series of sequences that are equal to the penultimate sequence by one. This increases one of the sequences by one unit, so that one bit position of the remainder is used up. The number of the next smaller sequence sizes is then increased by one until the entire remainder is used up.

A special case arises when the last episode is about exactly I is one bit position shorter than the adjacent sequence. the

i last sequence is then increased by one and the first (low-; digit) sequence to a special sequence with one in the low-

digit bit reduced, with three product terms
^S low ^cC in ^and ^ low are used:

^S low ⁼ (^ low '^ iny pi low ^rC inJ ⁽²³⁾ Low = P _low ^ _low ' C _1n j (24)

Conversely, the complements can also be used:

^ low ⁼ £ ^H low " ^c iny ^ low" ^ in) ^{(25) C} low ^{= G} low ^V > ^H low « ^C in? ⁽²⁶⁾

^PO976023 909827/0919

1 5 4th 4th 3 3 2 2 2 2 4th 4th 4th 3 3 2 2 2 3 3 4th 4th 3 3 2 2 2 4th 3 4th 3 3 2 2 2 5 ι 4th 4th 3 3 2 2 2 6th 2 4th 3 3 2 2 2 7th ί 4th 4th 3 3 2 2 2 8th 1 4th 3 3 2 2 2

- 25 -!

The following examples illustrate this: Sequence sizes in the first run (the number indicates the size of the

Examples follow on) Optimal consequences

no change - ■ procedure completed

4 4 4 3 3 2 2 1 |

4 4 3 3 2 2 1 y 4 4 4 3 3 2 2!

j 4 4 3 3 2 2 \

4 4 4 3 2 2 2 | 4 4 3 2 2 2

, + indicates a sequence that has been increased by one ^! - indicates a sequence that has been reduced by one / indicates a sequence as a remainder to be absorbed

iThis procedure results in an optimal solution, although for the same number of bit positions also other optimal solutions are possible.

Fig. 4 shows the arrangement of the sequences and the product terms, necessary for adding circuits with 8, 16 and 32 bits are.

Modifications to the above procedure are without further possible. For example, if the carry is represented using terms of a remote carry, where the method of the carry forecast is used, for example the H's in equation (3) be replaced by P's. Similarly, in developing the carry complement C in equation (4), the H's to be replaced by G's. The same rules also apply

PO 976 023 909827/0919

285594?

I - 26 -

for the development of the carry for the sum bits S in equations (8) and (9). This is because ^G i ^{+ H} i ' ^G i ₊ 1 = ^G i ^{+ P} i ^G i ₊ 1 and

With such replacements, care must be taken that i
ιproduct terms appear together; for this reason not all possible H's are substituted in the equations. In equations (3) and (4), the high-place H's have not been replaced so that they also appear in the corresponding sum bit. Of course, in the equations 8 and ¹ 9 highly-digit sum bits are not replaced, as no! Equivalence exists.

po 976 023 90 98 27/091

Claims (1)

285594 PATENTA N PROPOSALS Adding circuit with a programmable logic arrangement (PLA), its AND matrix decoder with two inputs and four outputs are connected upstream and their OR matrix has exclusive-OR locking circuits two inputs are connected downstream, characterized in that mutually corresponding bits (A., B.) of the Addends (A) and the Augenden (B) are each fed to a decoding circuit (10) and that for generation of the sum bits S. the AND and the OR matrix are assigned according to the following logical relation: ^s i V ^G i + l
⁺ V ^H i + l " ^G i VW V ¹ i + 2 i + j " ^F. YV ¹ W ¹ W K ₊₁ ^{+ C} i ₊ j + l PO 976 023 909827/0919 ORIGINAL INSPECTED ^S i = i + 2 ** ** ^H i + r ^H 1 + 2 ** + H ₁ whereby ^G i ^{= P} i ^=
H i = A ₁ + VB ₁ G. = A * + E. P ₁ = A ₁ -B ₁ H i = A ₁ VB ₁ H = ^{H or P H} PO 976 023 909827/0919 - 3 - ^C in 2a559A7 I. ^{+ Η} ο " ^ρ ι / J
i, marked,
according to the following ■ I ₊ H · Η ** ... · Η ** "F J 2. adding circuit according to claim 1, characterized
that any intermediate carry (C.)
logical relationship is determined: •
+ HiV _{1 + 1} -... 'C ₂ -G _n-1
* * *
+ H ₁ -H _{1 + 1} -... * H _n _ ₂ H _n-1 : ^ü in - or C- - P ₁ •
** ** -
• * Tl * P ^{+ H} i ^H i + 1 ··· n-2 ^H n-] 3. adding circuit according to claim 2, characterized in that
that the output carry bit (C.) according to the following
logical relation is determined:
-v ^C out PO 976 023 909827/0919 -A- or ^C out ⁼ / ^G 0 where q = j + 1 4. adding circuit according to claim 2, characterized in that an intermediate carry (C.) for generating successive sum bits (S. _Λ , S. _o ) according to the following X "" I X ~ Δ Relationship is used: ^r ii = { ^H i-iH ^c i] ^S i i-2 ^H i i-2 ^P i- f ^H il or ^S i-2 C, ι + H, PO 976 023 909827/0919 2S55947 Adding circuit according to Claim 2, characterized in that the length of any intermediate sequence of product _{terms P. Λ} , P. ~, ... P., according to the formula: i = k ² + (k-1) is determined, where i = the number of low-order bits that precede this sequence and k = the number of bits in this sequence. Adding circuit according to Claim 1, characterized in that the lower-digit carry and sum bits correspond accordingly can be determined using the following formulas: Q =; ^ TT * O down f down in down ^ down * ^H - ^J - ^J - ^J or their complements: C> down in C down ^ in y ^S down ⁼ ^ down low low ^V ζ ^H down ^C in 4- 7 ni down in C po 976 023 8098 27/0919