DE2850101A1 - Circuit to control analogue=digital converter - uses input of two groups of analogue signals from selector and from feedback loop via memory and multiplexer - Google Patents

Abstract

A summation unit (30) is connected between an analogue selection circuit (10) and the A/D converter (36) and also receives input from a D/A converter (52). The output from the A/D converter (36) is in binary form and is transferred to a memory unit (39) and thereafter to a multiplexer (50). The circuit has the property of incorporating a hysteresis effect in a feedback loop and thereby enabling some control to be exercised over the analogue signal. The first group of analogue signals enters through four terminals (2, 4, 6, 8) on the input side of the selector, and the second group from the D/A converter to produce the third group from the summator. Digital control signals enter via four input lines (20-26) and are supplied to the selector (10), memory (39) and multiplexer (50) as well as a digital display (64).

Description

Circuit arrangement for controlling an analog

Digital converter The invention relates to the tax. an analog-to-digital converter, and more particularly relates to a circuit arrangement with which the operation of illes analog converter is to be stabilized If a digital display device is connected to an analog-to-digital converter is and a representation in a BCD format is desired, the quick UmschaltElg of the digital output signal azu lead that the digital display becomes illegible. Whether @@@ l a lock or a storage register between the analog-digital converter and the digital display device can be placed, could be a change of the lock or the storage register each time then leads to a change in the Output signal when the latch or the storage register is through Control signal or a clock signal can be controlled. The time between control pulses or clock pulses can be increased to stabilize the display, however, it then takes a while to transmit an analog input signal into a digital output signal relatively long.

The invention is based on the A u f g a e, a control of a Analog-to-digital converter of the type explained in more detail to create which Dei high conversion speed even with relatively strong noise in the analog Input signal ensures a stable digital output signal.

The patent application in particular serves to solve this problem laid down characteristics.

According to a particularly preferred embodiment of the subject matter of the invention it is provided that an analog circuit arrangement between the input terminals and the Analog-digital converter is arranged, which on the rste analog signal responds to the second analog signal in such a way that this has an offset with respect to the first analog signal, and that one Offset control circuit is provided which is connected to the analog-to-digital converter and is responsive to the digital system such that the offset between the first analog signal and the second analog signal is controllable.

According to the invention, the essential technical progress can be achieved, that by equipping the analog-digital converter with a hysteresis a Stabilization of the output signal is achieved in such a way that a special stable digital display is made possible.

furthermore, the circuit arrangement according to the invention also proves itself when applied to a circuit system in which a plurality from analog input signals in multiplex process into corresponding digital output signals being transformed.

Overall, the readability of a digital display device is gem the invention significantly facilitated by appropriate stabilization.

The invention therefore makes use of the knowledge that with the help of Applying an offset signal in a feedback analog-to-digital conversion Can be significantly improved and in particular the display of a downstream Display device can be stabilized considerably.

The invention is explained below, for example, with reference to the drawing described; These show: FIG. 1 an overall block diagram of one according to the invention Analog-to-digital converter, which is used for a digital display device to operate in the multiplex method, as in a preferred embodiment of the invention, FIG. 2 is a block diagram of that shown in FIG Analog-to-digital converter showing the circuit arrangement in more detail FIG. 3 shows a detailed block diagram of that part of FIG the circuit shown in FIG. 1, which responds to a digital input signal, in order to add an offset signal to an analog input signal, FIG. 4 shows a graphic Representation showing the relationship between the analog input signal and the composite analog signal to which the offset signal was added, and Fig. 5 is a graphic representation which, on an enlarged scale, a specific Area of the representation illustrated in FIG. 4 reproduces.

According to the illustration in FIG. 1, an analog-to-digital converter a feedback path to create a hysteresis to a selected analog input signal to add up. A plurality of analog signals are sent to a corresponding one Number of input terminals 2, 4, 6 and 8 added, which are connected to an analog selection circuit 10 are connected.

In addition, to the analog selection circuit 10, there are a plurality of Control lines 12, 14, 16 and 18 connected, which with a corresponding Number of control input terminals 20, 22, 24 and 26 are connected respectively. One such analog selection circuit 10 is known in principle, and can be from a MOSFEI multiplexers exist, for example under the type designation MC14016B from the warm Motorola is delivered. The output of the analog selection circuit 10 is connected via a line 28 to a summing circuit 30, which is based on 3 is explained in detail below.

The summing circuit 30 combines the selected analog input signal, which is present on line 28, t an analog offset signal on the Line 32 and supplies an analog output signal into the line at its output 34 to the analog-to-digital converter 36, which is based on the lig. 2 in more detail below is described. The input terminal 38, which is connected to the analog-digital converter 36 is connected, takes a first control signal or clock signal to a digital Determine the result as explained below.

The analog-to-digital converter 36 is connected to the memory circuit 9: oer BCD output lines 40, 42, 44 and 46 connected.

The memory circuit 39 has a plurality of 4-bit memory registers which corresponds to the number of analog signals received from the analog selection circuit 10 to be taken on. The control lines 12, 14, 16 and 18 are connected to the memory circuit 39 connected to one of the memory locations or one of the memory locations in the 4wBit memory to activate, the input terminal 48 receives a second control signal or clock signal, to enable the BCD signal to appear on output lines 40, 42, 44, 46 is saved from the activated memory location of the 4-bit memory.

The memory circuit 39 is connected to a digital multiplexer 50, which picks up a plurality of 4-bit BCD signals which are stored in the memory circuit 39 are stored. The digital hultiplexer 50 is provided with control lines 12, 14, 16 and 18, which select one of the plurality of 4-bit BCD signals, to connect to the output of multiplexer 50. The digital one Multiplexer 50 is also connected to a digital to analog converter 52 via BCD output lines 54, 56, 58 and 60 connected. The digital-to-analog converter 50 is shown on the basis of FIG. 3 explained in more detail below.

The digital-to-analog converter 52 is connected to the summing circuit via the line 32 30 connected. The digital multiplexer 50 is also provided with a decoder circuit 62 connected via lines 54, 56, 58 and 60. The digital decoding circuit 62 is connected to a digital display circuit 64, which is also connected to the control lines 12, 14, 16 and 18 is connected. The control lines 12, 14, 16 and 18 select the Digit position that corresponds to the BCD data signal transmitted by the multiplexer 50 was selected, as is customary with multiplex display devices.

The details of the analog-to-digital converter 36 shown in FIG. 1 are shown explained below with reference to FIG. The analog output signal, which from the line 34 is received, a plurality of comparator circuits 66 fed. Each of these comparator circuits 66 is connected to a reference node, which is at a certain reference voltage. The reference voltages are through a conductor network is supplied, which is formed by a number of resistors 68 that is in series between the ground potential and a positive supply voltage potential are arranged, which is applied to the terminal 70. Every rator circuit provides a binary display voltage, which indicates whether the voltage of the analog Output signal on line 34 is more positive or more negative than that corresponding reference voltage. Since comparator circuits are known in principle, no further explanations appear in this context of the comparator circuits 66 is connected to the data input of the corresponding number of latch circuits 72, each of which has the output status of its associated comparator circuit stores. Any of these latches is connected to a common control signal input terminal 38, so that the data input each latch circuit 72 can be activated or deactivated at the same time can. The output of each latch circuit is to a digital coding circuit 74- which encodes the digital result, which in the majority of the Latches are stored in a BCD format, this Result appears on lines 40, 42, 44 and 46.

The digital coding circuit 74 functions as a priority coding circuit known in principle, and a circuit of this type is known under the type designation MC14532B manufactured and sold by Motorola.

The following are the details of the digital-to-analog converter circuit 52 and the summing circuit 30 based on the 'ig. 3 described. The digital-to-analog converter circuit 52 has four switching networks 78, 80, 82 and 84, each with the corresponding BCD input lines 60, 58, 56 and 54, respectively, are connected.

The switching network 78 is connected to a first current source 86. The switching network 80 is connected to a second power source 88, the one Leads current, which has twice the strength of the current of the current source 86. The switching network 82 is connected to a third btron source 90 whose power corresponds to four times the strength of the current from the current source 86. Finally is the switching network 84 is connected to a current source 92, the current of which is eight times Strength of the current of the power source 86 corresponds. The power sources 86, 88, 90 and 92 are jointly connected to a voltage supply line 94. continues to be each of the power switches 78, 80, 82 and 84 connected to the common node 90, which is connected to the summing circuit 30 via the line 32.

The switching network 78 is responsive to the binary signal transmitted by the Leiturb 60 is received, in such a way that the power source 8G only is then connected to the node 96 if, for example, the line 60 is a logical Has "1". On a similar track, the electric switches 80, 82 and 84 speak to the Signals at terminals 58, 56 and 54, respectively, to selectively switch off the current sources 88, 90 and 92 to connect to node 96 at which the selected streams can be summed together. The summation of the selected currents at node 96 provides the analog offset signal for summing circuit 30.

The analog signal which is generated by the analog selection circuit 10 is selected according to FIG. 1, is discharged on line 28. According to Fig. 3, the selected analog input signal on line 28 becomes the operational amplifier 98, which has a gain of 1! One11, to the analog input signal to buffer. The output signal of this operational amplifier, which is on node 100 is available, the output line 34 is via the summing resistor 102 supplied. The voltage on node 100 follows the voltage on the line 28 because operational amplifier 98 has "one" gain. However, the voltage on the output line 34 will be versus the voltage on the Node 100 offset due to the voltage drop across resistor 102, which caused by the current flowing from the digital-to-analog converter circuit 52 is delivered.

The magnitude of the offset voltage dropped across resistor 102, corresponds to the size of the BCD number available on terminals 54, 56, 58 and 60 is.

The following is the operating mode with reference to FIG the circuit arrangement according to the invention described.

The control lines 12, 14, 16 and 18 are connected through the terminals 20, 22, 24 and 26 programmed in such a way that one of the number of analog signals which has been picked up by the analog selection circuit 10 is selected. Similarly, the digital multiplexer circuit 50 selects the appropriate one BCD signal, which was stored in the memory circuit 39, and leads this BCD signal to the digital snalog converter 52. The selected BCD signal becomes also decoded by a seven-stage decoding circuit 62 to the corresponding Activate sections of the selected digit in the display unit 64. The control lines 12, 14, 16 and 18 select one of the digits in the display unit 64 so that they is activated in the multiplex process, as is common practice.

In response to the BCD signal passed through the digital multiplexer 50 has been selected, the digital-to-analog converter 52 generates an analog offset signal, as it is based on above 3 was explained. The summing circuit combines the selected analog input signal with the analog offset signal and provides an analog output signal on line 34, as also above has already been explained with reference to FIG. 3.

The strength of the current in the power sources 86, 88, 90 and 92 and the The value of the resistor 102 according to FIG. 3 are chosen such that the offset voltage, which drops across resistor 102, and only as a result of the action of the current source 86, is greater than the strength of the noise voltage, which the analog input signal is stamped on. For example, the offset voltage could be due to a power unit I are set at the Liiderstand 102 so that it is 0.1 volts. this leads to to the fact that the BOD signal 0001 the analog output signal lur, 0.1 volts further in offset the positive range than the analog input signal. The BGD number 0010 causes the analog output signal to go 0.2 volts further into the positive range is offset as the analog input signal and so on.

The analog output signal is then from the analog-to-digital converter 36 added. According to FIG. 2, the number of comparators 66 could be arranged in this way be that an analog output signal is determined in the range between 0 and 10 volts will. In this case, the terminal 70 could be connected to a positive supply voltage of + 10 volts, and the conductor network, which through the in series connected resistors 68 would be reference voltages of +1 volts, +2 Volts, ... deliver +9 volts.

After the comparators responded to the analog output signal have the data inputs of the plurality of latch circuits 72 thereby activates that the first control signal or clock signal is fed to terminal 38, through which the number of interlock switches 72 for the new comparator output signals Take note. The output signals of the latch circuits are through the Coding circuit 74 coded. ienn for example the analog AttiS output signal, which is picked up by terminal 34 is +4.5 volts, then the comparators, which have reference voltages of +1 volts, +2 volts, +3 volts and +4 volts have a logical "one", while those comparators which have reference voltages of +5 volts or above, each a logical one zero?; would be present. The digital coding circuit 74 codes this information into the SCD-Lahl 0100 or 4, so that this indicates that the analog output signal stronger -'- is positive than +4 volts, but less positive than +5 volts.

After the first expensive pulse or clock pulse out of its unverri egelten Position has returned (input activated, i.e. after this control pulse or the clock pulse has returned to its locked position (input switched off), will send the BCD result on lines 40, 42, 44 and 46 to the appropriate Place stored in the memory circuit 39, with the aid of the second control pulse or clock pulse. If there is an overlap of the first and the second control pulse is prevented, a mutual influencing of these impulses with one another avoided that could otherwise occur in the Räckführpfad. A cycle is now complete, and the control lines 12, 14, 16 and 18 are again like this programmed that the next analog input signal for the beginning of the next Cycle is selected.

The hysteresis effect of the circuit, which has already been addressed above is described below with reference to the illustration in FIGS. 4 and 5. As shown in 4 it is assumed that the analog-to-digital converter Has transition points at steps of 1 volt, with the vertical axis the voltage indicates. It is also assumed that an offset voltage of 0.1 volts to the analog input signal is added to whom -l exceeded a transition point will. The solid line in Fig. 4 represents the analog output signal, while the dashed line indicates the analog input signal. The difference between these two signals corresponds to the size of the offset which is caused by the summing circuit is brought about or added. When the analog input signal is less than one volt, x becomes one of the current sources 86, 88, 90 or 92 according to FIG 3 connected to the summing circuit 30. what is the analogue in this area output signal is the same as the analog input signal, and the solid as well as the dashed lines coincide with each other.

If the analog input signal becomes more positive than 1 volt, connect the power switch 78 the btromquelle 86 with the buzzing circuit 30, what to a positive offset voltage of 0.1 volts. Similarly, if the analog output signal exceeds the transition point of 2 volts, the current switch 78 is turned off and the power switch 80 is activated, removing the power source 88 is connected to the summing circuit 30, resulting in an offset voltage of 0.2 volts leads.

Fig. 5 shows in more detail a portion of the Representation in FIG. 4, specifically in the range of 2 volts. It should be noted that then when the analog input signal (dashed line) reaches 1.85 volts, the analog output signal is offset by 0.1 volts and then corresponds to +1.95 volts. When the analog input signal reaches +1.9 volts, the analog output signal crosses the transition point of 2 volts, reducing the BOD output of the Analog-to-digital converter is changed from 0001 to 010. An additional offset voltage of 0.1 volts causes the analog output signal to rise to +2.1 volts. if the analog input signal returns to +1.85 volts, which is due to noise may be the case, the analog output signal remains above the transition point of 2 volts, as illustrated in FIG. Therefore the BOD output signal remains of the analog-to-digital converter at 0010, and the negative transition of the analog input signal, which could be triggered by noise is suppressed.

The invention therefore makes use of the knowledge that by introduction or consideration of a hysteresis effect in the analog input signal the corresponding digital output signal can be stabilized, which in turn the possibility offers that a corresponding display device can be read out more easily can be.

Claims (11)

Claims 9 circuit arrangement for controlling an analog-digital converter, to which a first analog signal is fed to an input cycle and which continues responds to a second analog signal to provide a digital output signal, in that there is an analog circuit arrangement (30) between the input terminal and the analog-to-digital converter is arranged, which is based on the responds to the first analog signal to provide the second analog signal in such a way that that this has an offset with respect to the first analog signal, and that an offset control circuit (52) is provided which is connected to the analog-to-digital converter (36) is connected and responsive to the digital system such that the offset is controllable between the first analog signal and the second analog signal. 2. Circuit arrangement according to claim 1, characterized in that the offset control circuit (52) comprises a digital-to-analog converter, which on the digital signal is responsive to provide a third analog signal (32), and that the analog circuit is based on the first analog signal as well as on the third analog Signal responds to provide the second analog signal. 3. Circuit arrangement according to claim 2, characterized in that the digital signal is displayed in BCD format. 4. circuit arrangement according to claim 1, characterized in that, et that the analog-to-digital converter (36) has a plurality of comparator circuits (66), each of which responds to one of the number of reference signals (68) that further in each comparator circuit responsive to the second analog signal to be a digital display of the second analog signal in relation to one of the number of reference signals to deliver, and that a coding circuit (74) is provided which on the digital View of each of the plurality of comparator circuits responds to the digital Signal to deliver. 5. Circuit arrangement according to claim 4, characterized in that the digital signal is displayed in BCD format. 6. Circuit arrangement according to claim 1, characterized in that a memory circuit (39) is provided which is connected to the analog-to-digital converter (36) is connected and is designed such that it receives a control signal (48), to store the digital signal which is supplied by the analog-to-digital converter will. 7. Circuit arrangement according to claim 6, characterized in that the memory circuit (39) is responsive to the control signal to generate the digital signal to be supplied to the offset control circuit. 8. Circuit arrangement for controlling a multiplex analog-digital converter, which is a plurality of first analog signals for conversion into a decimal Representation picks up and has address terminals to a number of selected signals record, further comprising an analog selection circuit to the Record majority of the first analog signals and apply them to the selected ones Signals to address in such a way that one of the number of the first analog signals is selected, and wherein the analog-to-digital converter to a second analog signal is responsive to provide a digital output signal characterized in that an analog circuit (30) is provided which is between the analog selection circuit and the analog-I) igital converter is arranged that the analog circuit on the responds to selected signals from a plurality of first analog signals, to provide the second analog signal which is opposite to that of the plurality from the first analog signals selected signal has an offset that further a memory circuit (39) is present which has a plurality of memory locations which is connected to the xualog-digital converter and on the selected Signals responds to select one of the memory locations that the memory circuit has a terminal (48) which is used to receive a control signal that the Memory circuit responsive to the control signal to send the digital signal to a to store selected memory location, and that the offset control circuit (52) is connected to the memory circuit and is responsive to the digital signal which is stored in the selected location to determine the offset between the selected from the plurality of the first analog signals and the second to control analog signal. 9. Circuit arrangement according to claim 8, characterized in that the digital signal, which is supplied by the analog-to-digital converter, in BCD format is pictured. 40. Circuit arrangement for controlling an analog-digital converter, which is to be prevented from noise, which is an analog input signal is assigned to cause instability in a digital output signal could, where there is an input terminal that receives a first voltage, and wherein the analog-to-digital converter is responsive to a second voltage, ur. ei; e Multiple digital signals to deliver, which are the magnitude of the second voltage represent, characterized in that an analog circuit (30) is provided, which is arranged between the input terminal and the analog-digital converter, that the analog circuit has a terminal (32) which is used to provide a Versatzsig nal to record, which has a regulated variable that the analog circuit on the first voltage and responsive to the offset signal to produce a second voltage to deliver that the second voltage differs from the first voltage by such a Offset voltage differentiates that its size corresponds to the size of the offset signal, and that there is a displacement control circuit (52) connected to the analog-to-digital converter is connected and responsive to the plurality of digital signals to produce the offset signal to provide and to control the size of the offset signal in such a way that it of those Size corresponds to which is represented by the majority of the digital signals. 11. Circuit arrangement according to claim 10, characterized in that that the analog-to-digital converter (36) has a circuit arrangement (68) which serves to generate a plurality of transition voltages that the analog-to-digital converter is to operate so as to detect a change in the plurality of digital signals in response, causes the second voltage im essential that the change is equal to one voltage from the plurality of transition voltages In the majority of the digital signals we @ t in such a way that the second voltage is changed to a value that is more positive than a voltage from the Number of transition voltages when the change in the majority of the digital Signals to a presentation of a greater signal strength takes place, and that the change in the majority of the digital signals leads to the fact that the second voltage to one Value is changed, which is more negative than one voltage from the plurality the transition voltages when the change in the majority of the digital signals to display a lower signal strength.