DE2614362A1 - Composite output signal generating device - produces signal in dependence on digital signal with two parts using series of switching elements - Google Patents

Abstract

The system comprises first switching elements (16) for generation of a first signal, and this first signal is able to vary in a first way in accordance with the first part of the data signal. There are second switching elements (12, 18, 20) which are used for generation of a second signal, which varies in a second way in accordance with the second part of the data signal, and there are logic circuits (22, 24, 26) which are connected to the first and second switching elements (10, 16in order to combine the two signals into a composite signal.

Description

Digital-to-analog converter for generating a large number of defined output amplitude values The present invention relates to a digital to analog converter and in particular to a digital-to-analog converter with a high resolution, i.e. for generating a large number of precisely defined output values with a small spacing.

A digital to analog converter is an electrical or electromechanical one Device that generates an analog output signal as a function of a digital input signal erzeuqt whose amplitude depends on the digital input signal. While a variety of different systems for Creation of this purpose have been realized, the digital-to-analog converter works according to the invention a "pulse width modulation". This means that one pulse with one defined length (width), hereinafter referred to as duty cycle, is generated, where this duty cycle is variable in accordance with the digital input signal is. A time average is formed from the correspondingly wide pulse, so that an analog signal is formed. While using such digital-to-analog converters be used to carry out various functions is the digital-to-analog converter according to the invention preferably intended for use in an electronic Voting system, as it is described, for example, in patent application P, ........ (U.S. Patent Application Seral No. 565 121 dated April 4, 1975) entitled "Fully Electronic Voting system with a semiconductor memory "of the applicant (inventor: Louis-Pierre Zimmerman).

For many applications, the conversion accuracy (resolution) is one Digital-to-analog converter crucial. E.g. we in a voting system which is described in the above application, a resolution of 1 to about 15,000 required to achieve the necessary fine tuning of around 30 KHz. In one Digital-to-analog converter dependent on an input signal modulated in the pulse width the degree of triggering can be achieved by increasing the number of bits in the input data signal increase. However, the immediate consequence is the increase in the number of bits the input signal either; that pulses of a larger period through the pulse width modulator must be generated as part of the converter or that the clock, which the pulse width modulator controls must have a higher frequency. The integral (time average) of the generated Impulses takes place in a low-pass filter with a relatively large Time constant. At a clock frequency of this order of magnitude of 1 MHz, the larger pulse period a lowering of the filter frequency to an unacceptable level Delay (on the order of 10 seconds).

On the other hand, increasing the clock frequency would be logical Circuits outside of normal availability require and special high frequency digital circuits need what is difficult and expensive to fabricate, and therefore what is commercial Application of the system in the highly competitive television industry would make impossible.

It is therefore an object of the present invention to provide a digital-to-analog converter to provide high resolution, this increase in resolution being achieved without lengthening the pulse period or increasing the clock frequency.

Another object of the present invention is a digital-to-analog converter to create, with high resolution, in which two independent pulses are generated, each of which has a variable duty cycle in accordance with part of the having digital input signal.

It is a feature of the invention to provide a digital to analog converter with high resolution, in which two pulses with variable duty cycles are generated one of which is converted into a variable amplitude signal. Another feature of the invention is the provision of a digital to analog converter high resolution in which the pulse with variable duty cycle and the amplitude modulated signal to form a composite signal in a more defined manner Waveform can be combined.

In accordance with the present invention, the digital-to-analog converter high resolution first and second pulse width modulators, one of which each is designed to receive part of a digital input signal. E.g. becomes a digital input signal, which consists of m + n bits, where n is the least significant Bits are divided into two parts so that the first pulse width modulator m bits and the second pulse width modulator takes n bits. Each of the pulse width modulators generates a pulse with a duty cycle that varies in accordance with the part of the data recorded by it. The duty cycle of each of the generated Impulse is divided into a number of steps determined by the number of bits are contained in the corresponding part of the data signal, namely -2m and nich 2 and 2n. Both pulse width modulators are controlled by the signals of a clock generator switched on, the clock pulses also for synchronizing the other circuits in the rest of the system in which the converter is a part can.

The pulse train generated by the second pulse width modulator, which takes the digital input signal with n bits, is generated, is sent to a Analog switches transmitted to generate defined voltage levels that exceed a Filters are averaged in time to produce a signal of varying amplitude to generate, which is divided into 2n stages. The impulses with changeable Duty cycle, which is determined by the pulse width modulator for the m bits Part of the input signal are generated, also control an analog switch, about impulses with a defined voltage level. This signal and the variable in amplitude signal, which from the output of the second Pulse width modulator is derived, is combined in a logic circuit, to get a combined output signal. A time grid generator which is connected to the clock generator, is intended to control the logic circuit, to guarantee that the input signals fed to the logic circuit in evaluated in a predetermined manner in the composite output signal. The composite signal is then passed through a low-pass filter, preferably an RC low-pass filter, supplied, which has a relatively large time constant, so that the composite Signal is averaged over time to produce an analog signal whose amplitude is variable in 2m + n discrete steps, what makes the desired resolution possible will.

In this way, the desired resolution can be achieved through the digital-to-analog converter according to the invention by increasing the number of bits in the digital input signal can be increased without lengthening the pulse period or requiring any unusual high clock frequency. As a result, conventional digital circuitry can be used and no unrealistic time lag is assumed.

For this purpose, the digital-to-analog converter contains the Invention a first and second pulse width modulator, each of which is one Pulse is generated which has a variable duty cycle in accordance with the corresponding parts m and n of a digital input signal, which is composed of m + n Bits. The duty cycle of the pulse generated by each modulator, is divided into a number of steps (2m or 2n) which are divided by the number of Bits in the corresponding part of the Input signal is determined. Separate analog switches are used in conjunction with each pulse width modulator, to generate pulses with a defined signal level.

The pulse train derived from the second pulse width modulator (which contains the part of the input signal that contains the n least significant bits contains) is averaged over time so that a signal is generated whose amplitude variable in 2n steps in accordance with the duty cycle Impulses. The variable duty cycle of the pulses and the signal with the variable Amplitude are combined in a logic circuit to form a compound Create waveform.

A time grid generator is provided to connect the logic circuit control so that the composite output signal correctly has the ratio of each that reproduces input signals. The composite signal is then passed through a low pass filter with a relatively large time constant averaged in time to an analog signal to create. This increases the resolution of the digital-to-analog converter to 1: 2 m + n by increasing the number of bits from m to m + n in the. Input digital signal without increasing the time period of the generated pulses, causing unacceptable delays and time constants of the filter would be a prerequisite, and without the use of higher frequencies Clock pulses, which in turn special circuits to process these higher Frequencies would make it necessary to demand.

To complete these statements and to explain others Features and advantages of the invention, relating to a digital to analog converter with high resolution, as defined in the appended claims, is an embodiment in conjunction with the accompanying drawings described, in which like reference numerals relate to like parts. Show it: Fig. 1 is a block diagram of an electronic voting device for use in communications systems with tuning elements controlled by a tuning signal, which the digital-to-analog converter required after the invention and Fig. 2 is a block diagram showing the circuitry of the Digital-to-analog converter according to the invention shows.

As can be seen from Fig. 1, the fully electronic tuning device, incorporating the present invention for use in messaging systems determines in which the tuning elements are controlled by a tuning signal. Such tuning elements can be used, for example, by a varactor tuning device be realized, which has a number of diodes, their capacitance as a function is varied by an input voltage.

Because the voting system described here is an example of one of the various possible uses of the invention, this system is in its Function described in the interest of being able to better recognize the value of the invention. Such a system has an input signal generator, here as a keypad A is shown which has a series of snap fasteners and in which a channel selection signal is generated by any manipulation of the push buttons and is given to the logic control circuit B. The logic control circuit B contains a decoding circuit which converts the channel selection signal into an address signal, which can be used to address a memory C. The memory C is preferably an electronically controllable, permanent one that can be overwritten word by word Semiconductor memory, what one Has a plurality of storage locations. The number of storage locations in memory C corresponds to the number of different ones Frequencies to which the varactor tuning device D is to be tuned. Each of the storage locations of the memory C has a capacity of around one digital word a length of m + n bits. For example, memory C has 100 memory locations, each of which is designed to store a 14-bit digital word Length.

The number of storage locations corresponds to the required storage space for data corresponding to the 12 VHF channels and the 70 UHF channels, in addition to the Space for C.A.T.V. channels and other memory functions.

The address signal generated by logic control circuit B. is transmitted to a display device control and channel addressing circuit E, in which the address signal is converted into a code which is suitable for the To control display device F, which have any structure known per se can. The display device F is used to display the number of the selected channel.

In addition, the decoded address signal is used to control the band selection circuit used in the varactor tuner D. The original address signal becomes also used to select the memory location in the memory F, the digital Contains data which corresponds to the channel which was activated by pressing the Keypad A is selected.

The logic control circuit B contains a control circuit of the data flow to and from the addressed memory circuit in memory C, so that the data stored in the addressed memory location is sensed and temporarily in a section of the circle B. The saved data will and the processed signal is in the form of a pair of pulse trains zu'den remaining parts of the digital-to-analog converter G transmitted, which the Pulse trains are converted into an analog voltage that generates the desired resolution the corresponding vote, which in turn directly the varactor tuning device D changed to select the desired frequency.

It should be noted that a fine-tuning pulse generator H in Operational connection with the control circuit B is such that the stored in the buffer Data word can be changed before it is transferred to the tuning voltage fine-tune the varactor tuner D. After the data word is changed by the fine-tuning pulse generator, the changed data word is automatically stored back in the addressed memory location of the memory C, so that if the same channel is called up again, the data word to the addressed memory location reflects the fine-tuning value. In this way, the fine-tuning once set is made Part of the data word so that the fine tuning of a channel is retained for later use.

Fig. 2 shows the digital-to-analog converter according to the invention in Detail. The converter contains a first and second pulse width modulator (pulse length modulator) 10 or 12, which is part of the logic control circuit B. This part of the Circle B receives the scanned data from the addressed memory location in memory C. Data. Here, the pulse width modulator 10 takes the more significant m bits of the sampled signal word. It is assumed that the digital Word has 14 bits and that the pulse width modulator 10 receives the more significant ten bits of this word. The pulse width modulator 12 takes the n low order Bits of the digital input word. In the assumed case, the pulse width modulator receives 12 the four low-order bits of the 14-bit digital word. A clock signal generator 14 feeds both pulse width modulators 10 and 12 to the internal flow of the same to synchronize.

The pulse width modulator 10 generates a pulse train with a constant Frequency, the pulse duty cycle of which is variable in accordance with the higher-order ones m bits of the input word. This data word is a binary number within a certain Area that is determined by the number of input bits. Therefore this one can Part of the binary number Accept a value between 0 and 210.

The duty cycle of the pulse provided by the pulse width modulator 10 is generated corresponds in its duration to the value of the binary number compared to the total area. For example, if this number is 512 (half of the highest possible Digit 1024 (210)), then the duty cycle should be equal to half of the period of the Be an impulse train. In this way, the duty cycle of the output pulses is proportional to the digital input value of the modulator.

The clock pulse generator 14 generates clock pulses with a predetermined Frequency, e.g. 1 MHz, with each pulse having a duration of approximately 1 microsecond having. Since the digital input signal in the pulse width modulator 10 is a binary digit with m bits, this number will be 2m or approximately 1000 (m = 10) different Values on. The from Pulse width modulator generated pulse accordingly a duty cycle, which is divided into 2m discrete steps (approximately: 1: 1000), where each of the steps lasts approximately one microsecond (fixed by the clock frequency) varies. Therefore the output pulse train has a constant one Frequency of 1 KHz and a period of approximately one millisecond.

The pulse train generated by the pulse width modulator 10 is transmitted to a Analog switch 16 transmitted, which is intended to generate an output signal depending on the duty cycle of the input pulse train supplied to it. The analog switch 16 switches between two voltages V1 and V2. These tensions are supply voltages and are derived from the power supply. The task of the analog switch 16 is that generated by the pulse width modulator To give pulse train defined and precise voltage levels. These voltage levels are determined by the supply voltages at the analog switch. In the one shown Embodiment, V is a constant voltage, which is from a not shown Voltage source is derived. V2 is connected to ground (earth) so that the pulse train Has pulses with an amplitude equal to V1. The pulse train is shown graphically immediately above the analog switch 16.

The pulse width modulator 12 takes the n least significant bits of the binary input word. This pulse width modulator also produces one Pulse train with constant frequency and variable duty cycle of the pulses in accordance with the binary input value. However, this pulse train is divided into 2n discrete Steps. Since n = 4 in the chosen embodiment, can 16 discrete steps can be distinguished in the pulse width modulator (actually only 15, because the internal structure of the modulator is able to process the binary number 0000 as an input value), each step lasting approximately 1 microsecond (determined by the clock frequency) so that the pulse frequency is 67.2 kHz. Also, as described above, is the duty cycle of the pulses of the pulse train depending on the value of the binary word within the specified range. In In the exemplary embodiment, the range includes 24-1, that is from 1 to 15 and therefore The duty cycle can be divided into 15 discrete steps.

The output value of the pulse width modulator 12 is sent to the analog switch 18, which corresponds to the analog switch 16. The switch 18 generates an output pulse train with constant frequency, the duty cycle for the pulses corresponds to the duty cycle of the pulses, which are transmitted by the pulse width modulator 12 are derived, but with defined and precise voltage values. As well as described above, is one of the voltage terminals of the analog switch 18 connected to a constant voltage source, not shown, while the other Voltage connection V2 is connected to ground. A graphic representation of the impulse Zug is shown immediately above switch 18. It can be seen that the period of the pulse train derived from the pulse width modulator 12 is 15 microseconds is, during the pulse derived from the pulse width modulator 10 one period of one millisecond. The period of the pulse trains are accordingly accordingly different. The times in the graphical representations of the various Impulse shows this difference.

The output values of the analog switch 18 are transmitted to the filter 20, which is preferably made up of RC elements and a relatively large Zeint constant so that the pulse train is averaged over time to obtain a direct current signal to be generated with an amplitude which corresponds to the duty cycle of the pulse duration modulator 12 generated pulses corresponds. This voltage is shown graphically in the drawing above the filter 20. This DC voltage has an amplitude which can be different in approximately 2n discrete levels according to the division of the pulse derived from the analog switch 20 zuges.

The output values of the analog switch 16 and the output value of the Filters 20 are both transmitted to a link circuit 20, where they are transferred to a combined signal are composed, which approximated different values in 2m x 2n = 2m + n different steps. Accordingly points the initial value of the logic circuit 22 incremental values of approximately 1: 15,000 on. A timing generator 24 is dependent on the clock signals of the generator 14 controlled and generates a clock pulse for the logic circuit 22 with a predetermined Pulse width. In the selected exemplary embodiment, the timing generator receives Clock signals of the generator 14 of 1 MHz and generates pulses of 1 microsecond for the logic circuit 22. The logic circuit 22 combines the two input signals in a predetermined ratio depending on the pulses of the timing generator 24.

The output signal of the logic circuit 22 is a pulse train constant frequency with one pulse period of 1 millisecond. The logic circuit 22 generates this output signal by accepting the from Analog switch 16 originating input signal, except for its full duration for the last microsecond from this area. In the last microsecond of the Output pulse generates the logic circuit 22 a signal in accordance with the input signal derived from the filter 20. The timing generator controls accordingly 24 a fade-out of one microsecond, during which the logic circuit 22 emits a signal as a function of the input value of the filter 20. The rest of the time of one millisecond, the circuit 22 gives the signal as a function of the input value of the SC holder 16. The output value of the logic switch 22 is accordingly a composite signal that is derived from the output value of the switch for its lasts for the full duration, with the exception of the last microsecond, during which the composite signal passes the output value of the filter 20.

This composite pulse train is shown graphically above the Link circuit 22. The composite output signal of the link circuit 22 is fed to the filter 26, a low-pass filter, preferably with RC elements, which has a relatively large time constant. The filter 26 is used to average the Amplitude of the composite signal to produce a DC voltage whose Amplitude is determined by the output signal of the logic circuit 22 and which can accordingly assume about 2m + n discrete values (1: 15,000). The initial value of filter 26 represents the input tuning which is determined, the varactor tuner D to control to select a desired frequency depending on a binary word, which was sensed from the addressed memory location in memory C.

In this way, the present invention realizes a digital-to-analog converter of a pulse width modulation type capable of analog voltage with a very high resolution (quantization). The quantization will generated by a correspondingly large number of bits in the input signal. This would usually require a very high clock frequency or increased pulse period. However, by dividing the input signal and generating pulses into Dependence-on each of the parts of this signal and then assembling it the momentum averaged over time would lead to the demand for an increased one Clock frequency eliminated and therefore no circuit arrangements for higher Frequencies than usual needed.

Also the need for larger pulse periods, which is an unacceptable Would require a delay system with regard to the characteristics of the filters, to shape the analog signal is also not given.

Albeit a simple embodiment of the present invention has been set forth above for purposes of illustration, it will be apparent that many variations and modifications can be made. It is intended, to cover all such variations and modifications by the present invention, as defined by the following claims.

-Patent claims-

Claims (37)

Claims device for generating a composite Output signal dependent on a digital signal with a first and a second Part, characterized by first switching elements (10, 16) for generating a first Signal that is in a first manner dependent on the first part of the data signal is changeable, second switching elements (12,18,20) for generating a second signal, which can be changed in a second way depending on the second part of the data signal is, and logic switching elements (22,24,26) which are in operative connection with the first signal generation switching elements (10, 16) and the second signal generation switching elements (12,18,20) for the interconnection of the two signals to form a composite output signal to create. 2. Device according to claim 1, characterized in that the second Signal generating switching elements (12, 18, 20) a filter for temporal averaging of the output signal (20) have. 3. Device according to claim 1 or 2, characterized in that the first signal can be changed with regard to the pulse duration. 4. Device according to claim 1, 2 or 3, characterized in that the second output signal is variable in amplitude. 5. Device according to one of claims 1 to 4, characterized in that that the composite output signal has a period of X seconds and is divided into a part, which from the first signal and which from the second Signal is derived, the first part of the composite signal being a changeable Duration over the range of Obis X-R seconds and the second part of the compound Output signal has a duration of R seconds. 6. Device according to claim 5, characterized in that the amplitude of the first signal part is constant over the duration. 7. Device according to Claim 6, characterized in that the second Signal part has a variable amplitude. 8. Device according to one of claims 1 to 6, characterized in that that the second part of the data word has n bits and that the second signal one Amplitude, which can be changed in approximately 2 steps. 9. Device according to one of claims 1 to 8, characterized in that that the first and second part of the data word consists of m and n bits and that the composite output signal changeable in approximately 2m + n discrete steps is. 10. Device according to one of claims 1 to 8, characterized in that that the first part of the data word has m bits, so that the first signal approximates 2m can be changed in discrete steps. 11. Device according to one of claims 5 to 10, characterized in that that the second part of the composite signal has a duration of one microsecond having. 12. Device according to one of claims 1 to 11, characterized in that that the logic element (23,24,26) a logic circuit (22) with a having first and second input and an output, the first or second Input for receiving the first and second signals are used that a time generator (24) is in operative connection with the logic circuit in order to specify a time interval for switching the first input through to the output for a second predetermined one Time interval. 13. Device according to claim 12, characterized in that the first predetermined time interval X-R seconds and the second predetermined time interval R seconds. 14. Digital-to-analog converter for converting one consisting of m + n bits digital signal into an analog signal, characterized by first switching elements (10,16) for generating a first signal which is dependent in a first manner with m bits of the digital signal, second switching elements (12, 18, 20) for generation a second signal which is changeable in a second manner in accordance with with the n bits of the digital signal, as well as logic elements (22,24) for Linking of the first and second signals via a filter (26) to the analog Shape output signal. 15. Converter according to claim 14, characterized in that the two Signals can be subdivided into quantizable levels. 16. Converter according to claim 14 or 15, characterized in that the change in the first sense consists of a change in the pulse lengths. 17. Converter according to one of claims 14 to 16, characterized in that that the change in the second sense represents a change in amplitude. 18. Converter according to one of claims 14 to 17, characterized in that that the first signal can be changed in approximately 2m steps. 19. Converter according to one of claims 14 to 18, characterized in that that the second signal can be changed in approximately n 2 steps. 20. Converter according to one of claims 14 to 19, characterized in that that the combined output signal can be changed in approximately 2m + n steps. 21. Electronically working voting device with the voting signal controlled tuning elements consisting of an input signal generator, a Memory with a large number of memory locations for storing m + n bits, control devices, which are connected to the output of the signal generator for addressing a Storage space in the memory depending on the generation of the input signal and to control the flow of data from the addressed memory location, a Switching device, which is connected to the memory to form a variable signal of the data word stored in the addressed memory location and a filter for converting the variable signal into a tuning signal, wherein a switching device for generating a composite waveform signal which is dependent on the stored data signal, characterized by switching elements to generate a first waveform depending on the m bits of the stored Data signal and switching elements for generating a second waveform depending on the n bits of the stored data signal. 22. Tuning device according to claim 21, characterized in that the first signal is changeable in a first way, depending on the m bits of the stored data signal and the second signal in a second sense of the n bits of the stored data signal and that for generating a composite Wave form a device is provided which with the switching element (10,12) for the first part of the signal and the switching element (12,18,20) for the second part of the signal is connected. 23. Device according to claim 21 or 22, characterized in that that the first signal is varied in pulse duration. 24. Device according to one of claims 21 to 23, characterized in that that the second signal is varied in amplitude. o 25. Device according to one of claims 21 to 24, characterized in that that the composite output signal has a period of X seconds and one area for the first and one area for the second signal the first part of the composite signal having a variable duration over the range from 0 to X-R seconds and a range for the second signal of R seconds. 26. Device according to one of claims 21 to 25, characterized in that that the amplitude of the first signal is kept constant over the pulse duration. 27. Device according to one of claims 21 to 26, characterized in that that the second signal has an amplitude which can be changed in two 2n steps is. 28. Device according to one of claims 21 to 27, characterized in that that the composite signal is distinguishable in 2m + n discrete steps. 29. Arrangement for generating an output signal depending on one given input value, characterized by switching elements (10, 16) for generation a series of a first given number of pulses of a given fixed Output characteristic and to select a second given number of these pulses, where the second number is equal to or less than the first given number and depends on the input value, switching elements (18, 20) for generating an additional Pulse, switching elements (12) for controlling the output characteristics of this pulse depending on the input value and logic elements (22,26) to generate a Output signal by combining the second given number of pulses with the compound pulses. 30. Arrangement according to claim 29, characterized in that the first Number of pulses each has a defined uniform amplitude. 31. Arrangement according to claim 29 or 30, characterized in that the first number of pulses each have the same amplitude and duration. 32. Arrangement according to claim 29 to 31, characterized in that the controlled output characteristic of the composite pulse as a function of the amplitude is. 33. Arrangement according to one of claims 29 to 32, characterized in that that the duration of the composite pulse is essentially identical to that Duration of the impulses of the first number. 34. Arrangement according to one of claims 29 to 33, characterized in that that the input value has a first and a second part, that the first Part of the number of pulses determines which the pulse train of the second is given Number contains and that the second part is the output characteristic of the composite Impulses. 35. Arrangement according to one of claims 29 to 34, characterized in that that the controlled output characteristic of the composite pulse is amplitude dependent is. 36. Arrangement according to one of claims 29 to 35, characterized in that that the amplitude of the composite pulse is variable in defined steps. 37. Arrangement according to one of claims 29 to 36, characterized in that that the input value is a digit with two parts, one of which is m and the other n Has bits and that the composite pulse is changeable is in 2n discrete levels.