DE2808580C2 - Microcomputer with a microprocessor integrated on a chip and a read-only memory - Google Patents

Description

The present invention relates to a microcomputer according to the preamble of claim 1. From the DE-AS 14 99 226 a device for checking errors in an electrical data processing system is known, in which controllable connection devices are provided that either the test command decoder connect to the control store or to the main store. A read-only memory (control memory) checked with the main memory serving as a test aid

When creating user programs for the functional sequence control of devices or machines on the other hand, microcomputers proceed in such a way that the user program which has been drawn up from a program flow chart and which has not yet been used it is known whether it is finally in the correct form, not yet fixed in a read-only memory (ROM or PROM) of the controlling microcomputer is written, otherwise the read-only memory in the case of Errors in the program would become worthless. Rather, the user agent is initially in a Development microcomputer system with the help of a test program (real-time test adapter program; im The following ETA program is called). For this purpose, the user program is stored in a memory written with random access (hereinafter referred to as user program memory), which by means of a switch can be coupled to a microprocessor (CPU) of the development microcomputer system, wherein the switch then at the same time a memory containing the ETA program from the microprocessor uncoupled The device to be controlled is then in its functional sequence of the microprocessor with the help of the user program controlled In certain points (so-called breakpoints) the user program memory decoupled from the microprocessor and the ETA memory coupled to the microprocessor for test purposes.

Microcomputer development systems are known. An example of such a development system is in a prospectus from Intel Corporation. No. 98 005 01 A, June 1977 with the title »ICE-48 MCS 48

In-Cireuit Emulator «(» iCE-48 «and» MSC 48 «are trademarks of Intel Corporation).

A device controlled by a microcomputer can be great! characterized by three parts, namely the device hardware, a microprocessor (CPU) and a user program memory. When working with an emulation and test Adapitf the CPU from the remote device to be controlled to be its place is a connection to the emulation and test Adafier, as essential elements a similar CPU, an ETA memory and a switch rar coupling of CPU either to the device to be controlled or to the ETA memory. Such a configuration is shown schematically in FIG. 1 shown A device 1 to be controlled with a user program memory 2 can be coupled to an emulation and test adapter, which contains a CPU 3 and an ETA memory 4. or couple to the device to be controlled 1 (extended switch position).

In accordance with the two possible positions of the switch 5, the one enclosed in dashed lines in FIG. 1 operates and emulation and test adapters labeled ETA in two states.

In the first state, the CPU 3 is connected to the device 1 via the switch 5 and interprets this in the User program memory 2 standing user program.

In the second state, the CPU 3 is connected to the ETA memory 4 via the switch 5, see above that the emulation and test adapter is virtually separated from device 1. The CPU 3 can use the im ETA memory 4 running test program execute independent operations.

The transition from the first state in which the CPU 3 is coupled to the user program memory 2 in the second state, in which the CPU 3 is coupled to the ETA memory 4, can be the emulation and Test adapter can be specified by a programmer as a »breakpoint <. The event can either come from the device itself (e.g. faulty reaction of the device, the cause of which is in the User program is searched) or obtained from the sequence of the user program (for Example running through a program area recognized as critical).

During the transition mentioned, the contents of all CPU registers are initially stored in the ETA memory 4 saved so that they can later be issued for diagnostic purposes. The CPU registers are allowed to at least initially not be used, because otherwise their hooks would be changed. For this reason the switchover requires a considerable amount of hardware, because initially it is insufficiently dependent on the CPU 3 can be supported.

The transition from the second state, in which the CPU 3 is coupled to the ETA memory 4, to the first The state in which the CPU 3 is coupled to the device 1 to be controlled takes place via a corresponding from bo command given to a programmer. This initiates a test run of the user program. This switchover is preceded by a program section in the ETA memory, which in the CPU 3 contains the internal Sets the register to specified values so that the <> 5 User programs anywhere with a defined state of the CPU 3 can be started. After the CPU register «I; may be used more because they have already been set to certain values, is a relatively high level of hardship for this too. e-Auiwi:; d necessary «.

One-chip microcomputer with integrated on a chip Microprocessor and read-only memory (PROM) are z. B. from "Electronic Engineering", February 1977, issue 588, pages 59 and 61, known. However, they do not have two memories that alternate are to be switched to an instruction counter and an instruction register with an instruction decoder connected to it.

When using such microcomputers integrated on a semiconductor chip, there is an opposite the arrangement according to FIG. 1 an essential difference in that a CPU and a program memory are integrated in the form of a read-only memory (ROM) on a single chip. The occurring Relationships are shown in FIG. 2 when using an emulation and test adapter F i g. 2 becomes the user program memory with the CPU 3 and the ROM 3 'integrated with it on a chip 2 removed from device 1 ^ r. Via the connection of the emulation and test adapter with the device to be controlled is only the input / output of the microcomputer 3, 3 'via a Input / output unit 6 handled

Since the ROM 3 'cannot accept the possibly faulty user program that has yet to be changed, this must be in a further external user program memory 2 in the emulation and test adapter be accommodated. Furthermore, the emulation and test adapter again contains a switch 5 as well another memory 4 for the ETA program. The CPU 3 must not use the (worthless) program in the Interpret ROM 3 ', but must read all commands from outside. An emulation and test adapter according to F i g. 2 works in principle in the same way as the emulation and test adapter according to FIG. 1.

The present invention has for its object to provide a microcomputer of the type in question Specify type in which the considerable hardware effort explained above for switching between User program memory and ETA memory can be reduced.

In a microcomputer of the type mentioned at the outset, this object is achieved according to the invention by the im characterizing part of claim * 1 mentioned features solved.

Refinements of the inventive concept are characterized in the subclaims

The invention is illustrated below with reference to FIGS. 3 to 5 of the drawing shown Ausführungsbeispiclen explained in more detail. It shows

F i g. 3 is a schematic representation corresponding to F \ g. 1 and 2 to explain a microcomputer according to the invention,

F i g. 4 is a block diagram of an embodiment a switch provided in a CPU for switching from the user program memory to the Test program memory and vice versa; and

Fig. 5 in scht.natischer block form one in the Circuit according to Figure 4 used address and transfer logic.

Generally speaking, the invention relates to an emulation and Tesi adapter structure with a one-chip microcontroller. In the arrangement according to FIG. j> st die.-; didu. cn angsrepresents that the Cr L 'i um; the ROM 3 'as well as in the arrangement according to F i ₆ \ 2 are shown as a unit. Incidentally, in

3 the same elements as in the arrangement according to FIG. 2 are provided with the same reference numerals.

The invention is based on the assumption that the ETA program, which controls the independent functions of the emulation and test adapter ETA, is fixed and can thus be accommodated in the ROM 3 'of the microcomputer 3, 3'. In order to be able to do this, it is necessary that the CPU either only receives commands from external user program memories 2 or from the ROM 3 'containing the ETA program. For this purpose, a switchover is required in the CPU 3, which is based on FIG. 3 is explained in general. Switching to a switching state in which the CPU 3 only accepts commands from the external user program memory 2 is carried out by means of a command labeled CEP (Call External Program), which requires the address at which the user program in the user program memory 2 is started as a specification shall be. This one

Address variable uiiu durc

Programming vorgcbbnr

is, it cannot be in ROM 3 ', in which the rest of the test program is otherwise accommodated. Furthermore, may No CPU register can be used to accommodate the address as this register was previously on defined, programmable values r> are set. However, since the external user program memory 2 can be designed as read-write memory, this offers itself as a storage medium for the Jump address of the CfP command. The for this Address intended location in user program memory rather 2 must not be used for the user program, since it is also in the user program memory 2 stands. Therefore, the border (to the Example the address 0) of the user program memory j5 2 was chosen so that there are no significant restrictions in the address assignment for the user program entry.

The CfP command is used to switch the CPU 3 from ROM 3 '(i.e. from the ETA program) for executing the user program on the user program memory 2 switched.

The switchover of the CPU 3 from the user program memory 2 to the ROM 3 'containing the ETA program is carried out by another command labeled EIP (Execute Internal Program). This £ YP command can either be in the user program to be tested or entered externally. In the first case, interruptions can be carried out that are obtained directly from the sequence of the user program, while in the latter case external interruptions, which come, for example, from the device 1 to be controlled via the input / output unit 6, can also be taken into account.

The £ 7P command does not require an address specification, because at a transition from the user program memory 2 on the ROM 3 'the ETA program can be started at a fixed point.

When switching from the user program memory 2 bo to the ROM 3 ', the ETA program must immediately after the execution of the £ 7P command, the current register contents in the CPU 3 in an external one Read / write memory can be stored. Since this Memory in the microcomputer 3, 3 'is not available, bi lends itself to this. Purpose of the user program memory 2, if in this memory in addition to the Another space for the specification of the CEP command and the address range for the user program Address areas are reserved for the contents of the CPU registers so that they can be accessed using special transfer operations can be transferred there from the ETA program. This address range is then also locked for the user agent, of course, but this does not mean any significant loss.

A possible embodiment for switching the CPU 3 from the user program memory 2 to the ROM 3 'and vice versa is in FIG. 4 shown.

In this circuit according to FIG. 4 form an instruction counter 20, an instruction register 21 and an instruction decoder 22 parts of the CPU 3 according to FIG. 3. Further components of the CPU not involved in the switchover are in Fig. 4 not shown.

The central switching circuit of the CPU between the (in Figure 4, not shown) and the user program memory ROM 3 'serves a flip-flop 23, the f at a set input 5 by the command EIP and at a RiicksSizeirigSP.g R by the B? hl CFP is controllable. An output Q of the flip-flop? 3 and an output of the command counter 20 are led to an AND gate 24, via the output of which the ROM 3 'is controlled. Furthermore, the output Q of the flip-flop 23 via an inverter 25 and the output of the command counter 20 are led directly to the inputs of an AND gate 26, the output of which leads via cifisn connection 41 to the user program memory.

Two AND gates 27 and 29 are provided for receiving commands from the user program memory, which are entered via a connection 40 or from the ROM 3 '. These AND gates are input directly from the ROM 3' (AND gate 27) or from the user program memory via the connection 40 (AND gate 29) directly controlled! Her A =; ^. ^ Q of the flip-flop ?? is via an inverter 28 to a further input of the AND gate 29 or directly Another input of the AND gate 27. The outputs of the two AND gates 27 and 29 are coupled via an OR gate 30 to the command register 21, which in turn is routed to the command decoder 22.

To output addresses for the user program memory via a connection 42 or the register content: 3 CPU via a connection 43 to the user program memory, an address and transfer logic, which is incorrectly controlled by the EIP command, is provided. The / 7A command can either come to the user program memory via the command decoder 22 or be entered externally via a connection 44. The coupling of the E / P command to the flip-flop 23 or to the address and transfer logic 31 takes place via an OR gate 32.

To explain the mode of operation of the circuit arrangement according to FIG. 4 it is assumed that a CEP command is present which resets the flip-flop 23 via its reset input R so that its output Q is switched to a low level (bit 0). The AND gates 24 and 27 are thus blocked, so that the ROM 3 'can no longer receive any signals from the command counter 20 and also cannot issue any commands to the command register 21. However, since the low level at the output Q of the flip-flop 23 is inverted by the inverter 25, the AND gate 26 is activated so that the command counter 20 via the terminal 41 to the user program memory

can work. Further, since the deep level at the output Q of the flip-flop is also inverted by the inverter 28 23, and the AND gate is switched to be effective 29 so that the instruction register 21 via the terminal 40 Befeh'e of the user program from the ·> user program memory via the connection 40, which are decoded in the command decoder 22. In this switching state, the CPU is switched to the user program memory so that it can process the user program in this memory.

If a position is now reached in the user program in which there is an f / P command, or if an external E / P command is entered via terminal 44, the flip-flop at its set input 5 is activated by this r. Command set so that its output Q switches to a high level (bit 1). The AND gates 24 and 27 are now activated, while the AND gates 26 and 29 are blocked due to the inverters 25 and 28 connected in between. The command counter 20 can now work on the ROM 3 'via the AND gate 24, so that the commands of the ETA program in this ROM are given to the command register 21 and the command decoder 22 via the AND gate 27.

At the same time, the EIP-BeieM activates the address and transfer logic 31 so that the register contents of the CPU and the corresponding address are output via the connections 43 and 42.

Since the address and transfer logic 31 for the 3n above-explained switching process of the CPU in Meaning ('; r invention is not of primary importance, this logic is not explained in detail here.

According to FIG. 5, this logic 31 can be a data transfer stage 51 for taking over the contents of the registers of the CPU as well as an address generator 50 included, which are controlled by an input 52 of the E / P command.

It should be noted that in the circuit arrangement according to FIG. 4 only schematically shows the takeover the content of the command counter 20 of the CPU via the address and transfer logic 31 in de user program memory is shown. However, it is easily possible when switching over from the user program memory on the ROM 3 'containing the ETA program the content of further (not shown) To take over the register of the CPU via the address and transfer logic 31 in the user program memory.

It should also be noted that in the context of the invention, the connections 41 and 42 or 40 and 43 shared lines.

The above-mentioned microcomputer has the significant advantage that an external memory for the ETA program (memory 4 in Figs. 1 and 2) and the complex external switch (switch 5 in the F i g. 1 and 2) can be omitted.

The two commands to be executed, CEP and EIP, require so little additional hardware outlay in the CPU 3 that they can also be built into series production CPU modules without excessive redundancy. This means that serial microcomputers can be used for a real-time test adapter.

For this purpose 2 blue drawing inks

Claims (6)

Patent claims: 1.Microcomputer, with a microprocessor integrated on a chip and a read-only memory, the microprocessor having an instruction register, an instruction decoder connected to it and also an instruction counter, with a switch integrated on the chip and with an external read / write memory, thereby Indicates that the changeover switch has a first switching stage in which a demultiplexer (24, 25, 26) is provided which, when a first command signal (CEP) is present, connects the output of the command counter (20) to the input of the read / write memory ( 2) connects and decouples from the input of the read-only memory (3 ') and, when a second command signal (ElP ) is present, decouples the command counter (20) from the read-write memory (2) and connects to the read-only memory (3') that the Switch has the second switching stage, in which a multiplexer (27,28,29,30) is provided which, when the first command signal (CEP) is present, the input of the command register (21) from the output of the read-only memory (3 ') and connects to the output of the read-write memory (2) and which, when the second command signal (EIP ) is present, decouples the command decoder (22) from the read-write memory (2) and the The output of the read-only memory (3 ') connects to the input of the command register (21) 2. Microcomputer according to claim 1, characterized in that one of the ./wide command signal (EIP) controllable address and transfer logic (31) is provided, by means of which at least one register of the microprocessor (3) can be connected to the user program memory (2) isL 3. Microcomputer according to claim 1 or 2, characterized in that the switching stages contain a common flip-flop (23) which is connected to a reset input (R) by the first command signal (CEP) and a set input (S) by the second command signal ( Έ / Ρ ^ is controlled, contain that the first switching stage (23, 24, 25, 26) has an input at the output (Q) of the flip-flop (23), with a further input at an output of the command counter ( 20) as well as with its output to the read-only memory (3 ') coupled AND gate (24) and another with an input via an inverter (25) to the output fQJ of the flip-flop (23), with a further input to the Output de command counter (20) and AND gate (26) coupled with an output (41) to the user program memory (2), and that the first switching stage (23,27,28,29,30) has an input 5s on the read-only memory (3 '), with a further input at the output (Q) Acs flip-flops (23) and with its output AND gate (27) coupled via an OR gate (30) to the command register (21) and another with an input via an inverter (28) to the output (Q) of the flip-flop (23), with another Input (40) to the user program memory (2) and with its output via the OR gate (30) to the command register (21) coupled AND gate (29). 4. Microcomputer according to claim 3, characterized in that the first command signal (CEP) via the command decoder (22) is coupled directly to the reset input (R) of the flip-flop (23) 5. Microcomputer according to claim 3 or 4, characterized in that an OR gate (32) is provided for coupling the second command signal (EIP) to the set input (S) of the flip-flop (23) which is used to accept the second command signal from the user program memory (2) is coupled to an input to the command decoder (22) and to an input (44) to accept an externally input command, for example from the computer-controlled device (1) 6. Microcomputer according to one of claims 1 to 5, characterized in that the user program memory (2) a memory area for storing the user program and another Memory area for storing the data from the microprocessor (3) when switching from the user program on the test program via the address and transfer logic (31) output register content of the microprocessor (3) is set