DE2806836A1 - DIGITAL GENERATOR FOR PSEUDOMERSENNE TRANSFORMATION - Google Patents

Description

Applicant: 'International Business Machines

Corporation, Armonk, N.Y. 10504

heb-pi digital generator for pseudo-Mersenne transformation

The invention relates to a novel digital generator for performing pseudo-Mersenne transformations. Until recently, the development of areas of application of digital methods in the processing of signals was through technical and economic problems narrowed · In particular, the development of real-time applications was relative slowly, because of the computing power required and, as a result, because of the size and cost of those to be used Data processing systems. The digital processing of signals can be in a large number of elementary Operations such as modulation, rectification, filtering, correlation, etc., can be divided. Among these are the Correlation and filtering, i.e. convolution operations, are in a class of their own because the associated calculations are in general are much more extensive than the calculations required for the other operations. It is by no means unusual that over 80% of the calculations that occur in digital signal processing are based on convolution operations and correlation operations omitted.

The particular importance of convolution operations and correlation operations is due to the fact that, unlike the other signal processing operations each output signal depends on a large number of input signals.

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The filter operation associated with a discrete sequence {x _n > of samples of an input signal x (t) with a filter whose impulse behavior is defined by a discrete sequence ^a _£ } can be performed by the convolution operation

being represented. In the same way, the correlation between the sequences {x „} and {a _e } is given by

N-1

It can therefore be seen that for a single sample ζ des Output signal N multiplications and N-1 additions must be carried out.

Accordingly, it is extremely important that, in order to expand the application of digital signal processing techniques the mode of action of those used to carry out convolution operations and correlation operations Circuits is improved.

It should be noted that while in general the circuits used for convolution operations have a larger Interest was seen as the correlators, since convolution operations in digital filters can be used directly, so the methods developed in connection with it are also based on correlation functions and multiplier circuits for long polynomials, i.e. can be used for long whole rational functions.

Some of the more powerful circuits for performing convolution operations make use of discrete mathematical trans * use of formations in which a convolution plays a role

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plays. Such transformations can reduce the number of operations performed in the multiplier circuits when using folding operations considerably

2
because the N multiplications for deriving N samples, such as Z _1n , are reduced to N multiplications. If the sequences {a ₀ } and {x} discrete trans-

x * η

supplied to formation generators of the type mentioned above, one obtains the sequences {A,} and {X.} (where k = 0, 1, ..., N-1)), so that the inverse transformation of the sequence of {C _k } 's, which result from the expression for expression determined products {A. . X,} gives the convolution of the original sequences

Js. · Jv

j yields {a,} and {x}. The effectiveness of circuits of this I kind, which work according to this principle, depends on the effectiveness of the generators for the direct and inverse transformations. It would therefore be desirable to use transformation generators to create a minimum of switching means for a given precision of the definition of the values A !require.

Until recently, the only discrete transformation that actually turned into one suitable for a convolution operation was Circuit was used, the discrete Fourier transform, which is defined as follows:

N-1

A. = Yes.
n = o

for k »0, 1, ..., N-1

2π
and W ^β e ^

This transformation is particularly difficult to use in circuits that use binary coded samples, so that it is generally preferred to use Mersenne or Fermat transformations where W is a power of 2

809838/059 *

is what is obviously beneficial when processing binary words.

However, these latter transformations require special ones Circuits, since the mathematical operations to be carried out must be carried out with modulo N, where N is a predetermined number.

For an easier understanding of these statements, the book "Digital Processing of Signals" by Gold and Rader is published 1969, from McGraw-Hill (see especially Chapter 7) and to an essay entitled "Discrete Convolutions via Mersenne Transforms "by Rader in IEEE Transactions on Computers, Volume C-21, No. 12, December 1972, Pages 1269 to 1273 pointed out.

The Mersenne transform follows the relationship

The brackets <<>> and (()) used here mean that the quantities in brackets are modulo q- or modulo ρ ■ »■ 2 * ^ 1-1, where q .. is a prime number and ρ - 2 ^qi -1 is an integer. However, the practical application of this transformation is limited by the fact that there is _{a close relationship between p, the number of terms a R} to which the transformation is applied, and the precision or length of the words A. For a transformation with q., Expressions the words A, consist of

ι λ

q ₁ bit. This requires that the words supplied on the input side consist of less than

7 7

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Bits exist, but each of the circuits of the transformation generator must have a capacity of q-bit. This is evident for the effectiveness of the circuit disadvantageous.

For some areas of application it can also be advantageous _{to process the words a n} bit-by-bit serial. In such a case, the circuits for a Mersenne transform generator would be even more difficult and complicated to design than with a corresponding parallel processing of data.

The object of the invention is therefore to provide a discrete transformation generator to create, which can be used in a convolution generator and which is particularly useful for generating Mersenne Transformations can be used and requires less complex circuits than before.

In particular, a generator for Pseudo-Mersenne transformations are created of the computing circuits can use that require only half the capacity that in previously known circuits of this Kind was required. The invention is now based on a preferred embodiment in connection with described in detail in the accompanying drawings.

In the drawings «

1 schematically shows a block diagram of the invention,

Fig. 2 is a block diagram of an actually implemented one constructed in accordance with the invention Circuit,

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11 Fig. 3 shows a circuit that can be used in the invention,

FIG. 4 shows an embodiment of a circuit for performing convolution operations according to FIG of the invention and

5 shows an embodiment of a circuit according to the invention useful for convolution operations.

It is known that for discrete transformations of the Mersenne type, for the property of providing an annular convolution and accordingly being usable in convolution circuits, it is not necessary that q. is a prime number. In particular one can choose q ₁ = 2q, where q is a prime number, in order to define a pseudo-Mersenne transformation so that

< ⁴ > K - (( Γ a _n . 2 <^^>)) becomes. Vy n = o

The convolution product is then, as in the usual Mersenne transformation, calculated in such a way that all operations are performed modulo (2 ^ -1), with the exception of the last one

Operation, the 2 ² ^ -1

modulo () is performed.

If the selected value of q is an odd prime number, such as

then the values A ^ can be generated by adding a Generator for Mersenne transformations A. and a generator for pseudo-Fermat transformations A. used and the respective Output signals can be combined with one another.

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- 12 -

modulo q] (5)

/ modulo (2 ^q -iA,

' J modulo 2 ■

_{a β (} _ ₂ j <nk> modulo 1 j \ ⁱ⁶ *

n »o ⁿ * / modulo (2 ^q +1))

/ / modulo 2 ■

It can be shown that for every value of k the result

1 2

press A, and A. contain the same expressions a that begin with

Λ * λ H

are multiplied by the same powers of 2. In the same

2
for A, however, the expressions a assigned to an odd power I of 2 have a minus sign.

! (7) ΒΛ - i

n = o

n = o

a _n f ₂ ^<nk> - (-2) ^<nk> ]

k = Bk ₊ Bk ^{1 and} ^ ^{= B} k- ^B k

From this we get A, - B, + B, and

Accordingly, the pseudo-Mersenne transform generator according to the invention are constructed as in Fig. 1. The Samples a are simultaneously the circuits Comp

1 9

B / and Comp Br forwarded for implementation and weighting that perform the operations according to equations (7) and (8). The circuits can be made from ordinary arithmetic circuits can be built that do not need to take the modulus into account. The invention therefore provides the dual advantage that it allows the use of simple and also readily available circuitry.

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1 2
The initial signals B. and B are then ^{added to one another in the adder stage AD1 modulo 2 q} -1 and subtracted from one another in the adder stage AD2 modulo 2 ^{g +1 and thus provide}

1 2
A ^ and Aj ₅ . These expressions are fed to the input of a circuit labeled RES, which carries out the weighted additions required for the purpose of the so-called residual operation:

* k * U ^XA k ^{+ uA} k Jj modulo (2 ^2q -1)

where λ «= (2 ^q +1) 3

^{((2q + 1))} modulo (2 ^q -1)

μ - (2 ^q -1) t-

((2 -1)) modulo (2 ^q +1)

The reduction in energy that has been achieved so far for a generator the computing power required for the transformation A. is not particularly great. However, it will have to be shown how a particularly interesting circuit can be derived from it.

If g is a primitive root of q, then it is well known that if 1 takes on all integer values from 1 to q-1 one after the other, <g> modulo q the same values, but in a different order. The order of Members of the sequence <g> are supposed to be related to the primitive roots. For example, one obtains for q-7 and g = 3

12 3 4 5 6

3 2 6 4 5 1 809838/059 *

If you set

<g ^v >
<g ^u >

and η

then, if u and ν change according to the order 1, 2, 3, 4, 5, 6, the order in which <g ^v > and <g ^u > change, namely 3, 2, 6, 4, 5, 1 to be related to the primitive roots.

1 2

One finds that A - a and A

<g ^v >
culation of the expressions a _u in a transversal filter whose coefficients are powers of 2, whose exponents are all integer values «
be determined.

- a from a Ziro

all assume integer values from 1 to q-1. Only A must for

In FIG. 2, a transformation generator is shown as an exemplary embodiment, in which q = 7 and g-3. The expressions

1 2

Α / and A. follow for k 4 O the following relations »

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4 -% " ^a 3 ² ' ^{+ a} 2 ^{20 + a} 6 ^{24 + a} 4 ² ' ⁺ - ^a 5 ^{2 + a} l ² '

4 - ^a o ^{= a} l

^a o - ^a 5

AJ -

^A 2 - ^a o

- ^a o ^{= a} 4 ^a 4 ^{2 + a} 5

2 ⁵ ₊ a, 2

a ₄ 2 ⁶ ₊ a ₅ 2 ⁴ ₊ a, 2 ⁵

2 ⁵ ₊ a, 2 ₊ a, 2 ³

^a 4 ² '- ^a 5 ² - ^a l ² '

^a 6 ²⁵ - ^a 4 ² - ³ S ² '

> ⁵ - a ₆ 2 - a ₄ 2 ³

- ^a 6 ² "

a ₅ 2 ⁴ - _{& 1} 2 ⁵ - a ₃ 2 - a ₂ 2 ³

- a ₅ 2 ⁵ - aj 2 - a ₃ 2 ³

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The Ausrücke A ₁ to A _g are supplied to the shift register SRO, from which they are transferred in a standing to the primitive roots in relationship sequence according to a further shift register SR ¹ O whose output is connected via a feedback connection with the input. The shift register SR ¹ O is provided with taps which are connected to a group of multipliers, which evaluates the expressions appearing at the taps with coefficients 2,2,2,2,2 and 2. FIG. The output signals of these multiplier stages, which evaluate the expressions coming from the taps with an even-numbered power of 2, are added to one another in a summation circuit J1, which has a further input for a. The output signals of the other multiplier stages are added up in £ 2. Accordingly, £ 1 and]? 2 yield the expressions

B ¹ and B ² ,
<g><g>

The circuit then also contains the two adder stages AD1, AD2 and the residual level RES according to FIG. 1, which then use the expressions A

<g>

delivers, ie the transformations A, for k = 3, 2, 6, 4, 5, 1. To get the desired result, it is now only necessary to arrange these transformations in their correct order and then to add A _Q that has been independently determined.

This circuit is particularly useful when processing words bit by bit serial. For this purpose a weighting is used implementing circuits are replaced by accumulators, each consisting of an adder and a register exist. As shown in FIG. 3, a single Adding stage ADD1 can be used, this adding stage

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by a group of switches SW2 with two positions for

1 2
Derivation of the expressions B, and B, is widely used.

The circuit shown in Fig. 3 also allows the simultaneous processing of two successive bits of the expressions stored in SR1.

The input IN is connected to one of the contact terminals of a switch SW1. The switching arm of the switch SW1 is at the input of a shift register SR1, the output of which is connected to the second switching contact of SW1. The register SR1 is also provided with taps which are connected to a group of changeover switches SW2, the order of which will be explained below. The switching arms of the switches SW2 are connected to the inputs of a binary adding stage ADD1 for q bits. The outputs of the adder stage ADD1 are connected to a register R1 with 2q bit positions, the outputs of which are in turn connected to a register R2, which has the same capacity as R1. On the output side, R2 is connected to one of the inputs of a switch SW3. A switch SW4 and a modulo 2 q-1 adder ADD2 are provided as the input of the transformation generator. The switch SW4 is connected to a shift register SR3, the capacity of which is one word. The parallel outputs of the bit positions of R3 are connected to one input of switch SW3. The switch SW3 has two parallel outputs which are connected to the adder ADD1 and to the register R1. On the output side, the adder stage ADD2 is connected to the input of a shift register R4, the serial output signal of which is fed to the second input of the adder stage ADD2. _{The expressions B fc} and B _k occur at the output of R2, while the expression A _{Q occurs} at the output of the accumulator (ADD2, R4).

809838/0594

The sampling values ä, which, it is assumed, in the series

ι follow a, a-,

ag, sl ^ i a, are ordered, become

j serial and bit-wise fed to the input IN, starting with the lowest value. The expression a becomes over Switches SW1 and SW4 are diverted to register R3 and do not enter shift register SR1. via switch SW1 the q-1 samples circulate in the register SR1. As already mentioned, these samples must match the previously defined Powers of 2 whose exponents are all integer values of

! 1 to q-1 can be multiplied. In the example above, these exponents range from 1 to 6. The exponents of 2 are arranged in the same order as in Fig. 2, namely 2 ² , 2 ⁶ , 2 ⁴ , 2 ⁵ , 2, 2 ³ . The weightings and accumulation operations required to generate the expressions (A.-a) can be carried out in such a way that the bits with identical weighting, which relate to the words in SR1, are output after the corresponding inputs of ADD1. It should-

however, with respect to the expressions (A, - a), the subtractions must be taken into account. This can be done in a number of ways. In this case, the

1 2
press BJ and B. developed sequentially, from which the requirement for the group of two-pole changeover switches SW2

1 2

which: are used to develop the terms B. and B ^. Accordingly, the adder ADD1 will normally only process or at most S £ bits at any one time, SW1 will consist of % ψ switches, and the registers R1 and R2 will each have q bit positions. The adder ADD1, registers R1, R2, the switches SW3, SW4 and the register R3 represent a total of a series parallel accumulator. The circuit shown in FIG refer to the ones in SR1

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Relate words that can be treated at the same time. This explains why SW2 contains q switches and why ADD1 has a capacity of q bit positions while R1 and R2 respectively have a capacity of 2q bit positions.

If the switches SW2 are toggled to their left position, then they accept bit pairs that are used to form the Expressions B, serve (left half of SR1) and if the Switch SW2 are switched to the right position, then

2 use them for the formation of the expressions B, (right half of SR1) bit pairs, with the exception of the least significant bit of the rightmost word, because this bit, because of the circulation, has already been reinserted in SR1. The words in SR1 are shifted by two bit positions at each clock time shifted, and the switches of SW2 are operated in accordance with these shifts. The ones occurring at the output of SW2 Bits are transferred to ADD1 taking into account their weighting or weighting, together with the bits of the Word stored in register R2 (via SW3). The result is a shift by one bit position to the right entered in R1 and then applied to R2. Finally, the expression a becomes the content of the after parallel conversion in R2

° 12

Adders ADD1 added. Thus B. and B. are derived one after the other, allowing the development of A ^ (for

k j * O) in an arrangement consisting of AD1, AD2, RES, similar to that in FIGS. 1 and 2, but not shown in Fig. 3 arrangement.

However, as mentioned earlier, the transformation generator according to the invention is mainly intended for to be used in a circuit arrangement for performing a convolution operation. Accordingly, the Expression for expression performed multiplications of the

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Values A ^ made by other transformations X. the Expressions X can thereby be determined according to the invention

12th

that one first derives the expressions X / and Xf.

JC JC

12 1 2

The paths followed by the expressions A /, Af, X / and XT should preferably be separated from each other. Accordingly, it would be desirable to perform the following operations

'V / modulo 2 ^g -1 ^K

) I A. ² - X. ² I

modulo 2 ^q +1

(10) f ä2. x? ) _σ -c *

^{q K}

to be carried out before the residual operation is carried out in the circuit iRES (compare FIGS. 1 and 2). A multiplier circuit, which can advantageously be used to derive the quantities C, is shown in FIG. 4. It was accepted been that the expressions {x} have already been defined

1 and that the expressions X. in memory MEM1

1 2

can be saved. The words B, and B, with respectively two g bits are added serial bit by bit in an adder ADD3 and deliver the word B ^ with (2q + 1) bit.

3 3

The bits hl of the word B £ are sequentially placed in the shift register SR2 with a capacity of g bits. If the bit bf. 2 is available at the output of the shift register SR2, then the input of SR2 i> _{i + a} niasat. · 2 "^ on. In a system working with modulo 2 ^ -1, 2 ^ = 1 _f so that the multiplication of X ^ by (b ^. 2 ¹ + bf . 2 ^{i + q} ) is reduced to

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- 21! Accordingly, the operation (9) can be simplified.

The expression provided by MEM1 X is, in a by the output signal t .. a logic AND gate A ₁ controlled shift circuit SH1 modulo 2 ^g -1 is multiplied, wherein at the input of the AND gate _A1, the signals b ^ and b. lie.

The content of SH1 is shifted when the

3 3
Bits b. and b. ₊ both are equal to 1. If at least one of these bits is 1, then the output signal t _{2 of} the OR element O _{1 is} also 1. This opens the switch JSW6, so that the content of SH1, namely j (b. + B.) X. an a 2 ^ -1 accumulator ADD4 can be applied. At each bit time, the content of this accumulator | is shifted by one bit position in the direction of the least significant position. If the 2nd bit at the output of ADD3

3 1

occurs, then the operation b "X" must be carried out.

zq κ 2

For this purpose switch SW5 is opened and if b_ = 1 then X. is added to the contents of the accumulator ADD4, controlled by SW6 and OR gate 01.

The expression C, can be used with a circuit similar to that in Fig. 4 can be determined, provided that a subtracting circuit is provided instead of the adding circuit ADD3.

So far, all of the expressions a were assumed to be positive. Where this is not the case, a constant value d = Ia _n I is added to the expressions of the sequence {a} and that

Max
Convolution product ζ that was wanted to be determined is replaced by

m ho ~ n "~ mn ~ * _ ^x mn

n = o

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• - 22 -

Γ
n = o ^x mn d = ^X o ^W m - ^z m ⁺ d ^X o ^z m - ^W m- • ^X o

is,

and

Since in this example the expression X has already been saved it is extremely easy in practice to find the expressions resulting from the convolution {a} H {x}

η η

ζ to be derived. A block diagram of a circuit suitable for this is shown in FIG. 5. At the input of the circuit, for each expression a _R, a value d - | a _n | added. The resulting expressions are fed to a pseudo-Mersenne transformation generator DT, which uses normal arithmetic logic circuits and processes words with q bits! The generator DT can be constructed, for example, as shown in FIG. 3, provided that the terms a for the feed at the input of the circuit are arranged in the order a. The expressions B. and B. supplied by the pseudo-Mersenne transform generator Dt are fed to two circuits M ₁ and M ₂ , which can both be constructed as shown in FIG. 2, however

12 12
Process Β / + BT and B. - B £. The memory labeled MEM2 is constructed similarly to the memory MEM1 in FIG

1 2

except that X. X. and X. saved at the same time

12th

will. The expressions C. and C. supplied by M ₁ and M ₀ are combined with one another in the circuit RES1 and supply

ff

xcj + pc ^

^KK " modulo

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for k = 1, 2, ..., q-1. The term C is derived from the terms X and A supplied by DT in a multiplier circuit M ₄ . The expressions C. are fed to an inverse transform generator IMT which generates the expression W. The inverse transformation generator IMT can be a generator for an inverse pseudo-Mersenne transformation of a type known per se, but which uses arithmetic circuits of the modulo 2 ^ -1 type for processing 2q bits. The pseudo-Mersenne inverse transform generator also includes a circuit that performs an operation

modulo

(2 ^2q -1)

performs. The convolution expressions ζ then finally become derived using a subtraction stage S, the input side the expression dX, derived from the multiplier circuit M- comes, and W are supplied.

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Claims (1)

PATENT CLAIMS Generator for pseudo-Mersenne transformation A _{k of} a sequence of q binary terms a, characterized in that a first and a second weighting and 1 2 Accumulator circuit (Comp B ', Comp BT) are provided which, on the input side by the elements of the sequence a controllable, on the output side the expressions B. and ß2 with <nk>. , " n = o
and ! n = o _n Γ 2 ^<nk> - (-2) ^{<nk> n} LJ provide that two adding or subtracting stages (AD1, AD2) are provided, each with their two Inputs are connected to the outputs of the weighting and accumulator circuits and the 1 2 Expressions A / and A, respectively, yield, and that finally a Summation circuit (RES) is provided, which the modulo 2 * ^ - 1 -weighted addition of the terms A, and A, too A, which delivers the pseudo-Mersenne transform. 2. Generator according to claim 1 for generating pseudo-Mersenne transformations of sequences of linear members a, characterized in that a first rotating shift register (SR ¹ O) is provided with taps for the decrease of a, in which the members a _R without the Member a can be stored in a sequence related to primitive roots, that a multiplier circuit (MULT) is also provided with two groups of multiplier stages, one group being part of the ^FR976017 809838/059 * Members (a_, a_, a,.) With even-numbered powers of 2 (2, 2, 2) and the other group the other part of the members (a ₄ , a ^ »a,) with odd-numbered powers 5 3
multiplied weighted by 2 (2, 2, 2), that two summing circuits (J, J ₂ ) are provided in which the output signals of the first group or the second group of multiplier stages are added and that finally an adding and a subtracting stage (AD1, AD2) are each connected with their two inputs to the outputs of both summing circuits (J, J_) and on the output side are connected to the summing circuit (RES) for outputting the expression A. Generator according to Claims 1 and 2 for generating pseudo-Mersenne transformations A. of a sequence of q binary terms a with n = 0, 1, 2, ..., q-1 and with an input terminal at which the expressions a are sequential are supplied, characterized in that a first shift register (SRO) for receiving the expressions a (for η φ O) is connected to this input terminal, to which a second shift register (SR ¹ O) for receiving the contents of the first shift register (SRO) when this is full, is connected in an order related to the primary roots, the second shift register being switched for a circulation of its memory contents and being provided with taps for a parallel output of the expressions a, that furthermore a multiplier circuit (MULT) for a Weighting of the expressions occurring at the taps with powers of two is provided, which can assume all integer values from 1 to q-1, that a first and a second Ad dierschaltung (J ^, J ₂ ) for a separate addition of the with even powers of 809838/059 * j two or with odd powers of two weighted expressions a are provided that a third Adding circuit (AD1) for adding the output signals the first and second adding circuit and a fourth adding circuit AD2) for subtraction the output signals of the first and second adding circuits are provided from each other and that finally a summation circuit (RES) is provided which i the expressions of the pseudo-Mersenne transform from the output signals of the third and fourth adder circuits forms. 4. Generator according to claim 1, characterized in that the weighting and accumulator circuits (Comp B, Comp B.) contain a rotating shift register (SR1, SW1) provided with taps, the one on the input side the expressions a with η from 1 to q-1 can be supplied in a sequence arranged according to primitive roots are that a serial parallel accumulator (ADD1, R1, R1, SW3) for generating the expressions a-1 i- B ¹ ■ ¹ I a Γ 2 ^< + (-; n = o ⁿ l- and -1 it is provided that a switch (SW2) is also provided, via which a number of the taps alternately and then the remaining taps can be connected to the accumulator and that finally Switching means (SW4, R3, SW3) are provided for introducing the term a into the series parallel accumulator. E ¹ R 976 017 009833/0594 2808836 5. Generator according to claim 4, characterized in that the accumulator switching means (ADD2, R4) for generating of the expression A contains,
ο 6. Generator according to claim 4, characterized in that a first register (R1) with a capacity of 2q positions at the output of the adder (ADD1) is connected, that a second register (R2) with 2q positions on the input side with the output and ausgangssei tig is connected to the input of the first register with 2q positions, that furthermore the series-parallel conversion (SW4, R3) is connected on the input side to the input of the generator and on the output side to the inputs of the adder stage and that a second accumulator (ADD2, R4) for the q Expressions a _{n is} provided. Generator for circular convolution operations of a sequence of expressions {a} with a sequence of expressions {X j using the principles of an or several of claims 1 to 4 with a generator according to claim 5 or 6, characterized in that a memory (MEM2) for storing the expressions 4 * 4 Γ ^x n Γ ^{2 <η1ς> +} <- ² >^<nk> l n ^e o · - ■ * and is provided on which circuits (MEM2, Fig. 5, 6) a first and a second multiplier circuit 111 (M1, M2) to generate the expressions C; = A /. X / and 9 2 2 Cr «AT. Xr is connected that also to this JC JC JC 9. Circuits (MEM2, Fign. 5, 6) a third multiplier circuit (M4) for generating C = A .X is connected is that further at the outputs of the first and second multiplier circuit (M1, M2) a Summation circuit (RES1) for carrying out weighted Additions is connected and that a generator (IMT) for inverse Mersenne transformations at the outputs the third multiplier circuit (M4) or the summing circuit (RES1) is connected. Generator according to Claim 7, characterized in that an adding stage (+) for adding the value d -Ia _n I to each of the expressions a before these expressions are applied to the circuit according to FIGS. 5, 6 is provided and that in a further stage (M5, S) d χ X can be subtracted from the expressions to be applied to the generator (IMT) for inverse Mersenne transformations. Generator according to claim 7 or 8, characterized in that that at least one of the first and second multiplier circuits an adder (ADD3), at whose 1 2 inputs the expressions B and B, lie, as well as a k ^K Contains shift register (SR2) connected to the output of this adder, at its input and output an AND gate (A1) and an OR gate (01) are connected that one by the output of the AND gate controlled shift circuit (SH1) on the input side with at least one of the expressions X. and X. containing memory is connected, and that an accumulator (ADD4) is connected to its input via a switch (SW6) controlled by the output signal of the OR gate to the shift circuit, and thus the terms C _fc and supplies. FR 976 017 809838/0594