GB1599584A - Pseudo mersenne transform generator - Google Patents

Description

(54) PSEUDO MERSENNE TRANSFORM GENERATOR (71) We, INTERNATIONAL BUSINESS MACHINES CORPORATION, a Corporation organized and existing under the laws of the State of New York in the United States of America, of Armonk, New York 10504, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement The invention relates to a pseudo Mersenne transforms generator.

Until recently, the development of the applications of digital techniques to the processing of signals had been hampered by technological and economic problems.

In particular the development of real-time applications had been relatively slow because of the computing power required and, consequently, of the size and cost of the processing systems involved. The digital processing of signals may be split into a large number of elementary operations such as modulation, detection, filtering, correlation, etc. The calculations associated with the correlation and filtering or convolution operations are considerably more. extensive than those involved in other operations. It is by no means unusual for over 80% of the computations associated with a digital signal processing problem to consist of convolutions or correlations.

The particular importance of the convolutions and correlations is due to the fact that, contrary to the other signal processing operations, each output sample is dependent on a large number of input signals.

The filtering process associated with a discrete sequence {xn} of samples of an input signal x(t), using a filter the impulse response of which is defined by a discrete sequence {a1J may be represented by a convolution operation:

Similarly, the correlation between sequences lx} and {a,} is given by

Thus, it is seen that, to obtain a single sample Zm of the output signal, N multiplications and N-I additions are required.

Accordingly, it is particularly important that, in order to extend the scope of the digital signal processing techniques, means be provided to increase as much as possible the effectiveness of the devices known as convolvers and correlators.

It should be noted that, although more interest has generally been taken in convolvers than in correlators because convolvers can be directly used in digital filters, the techniques developed in connection therewith are also applicable to correlators and to multipliers of long polynomials.

Some of the more efficient convolvers in existence use discrete mathematical transforms which have a so-called convolution property. Such transforms allow the number of operations carried out by the multipliers provided a convolver to be considerably reduced since the N2 multiplications required to develop N samples such as Zm are reduced to N multiplications. If the sequences (a,J and {xn} are fed to discrete transform generators of the type defined above, one obtains sequences {Ak} and {Xk} (where k=0, 1,..., N-1) such that the inverse transform of the sequence of the ICkI'S resulting from the term-by-term products {Ak . Xkl will provide the convolution of the original sequences (a, and {xn). The effectiveness of convolvers relying upon these principles depends on that of the generators of direct and inverse transforms. It would therefore be desirable to provide transform generators which, for a given precision of the definition of the Ak's, requlre a minimum of means.

Until recently, the only discrete transform which had actually been used in a convolver was the discrete Fourier transform defined as

for k=0, 1,..., NI and W=e-j 2#/N.

This transform is particularly awkard to use in devices that process binary coded samples, so that it is generally preferred to employ Mersenne or Fermat tranforms wherein W is a power of 2, which is obviously advantageous when dealing with binary words.

However, the latter transforms call for the use of special circuits because the mathematical operations they involve must be carried out modulo N, where N is a given number.

In order that the foregoing may be more readily understood, reference is made to "Digital Processing of Signals", by Gold and Rader, published by McGraw-Hill, 1969 (see particularly chapter 7), and to an article entitled "Discrete Convolutions via Mersenne Transforms", by Rader, in IEEE Transactions on Computers, Vol. C21, No. 12, December 1972, pp. 1269-1273.

The Mersenne transform obeys the relation

As used herein, the symbols > > and (()) mean that the enclosed quantities are respectively taken modulo q1 and modulo p=2qi-1, where q1 is a prime number and p=2q1-1 is an integer. However, the practical use of this transform is limited by the fact that a close relationship exists between p, the number of terms an to which the transform is applied, and the precision or length of the words Ak. For a transform of q1 terms, the words Ak will be comprised of ql bits. This requires that the input words an be comprised of fewer than (qlI) 2 bits, and yet each of the circuits of the transform generator must have a capacitor of q1 bits. Obviously, this is detrimental to the effectiveness of the device.

Also, it may be advantageous in some applications to process the words an serally by bit. In such a case, the circuits of the Mersenne transform generator would be even more complex than those required for a parallel processing of data.

According to the invention there is provided a generator of pseudo Mersenne transforms Ak of a sequence of q binary terms an including weighting and accumulation means having inputs to receive the terms an and means to generate terms Bk and B2k defined as

addition means and subtraction means having inputs connected to the outputs of said weighting and accumulation means, and means for performing weighted additions and to supply the terms Ak of the pseudo Mersenne transforms, the inputs of said means for performing weighted addition being connected to the outputs of said addition means and said subtraction means.

The invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 illustrates a generator of Pseudo Merseene transforms according to the invention; Figure 2 illustrates the generator embodying the invention: Figure 3 shows an embodiment of a circuit used in the generator according to the invention; Figure 4 illustrates an embodiment of a circuit for use in a convolver incorporating the generator of the present invention; and Figure 5 illustrates an embodiment of a convolver including the generator embodying the invention.

It is known that, in order for a discrete transform of the Mersenne family to exhibit a circular convolution property, and consequently to be usable in convolvers, it is not essential that q1 be a prime number. In the articles "Digital Filtering Using Complex Mersenne Transforms" by H. Nussbaumer, IBM Journal of Research and Development, Vol. 20, pp 498-504, September 1976 and "Digital Filtering Using Pseudo Fermat Number Transforms" by H. Nussbaumer, IEEE Transaction, Acoustics, Speech and Signal Processing, Vol. ASSP-26, pp 79-83, February 1977, pseudo Mersenne transform defined modulo (2q11), q1, composite have the circular convolution property modulo a factor p1 of (2'1l). Thus one may compute a convolution with these transforms defined modulo (2q11) provided a single final reduction modulo the factor of (2q1-1) is made on the final convolution product. It should be kept in mind that the pseudo Mersenne transforms have not the convolution modulo (22l) but modulo a factor of (229-1). In particular, one may select q1=2q with q a prime, and define a pseudo Mersenn transform such that

where the symbols < > and (()) 22q~I mean that the enclosed quantities are taken modulo q and modulo 221l respectively.

The convolution product is then calculated as in the case of a conventional Mersenne transform, with all operations being performed modulo (22ll), except for one final operation which is carried out modulo p1 with (22q~1) Pl= 3 The proof that this pseudo Mersenne transform has the convolution property modulo (22q~13, that this transform has an inverse and the computation can be carried out modulo (22q~l) with a single final.operation modulo (2-)1/3, can be found in the above mentioned articles by H. Nussbaumer.

The circular convolution property modulo (22llY3 of the pseudo Mersenne transform is defined in the above articles.

In practice, it would be inconvenient to perform all the calculations modulo (22q~1) 3 or part of the calculations modulo (2q+1) 3 A much better approach, to be described below consists in performing the calculation modulo (22q-1) or, separately modulo (2q-1) and (2q+1), and to perform once and only once a final reduction modulo (22q-1) 3 on the output samples.

We return now to the computation of the pseudo Mersenne transform defined by equation (4). In practice, we will compute this transform from its residues modulo (2q-1) and modulo (2q+1). In practice, when convolving two q-joint input sequences an and bm to produce a q-joint convolved sequence Z, defined modulo (221l), care must be exercised to ensure that there is no overflow. This may be done by scaling these sequences such that

Since for the two transforms defined modulo 2qI and 2q+1, the largest power of 2 is 21-1, all the words in the reduced transforms computed in ordinary arithmetic are of length equal to 2q. In other words, we can compute the transforms Ak and Ak defined respectively modulo (2q+1) and (2q+1) by performing all operations in ordinary arithmetic (modulo 22q) provided all exponents and indices are taken modulo q and provided we perform a single final operation modulo (2q1) and (2q+1) respectively.

A1 = an z 2 > < nk > modulo %, duo q k modulo 22q (5) modulo (2q 1) A2 = t z a . (-2) modulo ) 22q (6) n=o )2odulo (2q+1) Because of the word length limitations in the input sequence it is both possible and advantageous to perform first the computation in ordinary arithmetic (modulo 22q) with final operations modulo (2q1) and (2q+1).

It can be demonstrated that for each value of k, expressions Ak and Ak will include the same terms an multiplied by the same powers of two. However, in Ak2, the terms an associated with an odd power of two will have a minus sign.

and similarly Ak2 = Bk1 = Bk2 Accordingly, the generator of pseudo Mersenne transforms of the present invention can be designed in accordance with Figure 1. Samples an are simultaneously fed to weighting and accumulation devices COMP Bk and COMP Bk that perform operations (7) and (8). These devices can be implemented by means of ordinary arithmetic circuits (which need not take the modulo into account). Thus the invention offers the dual advantage of permitting simple and readily available circuits to be used.

The outputs of Bk and Bk are then added together modulo 2q-1 in ADI and subtracted from each other modulo 2q+1 in AD2 to provide Ak and A2. The latter terms are inputted to a device RES which carries out the weighted additions required for the purposes of the so-called residue operation:

modulo (22q-1) where (21+1) 2 -(2q-1) 2 with 1 =22q-1 modulo (22q-l) 2 where Ak is obtained by direct application of the chinese remainder theorem which can easily be verified by noting that, since 2q+1=2 modulo (2q1) and 2q-1#o modulo (2q-1) (2q+1) Ak modulo (2q-1)= Ak1=Ak1 2 and since -(2q-1)#2 modulo (21+1) and (2l+l)=o modulo (21+1) (2q-1) Ak modulo (2q+1)=- Ak2=Ak2 2 then, when i sequentially assumes all integer values from 1 to q-l, < gi > modulo q, will take on the same values, but in a different order. The order of the sequence < gi > will be said to be related to the primitive roots.

For example, for q=7 and g=3, we get

i 12 3 4 5 6 < 31 > 3 2 6 4 5 1 If we put k= < gv > and n= < gu > then, when u and v vary in the sequential order 1, 2, 3, 4, 5, 6, the order in which < gv > and < gu > will vary, namely, 3, 2, 6, 4, 5, 1, will be said to be related to the primitive roots.

We can find that the terms A < gv > 1-ao and A < gv > 2-ao result from circulations of the terms a < gu > in a transversal filter whose coefficients are powers of two the exponents of which assume all integer values from 1 to q-l. Only Ao must be determined separately.

As shown in Figure 2, a transform generator in which q=7 and g=3 has been chosen by way of example. The terms Ak and Ak2 for k+0, obey the following relations: A31-a0=a322+a226+a624+a425+a52+a123 A21-a0=a122+a326+a224+a625+a42+a523 A61-a0=a522+a126+a324+a225+a62+a423 A41-a0-a422+a526+a124+a325+a22+a623 A51-a0=a622+a426+aS24+a125+a32+a223 A11-a0=a222+a626+a424+a525+a12+a323 A32-a0-a322+a226+a624-a425-a52-a123 A22-a0=a1 22 + a326 fa224-a625-a42-a523 A26ao=a522+ a,26 + a,24-a,25-a,2-a,23 A42-a0=a422+a526+a124-a325-a22-a623 A:-a,=a,22+a,26fa,24-a,25-a,2-a,23 A52-a0=a622+a426+a524-a125-a32-a223 A12-a0=a222+a626+a424-a525-a12-a323 The terms a, to a6 are fed to a shift register SR0 from which they are sent, in an order related to the primitive roots, to another shift register SR'0, the output of which is fed back to its input. Register SR'0 is provided with taps connected to a set of multipliers which weight the terms available on the taps with coefficients 22, 26, 24, 25, 2 and 23. The outputs of those multipliers which weight the terms received from the taps with even powers of 2 are added together in 1 (which has an additional input for aO). The outputs of the other multipliers are added up in #2.

Accordingly, 1 and #2 respectively provide the terms B < gV > 1 and B < 26v > .

The remainder of the device comprises circuits ADI, AD2 and RES which are similar to corresponding circuits of Figure 1. Circuit RES supplies the terms A < gv > that is, the transforms Ak for k=3, 2 6, 4, 5, 1. All that is required to obtain the desired result is to rearrange these transforms in a sequential order and to add thereto A0 which has been determined separately.

This type of circuit is particularly useful when processing words serially by bit.

To this end, the weighting means are replaced by accumulators consisting each of an adder and a register. As shown in Figure 3, a single adder (ADD I ) may in fact be used, this adder being multiplexed by means of a set SW2 of two-position switches to develop the terms Bk and B2k. The device illustrated in Figure 3 is also designed to enable two consecutive bits of the terms contained in SRI to be simultaneously processed.

Input IN is connected to one of the contact studs of a two-position switch SWI. The mowing arm of SW1 is connected to the input of a shift register SRI the output of which is connected to the second contact stud of SWI. Register SRI is also provided with taps connected to the set SW2 of two-position switches, in an order to be specified later. The moving arms of the SW2 switches are connected to the inputs of a q-bit binary adder ADD 1. The outputs of ADD 1 are connected to a register RI which has 2q bit positions the outputs of which are in turn connected to a register R2 that has the same capacity as R1. The output of R2 is connected to one of the inputs of a switch SW3. A switch SW4 and a modulo 224~1 adder ADD2 are provided at the input of the transform generator. Switch SW4 is connected to a shift register R3 having a capacity of one word. The parallel outputs of the bit positions of R3 are connected to an input of switch SW3. Switch SW3 has two parallel outputs which are respectively connected to ADDI and RI. The output of ADD2 is connected to the input of a shift register R4 the serial output of which is fed back to the second input of ADD2. The terms Bk and Bk are obtained at the output of R2 while the term Ao is available at the output of the accumulator (ADD2, R4).

The samples an, which will be assumed to be arranged in the order aO, a1, aS, a4, a6 a2, a,, are applied to input IN serially by bit, beginning with the least significant weight. The term a0 is diverted toward R3 and R4 by means of switches SWI and SW4 and does not enter SRI. Register R3 deserializes aO. The q-l samples in register SRI will circulate therein through SWI. As previously mentioned, these samples must be multiplied by previously defined powers of two the exponents of which assume all integer values from I to q-l. In the above example, these run from 1 to 6. The powers of two are arranged in the same order as that shown in Figure 2, namely, 22, 26, 24, 25, 2, 23. The weighting operations and the accumulations required to generate the terms (A1-ac) can be carried out by feeding the bits of identical weight pertaining to the words contained in SRI to the appropriate inputs of ADDI. However, having regard to the terms (A2kaO), the subtractions should be taken into account. This can be done in a number of ways.

In this instance, we chose to develop the terms Bk and Bk sequentially, hence the need for the set SW2 of two-position switches, which positions are respectively used to develop the terms Bk and the terms Bk. Accordingly, adder ADD1 will normally process a maximum of q-l 2 bits at a time, SW2 will comprise q-l 2 switches, and registers Rl and R2 will have q bit positions each. The composite of ADDI, Rl, R2, SW3, SW4 and R3 constitutes a serial-parallel accumulation means. In fact, the device illustrated in Figure 3 is designed to enable an accelerated process in which consecutive couples of bits pertaining to each of the words contained in SRI are dealt with simultaneously. This explains why SW2 comprises q switches and why ADD 1 has a capacity of q bit positions, whereas Rl and R2 have a capacity of 2q bit positions each.

When the SW2 switches are set to the left-hand position, they receive the couples of bits serving to form the terms Bk (left half of SRI), and when set to the right-hand position, they receive the couples of bits making up the terms Bk (righthand half of SRI), except for the least significant bit of the rightmost word, which bit, because of the recirculation, has already been reinserted into SRI). The words within SRI are shifted two bit positions at a time and the switches of SW2 are actuated in accordance with these shifts. The bits outputted from SW2 are fed to ADD 1, taking their weights into account, together with the bits of the word stored in register R2 (through SW3). The result is inputted to RI with a one-bit position shift to the right and is then applied to R2. Lastly, the term a0 deserialized in R3 is added to the contents of adder ADDI. Thus, Bland Bk are consecutively obtained and will permit developing Ak (for k5t0) in an arrangement (comprised of ADI, AD2, RES) similar to that of Figures 1 and 2 (not shown in Figure 3).

However, as previously mentioned, the transform generator of the present invention is mainly designed to be incorporated in a convolver. Consequently, term-by-term multiplications of the Ak'S by other transforms Xk are performed therein. The terms Xk can be determined, in accordance with the invention, by first determining the terms Xk and Xk.

The paths followed by the terms Ak, Ak, Xk and X2k should preferably be kept separate. Accordingly, it would be desirable to perform the operations

t9) (AkI X1 ) = Ckl modulo 2q-1 (10) Ak2 Xk2 ) = Ck modulo 2q+1 before the residue operation carried out in device RES (see Figures I and 2).

A multiplier capable of developing the Ck1's advantageously is shown in Figure 4. It has been assumed here that the set of terms (x,J had previously been defined and that the terms Xk1 could be stored in MEM 1. The words Bk1 and Bk2 of 2q bits each are added serially by bit in an adder ADD3 to provide a word Bk3 of (2 q+l) bits.

The bits b3 of the word Bk3 are introduced sequentially in a shift register SR2 having a capacity of q bits. When the bit b3i. 2i is available at the output of SR2, the inDut thereof receives bi+n3 . 2i+q. In a modulo 2q-1 system, 2q=1 (the symbol means congruent to), so that the multiplication of Xk1 by (bi3 . 2i+b3i+q .21+1) reduces to Xki (b3+b3+1)21.

Accordingly, operation (9) can be simplified.

The term Xk1 supplied by MEM 1 is multiplied modulo 2qI in a shifting circuit SH1 controlled by the output t, of an AND logic circuit At the inputs of which receive bi3 and b3 A shift of the contents of SH 1 takes place when the bits b3 and b3i+q are both equal to 1. If at least one of these bits is equal to 1, the output t2 of OR circuit O1 is also equal to 1. This causes switch SW6 to open to thereby allow the contents of SHI, namely (bi3+bi3+q)Xk1, to be applied to a modulo 2q-1 accumulator ADD4. The contents of this accumulator are shifted one bit position to the least significant positions at every bit time. When the 2qth bit appears at the output of ADD3, the operation b2qXk must be carried out. To this end, switch SW5 is opened, and if b321=l, then Xk1 is added to the contents of accumulator ADD4 under control of SW6 and OR Oi.

The term Ck2 can be determined by means of a circuit similar to that of Figure 4, provided that a subtractor is substituted for ADD3.

In the foregoing, all terms an have been assumed to be positive. Where such is not the case, a constant value d=lanlMax is added to the terms of the sequence {an}, and the convolution product Zm it was desired to determine is replaced by Since

Wm=zm+d X0 (11) zm=Wm-d . X0.

Since the term X0 has, in this example, previously been stored, it will be extremely simple, in practice, to obtain the terms Zm resulting from the convolution {an}X{xn}. A block diagram of such a convolver is shown in Figure 5. A value d=!anlMax is added to each term an at the input of the device. The resultant terms are fed to a pseudo Mersenne transform generator DT that uses ordinary arithmetic circuits and processes words of q bits. Generator DT may take the form of the device of Figure 3, provided the terms an are rearranged to be applied to the input of the device in the order a < gw > . The terms Bk1 and Bk supplied by DT are fed to a couple of devices M, and M2 which may be of the type shown in Figure 4 but process Bk+Bk and BkBk, respectively. The device designated MEM2 is a memory similar to MEMI of Figure 4, except that it stores Xo, Xk and Xk simultaneously. The terms C' and Ck2 respectively supplied by Ml and M2 are combined in RESI to provide

Ck = gS Ck + U ))odu1o 229,1 modulo 22q-1 fork=l, 2....,q-l. The term CO is developed in a multiplier M4 from the terms0 and Ao provided by DT. The terms Ck are fed to an inverse transform generator IMT which generates Wren. Device IMT may be a generator of inverse pseudo Mersenne transforms which uses modulo 22q~I arithmetic circuits processing words of 2q bits. The generator of pseudo inverse Mersenne transforms also includes a circuit performing a (22q-1) modulo operation.

3 Lastly, the convolution terms Zm will be obtained using a subtractors the inputs of which receive dXo, as supplied by a multiplier M5, and Wren.

WHAT WE CLAIM IS: 1. A generator of pseudo Mersenne transforms Ak of a sequence of q binary terms an including weighting and accumulation means having inputs to receive the terms an and means to generate terms Bk and Bk defined as

addition means and subtraction means having inputs connected to the outputs of said weighting and accumulation means, and means for performing weighted additions and to supply the terms Ak of the pseudo Mersenne transforms, the inputs of said means for performing weighted addition being connected to the outputs of said addition means and said subtraction means.

2. A generator according to Claim 1, in which the weighting and accumulation means includes shifting and recirculation means wherein the terms an, excluding the term aO, are initially loaded in an order related to the primitive roots, means for extracting said terms an, first weighting means for weighting a portion of said extracted terms with even powers of two, and second weighting means for weighting the remainder of said extracted terms with odd powers of two, said addition means includes first addition means for adding together the outputs of said first weighting means and adding a0 thereto, second addition means for adding together the outputs of said second weighting means and third addition means for adding together the outp

Claims (11)

**WARNING** start of CLMS field may overlap end of DESC **. of devices M, and M2 which may be of the type shown in Figure 4 but process Bk+Bk and BkBk, respectively. The device designated MEM2 is a memory similar to MEMI of Figure 4, except that it stores Xo, Xk and Xk simultaneously. The terms C' and Ck2 respectively supplied by Ml and M2 are combined in RESI to provide Ck = gS Ck + U ))odu1o 229,1 modulo 22q-1 fork=l, 2....,q-l. The term CO is developed in a multiplier M4 from the terms0 and Ao provided by DT. The terms Ck are fed to an inverse transform generator IMT which generates Wren. Device IMT may be a generator of inverse pseudo Mersenne transforms which uses modulo 22q~I arithmetic circuits processing words of 2q bits. The generator of pseudo inverse Mersenne transforms also includes a circuit performing a (22q-1) modulo operation. 3 Lastly, the convolution terms Zm will be obtained using a subtractors the inputs of which receive dXo, as supplied by a multiplier M5, and Wren. WHAT WE CLAIM IS:

1. A generator of pseudo Mersenne transforms Ak of a sequence of q binary terms an including weighting and accumulation means having inputs to receive the terms an and means to generate terms Bk and Bk defined as

addition means and subtraction means having inputs connected to the outputs of said weighting and accumulation means, and means for performing weighted additions and to supply the terms Ak of the pseudo Mersenne transforms, the inputs of said means for performing weighted addition being connected to the outputs of said addition means and said subtraction means.

2. A generator according to Claim 1, in which the weighting and accumulation means includes shifting and recirculation means wherein the terms an, excluding the term aO, are initially loaded in an order related to the primitive roots, means for extracting said terms an, first weighting means for weighting a portion of said extracted terms with even powers of two, and second weighting means for weighting the remainder of said extracted terms with odd powers of two, said addition means includes first addition means for adding together the outputs of said first weighting means and adding a0 thereto, second addition means for adding together the outputs of said second weighting means and third addition means for adding together the outputs of said first and second addition means and said subtraction means including means for subtracting from each other the outputs of said first and second addition means.

3. A generator according to Claim 1, in which the weighting and accumulation means includes a first shift register having an input to receive the terms an (for a a second shift register which receives the contents of said first register, when

the latter is full, in an order related to the primitive roots, said second register being provided with means for recirculating its contents and with taps to supply the terms an in parallel, and means for weighting the terms provided on said taps with powers of two the exponents of which assume all integer values from I to q- I, said addition means includes first and second addition means for separately adding the terms weighted with even powers of two and those weighted with odd powers of two and third addition means for adding together the outputs of said first and second addition means and said subtraction means including means for subtracting from each other the outputs of said first and second addition means.

4. A generator according to Claim 1, in which said weighting and accumulation means includes a shift register provided with recirculation means and with taps, and to the input of which are applied the terms an (with n varying from I to qI) in an order related to the primitive roots, serial-parallel accumulation means for generating the terms

means for alternatively connecting a number of said taps, then the remainder thereof, to the input of said accumulation means, and means for introducing the term a0 into said serial-parallel accumulation means.

5. A generator according to Claim 4, further including accumulation means for generating the term A,.

6. A generator according to Claim I, in which said weighting and accumulation means includes a first shift register provided with recirculation means and taps, and having an input to which are applied the terms an (with n varying from 1 to q-l) in an order related to the primitive roots, first serial-parallel accumulation means comprising a set of two-position switches connected to said first shift register, an adder, the inputs of which are connected either to a number of said taps or to the remainder thereof through said set of switches, a first register with a capacity of 2q positions and having inputs which are connected to the outputs of said adder, a second register with a capacity of 2q positions and having inputs and outputs which are respectively connected to the outputs and to the inputs of said first register having a capacity of 2q positions and a deserializer circuit having an input connected to the input of the generator and outputs connected to the inputs of said adder.

7. A generator of circular convolutions of a sequence of terms {ant by a sequence of terms {xn} including the generator claimed in Claim 5 or 6, a memory storing the terms

first and second multiplication means connected to said memory and to said generator according to Claim 5 or 6 for generating the terms Ck1=Ak1. Xk and C2k=Ak2 . X2k, third multiplication means connected to said memory and to said generator for generating C0=A0 . X0, means for performing weighted additions, the inputs of which are connected to the outputs of said first and second multiplication means, and a generator of inverse pseudo Mersenne transforms having an input connected to the output of said third multiplication means and to said means for performing weighted additions.

8. A generator of circular convolutions according to Claim 7, including means for adding a value d=lanlMax to each of the terms an before each such term is fed to said generator and means for subtracting d . XO from each of the terms supplied by said generator of inverse pseudo Mersenne transforms.

9. A generator of circular convolutions according to Claim 7 or 8, in which at least one of said first and second multiplication means includes an adder, the inputs of which receive the terms Bx and B2k, a shift register, the input of which is connected to the output of said adder, an AND logic circuit and an OR circuit, both of which are connected to the input and to the output of said shift register, a shifting circuit controlled by the output of said AND circuit and the input of which is connected to the memory storing at least one of terms X' and X2, and an accumulator the input of which is connected to said shifting circuit through a switch that is controlled in turn by the output of said OR circuit, said accumular supplying the terms Ck and C2k.

10. A pseudo Mersenne transforms generator substantially as hereinbefore described with reference to the accompanying drawings.

11. A generator of circular convolutions substantially as hereinbefore described with reference to Figures 4 and 5 of the accompanying drawings.