DE2803639B2 - Analog-digital encoding for passive transducers with direct current supply - Google Patents

Description

The invention relates to an analog-digital encryptor for passive measuring transducers with a common DC supply voltage for measuring transducers and a reference voltage source and with an integration device and a polarity reversing switch alternately applied by the output signal of the measuring transducer or the reference voltage source with the aid of an integration time or voltage-controlled changeover switch for the supply voltage of the transducer and a preamplifier for the output signal of the transducer.

Such an analog-digital encryptor is described in DE 24 50 111. This well-known analog-digital encoder is intended to compensate for thermoelectric voltages in the measuring circuit as well as the influence of zero point fluctuations in the preamplifier. However, thermoelectric and contact voltages also occur in the reference voltage circuit. The known analog-digital encryptor does not contain any measures to eliminate these error voltages or to compensate for their effect.

The invention was based on the object of specifying an analog-digital encryptor in which measures are also taken to render the contact or thermal voltages in the reference voltage circuit ineffective.

In the case of an analog-digital encryptor, as described at the beginning, this object is achieved by the combination of the characterizing features listed in claim 1.

When considering the mode of operation of the invention, it will be demonstrated later that the objectives set at the beginning have been achieved. In addition, the present encryptor also retains the advantages of the known double integration encryptors, namely the independence of long-term fluctuations in the clock pulse frequency, which are maintained independently of long-term fluctuations in the specific elements of the integration device and the independence of long-term drifts in the switching level of a threshold switch.

In the present analog-digital encryptor, a Schmitt trigger is expediently connected downstream of the integration device, the two mutually inverse outputs of which are connected to two inputs of an OR gate via delay elements. The exit of the OR gate is connected to an input of an AND gate, the other input of which is connected to the output of a clock pulse generator and the output of which is connected to the counting input of a first counter and a second AND gate to the counting input of a second counter. A carry output of the first counter is connected to an input of a flip-flop, the other input of which, as well as a reset input of the first counter, is connected to the output of the OR gate via an inversion element. The output of the flip-flip is connected to the second input of the second AND gate and a control input of the switch. The inverting output of the Schmitt trigger is connected to a control input of the polarity reversal switch and an acceptance input of a buffer for the content of the second counter, as well as a reset input of the second counter.

A Miller integrator is advantageously used as the integration device.

A digital display is expediently connected to the output of the buffer.

The polarity reversal switch consists of four field effect transistors, which are controlled in pairs by mutually inverse outputs of the Schmitt trigger.

The switch consists of four field effect transistors, which are controlled in pairs by mutually inverse outputs of the flip-flop.

Two delay elements in front of the two inputs of the OR element delay signals that jump from "0" to "L". Signals that jump from "L" to "0", on the other hand, are not delayed.

The invention is explained with the aid of four figures.

Fig. 1 shows an embodiment of the invention as a basic circuit diagram;

in Fig. 2 the same embodiment is shown in more detail;

FIG. 3 shows a voltage timing diagram together with signal diagrams of signals present at various points in the circuit;

4 shows, as a basic circuit diagram, the interconnection of a passive measuring transducer with the main parts of a known double integration cipher.

In FIG. 1, a DMS bridge circuit composed of strain gauges is connected to a polarity reversal switch S [deep] 1 via lines L [deep] 1 and L [deep] 2. The movable contacts of the pole reversal switch are connected to a voltage supply that emits a direct voltage u´ [low] s. A voltage divider circuit consisting of a resistor R [deep] N and two resistors 1/2 R [deep] v is located parallel to the supply diagonal of the DMS bridge circuit. The voltage drops +/- u [low] s on the feed diagonal of the DMS bridge circuit. The two connection points of the measuring diagonals of the DMS bridge circuit are connected to fixed contacts of a changeover switch S [deep] 2 via lines L [deep] 3 and L [deep] 4. A generator is inserted in the train of the line L [deep] 3, which is intended as a substitute source for the resulting thermal voltage u [deep] t occurring in the measuring circuit due to interference. The voltage on the measuring diagonal is marked with +/- u [deep] m, the voltage between the conductors L [deep] 3 and L [deep] 4 after the thermal voltage generator is +/- u [deep] m + u [deep] t. Two other fixed contacts of the changeover switch S [deep] 2 are connected via lines L [deep] 5 and L [deep] 6 to the resistor R [deep] N, at which a reference voltage +/- u [deep] N drops. In the train of the line L [deep] 5 another generator is inserted, in which another disturbance-related thermal voltage u [deep] small theta is generated. A voltage of +/- u [low] N + u [low] small theta is then applied to the two contacts of the changeover switch S [low] 2 occupied by the lines L [low] 5 and L [low] 6. The moving contacts of the switch S [low] 2 are connected to the two inputs of a preamplifier V [low] 1, the gain factor of which is v. In the non-earthed supply line from the changeover switch S [low] 2 to the amplifier V [low] 1, another generator is thought to be located, which generates a zero point drift voltage u [low] o of the amplifier V [low] 1 caused by interference. The voltage u [low] A can be taken from the output of the amplifier V [low] 1. This output is via a switch S [low] 3 and a resistor R with one input of an amplifier V [low] 2 designed as a Miller integrator tied together. The second input of the amplifier V [low] 2 is expediently connected to ground. The output terminal of the amplifier V [low] 2 is connected to the first-mentioned input via an integration capacitor C [low] 1. An integration voltage u [low] i is then applied to the output terminal of the amplifier V [low] 2. The same output terminal is also connected to an input of a Schmitt trigger ST, which has two outputs. A signal A, which can be taken from one output, is applied via a delay element V [low] z1 with the delay time small Tau [low] 1 to an input of an OR gate OR. A signal B, which can be taken from the other output of the Schmitt trigger ST, is present via a delay element V [low] z2 with the delay time small Tau [low] 2 at the other input of the OR gate OR. The same output signal controls the polarity reversal switch S [low] 1. The output of the OR gate OR is connected to an input of an AND gate U [low] 1, the other input of which is connected to the output of a clock generator TG, which emits a pulse voltage u [low] z at the frequency f [low] o is. The output of the AND gate is at the counting input of a first counter Z [low] 1, the highest possible counter content of which is N. A carry output of the counter Z [low] 1, which carries the signal U, is connected to an input of a flip-flop FF, the other input of which is connected to the output of an inversion element NOR. The input of this gate is at the output of the OR gate OR. A signal C that can be taken from this output controls the switch S [low] 3. A signal C [with overline] can be taken from the output of the inversion element NOR, which also applies to a reset input of the counter Z [low] 1. An output of the flip-flop FF, from which a signal D originates, which is used to control the switch S [low] 2, is connected to an input of a second AND gate U [low] 2. The second input of this AND gate is connected to the output of the first AND gate U [low] 1. The output of the AND gate U [low] 2 is at the counting input of a second counter Z [low] 2, which is designed to receive a number of pulses n. Bit outputs of the counter Z [low] 2 are connected to a numeric display ZA via a buffer memory S. A transfer input of the buffer S and a reset input of the counter Z [low] 2 are acted upon by one output signal B of the Schmitt trigger ST.

In the figure 2, the embodiment of the invention according to Figure 1 is shown in detail. In particular, the switches S [deep] 1, S [deep] 2 and S [deep] 3 are no longer shown as mechanical switches, but rather designed as electronic switches. The other details, which correspond to FIG. 1, are provided with the same reference symbols. In the lines L [low] 1 to L [low] 6 of FIG. 1, line resistances R [low] L1 to R [low] L6 are shown in FIG. The polarity switch S [low] 1 consists of two transistor pairs T [low] 1, T [low] 2 or T [low] 3 and T [low] 4. The first pair is controlled by signal A, which is present at an output of the

Schmitt trigger ST occurs. The second pair of switching transistors T [low] 3 and T [low] 4 is controlled by signal B, which is taken from the other output of the Schmitt trigger. The signal B also controls the transfer of the counter contents of the counter Z [low] 2 to the buffer memory S and the resetting of the counter Z [low] 2. According to FIG. 2, the changeover switch S [low] 2 comprises two transistor pairs T [low] 5, T [low] 6 or T [low] 7 and T [low] 8. The first-mentioned pair is controlled by a signal D which occurs at an output of the flip-flop FF. The second pair T [low] 7, T [low] 8 is controlled by a signal D [with overline] originating from the other output of the flip-flop FF. The delay elements V [deep] z1 and V [deep] z2 are designed so that they are at the transition from log. Delay "0" to "L" while the transition from "L" to log. "0" is transmitted without delay.

FIG. 3 shows a voltage-time diagram which shows the course of the integration voltage u [low] i during a complete measurement cycle. The meaning of times t [low] 0 to t [low] 6, which are entered in the diagram, emerge from the description of effects that follows later. The switching threshold u [deep] ST of the Schmitt-Tiggers ST is parallel to the abscissa. Delay times small Tau [deep] 1 and small Tau [deep] 2 are in the delay elements V [deep] z1 and V [deep] z2 of the figures 1 and 2 generated. Time segments n times T [low] o correspond to the highest possible counter content of the counter Z [low] 1, multiplied by the period duration T [low] o of the counting pulse frequency arising from the generator G. n [deep] 1 and n [deep] 2 is the number of pulse counts that accumulate during the corresponding integration times. The maximum values of the integration voltage, each measured from the switching threshold u [low] ST of the Schmitt trigger ST, are denoted by a large delta u [low] iI and a large delta u [low] iII.

The switching times of the switching transistors T [low] 1 to T [low] 9 of FIG. 2, which correspond to the diagram, are drawn in below the voltage diagram in five lines. They correspond to the control signals A to E of the switching transistors.

In the following sections, the mode of operation of the circuits according to FIGS. 1 and 2 is explained in connection with the voltage-time diagram of FIG.

The DMS bridge circuit is fed with the DC voltage u '[low] s via the pair of conductors L [deep] 1, L [deep] 2 and the polarity reversal switch S [deep] 1. The polarity of the supply voltage applied to the supply diagonal of the DMS bridge circuit, reduced by the voltage drops on the supply lines L [low] 1 and L [low] 2 and the switch sections of the polarity switch S [low] 1 compared to the voltage u´ [low] 2s / - u [low] s can be changed periodically - controlled by the polarity reversal switch S [low] 1. This causes a measurement voltage to drop on the output side of the DMS bridge circuit

+/- u [deep] m = V times (+/- u [deep] s)

where V is the measurement-proportional detuning of the bridge circuit. The reference voltage drops at the terminals of the normal resistor R [low] N within the voltage divider consisting of 1/2 R [low] V - R [low] N - 1/2 R [low] V at. Both voltages change their polarity in the same cycle as u [low] s and after a settling time small Tau [low] µ both are strictly proportional to the amplitude of u [low] s. These output voltages are superimposed for a short time with constant sign, unaffected by the polarity change of u [deep] s, but long-term according to sign and magnitude but irregularly drifting thermal voltages, which would incorrectly influence the measurement result if a direct voltage supply were used. These interference voltages are summarized in the measuring circuit in the interference voltage u [low] t and in the reference voltage circuit in the interference voltage u [low] small theta.

The voltages subject to interference voltages +/- u [deep] m + u [deep] t and +/- u [deep] N + u [deep] small theta reach the clock-controlled switch S [deep] 2 alternately as u [deep] E to the input of the DC voltage amplifier V [low] 1 with the gain factor v; u [low] E is amplified by this to the output voltage u [low] A. In practice, this output voltage is unfortunately not a true representation of u [low] E, but it contains a level-independent, short-term constant, long-term but irregularly drifting zero component, the size of which is converted to the input side as an interference voltage value u [low] o can be represented. This applies to

(1)

u [low] A reaches the input of the Miller integrator via a clock-controlled switch S [low] 3 and is integrated into an integral voltage at its storage capacitor C [low] 1

(2)

to lead. The following Schmitt trigger ST with its as sharply defined, briefly stable switching threshold u [low] ST constantly decides whether the level of u [low] i is above or below u [low] ST and forms this in the conjugate switching states A. and A [with top line] = B from, whose switching times from 0 to L are delayed by the delay elements V [deep] 1 and V [deep] 2 by small Tau [deep] 1 or small Tau [deep] 2, and whose switchover points from L to 0 reach the OR element OR without delay and form signal C there.

L signal on C closes switch S [low] 3 and opens gate U [low] 1 at time t [low] 1 (Figure 3), and the counting pulses from alternating voltage generator G (free-running oscillator) with the briefly stable frequency f [low] o reach the counter Z [low] 1 with the counter content N, which was previously set to zero (by a c [with top line] pulse).

The first integration phase of the amplifier input voltage then follows for the time T = N times T [low] o = N / f [low] o

(3)

After amplification by amplifier V [low] 1, this becomes the output voltage

(4)

Over the 1st integration time from t [low] 1 to t [low] 2 = t [low] 1 + N times T [low] o, the voltage u [low] i at the output of the Miller integrator changes by the amount

(5)

When the counter content N is exceeded, the counter Z [low] 1 emits a transmission pulse ü, the FF into the opposite switch position and outputting one

Signal D brings, the switch S [low] 2 flips over and the voltage

(6)

with brings to the amplifier input. This is followed by the second integration phase over the time t [deep] 3 - t [deep] 2 = t [deep] 3 - n [deep] 1 times T [deep] o, which the Miller integrator needs to convert the values from u [ low] E1 to reverse the change caused by the large delta u [low] iI of u [low] i, ie to return u [low] i to the switching threshold u [low] ST of the Schmitt trigger. The following applies here

(7)

with

(8th)

During the second integration phase from t [low] 2 to t [low] 2 + n [low] 1 T [low] o, D also opens AND gate U [low] 2 and enters counter Z [low] 2 the number of n [low] 1 counting pulses from G occurring during this time. n [deep] 1 is calculated from the equality of

(9)

from (5) and (7) to

(10)

At time t [low] 3, switching over the Schmitt trigger ST generates signal B, which switches the polarity reversal switch S [low] 1 and thus reverses the polarity of u [low] s. The disappearance of A = B [with top line] arrives at OR without delay through V [low] 2 and lets C return to switching state 0. C is inverted from NOR to C [with top line], which signal sets the counter Z [low] 1 to zero and returns FF to its basic position. Signal C blocks the AND gate U [low] 1 and prevents further counting pulses from reaching Z [low] 1 and Z [low] 2 until after the delay time has elapsed small Tau [low] 2 via OR at time t [low ] 4 signal C is again logically L and the third integration phase from t [low] 4 to t [low] 4 + n times T [low] o is carried out, in which the switch S [low] 3 is closed again by signal C and because of the polarity reversal of u [deep] s now the voltage

(11)

to the input of the preamplifier V [low] 1.

She is amplifying too

(12)

and at the end of the third integration phase leads to a change in large delta u [deep] i3 = large delta u [deep] iII

(13)

The carry pulse ü of the counter Z [low] 1 switches the flip-flop FF again and forms the signal D, which toggles the switch S [low] 2 and further counting pulses via the gate U [low] 2 into the counter Z [low ] 2 can get. This initiates the fourth integration phase from t [deep] 5 to t [deep] 5 + n [deep] 2 times T [deep] o, during which the voltage

(14)

at the input of the amplifier V [low] 1 and from this on

(15)

is reinforced.

u [low] A4, through the integration in the Schmitt trigger ST, leads its output voltage u [low] i4 back to the switching threshold u [low] ST and thus makes the voltage change large delta u [low] i3 = + large delta u [low ] iII = - large delta u [deep] i4 undo

(16)

The number of counter pulses n [deep] 2 resulting from the equality of large delta u [deep] i3 = - large delta u [deep] i4 (from (13)! = (16))

(17)

is also counted into the counter Z [low] 2 during the fourth integration phase, which is therefore at time t [low] 6 = t [low] 5 + n [low] 2 T [low] o after the Schmitt trigger ST the counter contents in its excited switch position

(18)

from (10) + (17). (18) can be transformed:

(19)

If the maximum usable detuning V [low] max of the DMS bridge circuit is dimensioned in such a way that it fully utilizes the counter content n of Z [low] 2, the determining equation is obtained with (19)

(20)

which can be simplified by neglecting the error terms

(21)

from which one finds the dimensioning for k

(22)

With (22) can be replaced by inserting into (19) taking into account the relationships

(23)

Calculate the remaining influence of the interference voltages on the measurement result when the invention is applied:

(24)

With (24) a sensitivity error (relative error!)

(25)

and then a relative zero point error related to the modulation value of

(26)

determine.

The errors according to equations (25) and (26) are to be compared in the following with corresponding errors that have to be accepted in a circuit with the known double integration. Such a circuit is shown with its essential parts in FIG. On the input side, the circuit largely corresponds to the circuit according to FIG. 1. An important difference, however, is that no polarity reversal switch is provided for the supply voltage of the bridge circuit DMS and the voltage divider for generating the reference voltage. In this usual circuit there is only the switch S [low] 2, which is located in front of the Miller integrator and whose input switches alternately to the outputs of the preamplifier V [low] 1 and the voltage divider for the reference voltage u [low] N. With the voltages entered in FIG. 4, taking into account the interference voltages, the count result after the second integration step is obtained

(27)

If the maximum value of the counter result of the second integration step with maximum detuning V [low] max of the DMS bridge circuit (cf. see (21) (28)

so that see (22) (29)

is to be dimensioned.

With (23) one then finds for the numerical value n [deep] 1 via (27): see (24) (30)

The sensitivity error is calculated from this see (25) (31)

and the zero point error see (26) (32)

According to (30), changes in the gain v are included in the encryption result in a directly proportional manner. While according to (31) thermal voltages u [deep] small theta in the comparison voltage circuit are inversely proportional to the gain v, reduced in sensitivity errors, additionally reduced by the factor n / N, both the thermal voltages u [deep] t in the measuring circuit as well as the zero point errors of the Amplifier with its full weight in comparison with the maximum measuring voltage u [deep] m [deep] max in the measurement result.

A rough calculation with practical values shows the consequences of this are required

(33)

If this method is to be used within the scope of legal-for-trade weighing systems, both the thermal voltages of the complete measuring circuit installation u [deep] t <0.5 µV and the drift voltages u [deep] o of the measuring amplifier V [deep] 1 with u [deep] o <0.5 µV can be kept at a level that can only be achieved today with very complex measuring amplifiers based on the chopper principle. In addition, changes in the gain factor v are fully integrated into proportional changes in the sensitivity of the measuring circuit, as can be seen directly from (27),

(34)

which is why the long-term stability of the measuring amplifier amplification must be kept at least to values <10 [high] -4.

If one compares this with the errors of the measuring arrangement according to the invention, thermal voltages u [deep] small theta in the reference voltage circuit and the amplifier drift voltage u [deep] o compared to the maximum measurement voltage u [deep] m [deep] max only deal with the square of theirs the factor n / 2 N reduced ratio into the sensitivity error, cf. (25). This is all the more important because, in the interest of averaging the influence of dynamic measured variable fluctuations, the ratio of the integration times should be N times T [low] o / n times T [low] o and thus the value N >> n should be made the factor n / 2 N at least with the values of

(35)

can work.

In order to save additional filter costs and shielding expenses in the measuring circuit installation, one is for the value if possible

(36)

with G = 1, 2, 3

d. H. choose an integral multiple of the period of the mains frequency, a dimensioning that has already been used with good success in measured value processing.

With the values of u [deep] m [deep] max = 10 mV in our example, the maximum sensitivity error becomes with (25) and (35)

(37)

This means that even values of the maximum sensitivity error

(38)

The influence of long-term fluctuations in the gain factor v on the sensitivity of the measuring circuit is therefore practically completely eliminated.

The conditions for the zero point error according to (26) are very similar. If one sets here again for all interference voltages in their ratio to the maximum measurement voltage u [deep] m [deep] max the values of to be adhered to with the lowest installation effort and the cheapest of the operational amplifiers commonly used today a, ie | u [deep] t | = | u [deep] o | = | u [deep] small theta | </ = 100 µV absolute, according to (26) maximum zero point errors of

(39) and thus values of

(40)

retain. In other words: all interference voltages may reach values of 5 times 10 [high] -2 - related to u [deep] m [deep] max - before in the worst case F [low] o [low] Qmax the required value of 10 can exceed [high] -4.

Usually the values of the thermal voltages u [deep] small theta and u [deep] t are always below 20 µV absolute in practice. In this case you can use the measuring amplifier even has a zero point drift u [deep] o [deep] max of

(41)

without exceeding the maximum permitted value of the zero point error of 10 [high] -4.

These few calculation examples prove that the requirements made at the beginning can be fully and convincingly achieved when used in bridge circuits. With minor, inexpensive expenditures and additions, e.g. double equipment of meters, all requirements of the calibration law with regard to the functional reliability of these circuits can easily be met.

If a bidirectional counter with a separate tare memory is used for Z [low] 2, the circuit can also directly take on the task of automatic zero setting and / or taring and / or tare specification.

In the exemplary embodiment of the invention according to FIG. 2, the switches are implemented by field effect transistors. The circuit is designed by using a high-impedance amplifier input circuit (R [low] E> 10 [high] 6 Omega) so that the forward resistance of these transistors does not lead to sensitivity errors> 10 [high] -4 even with values up to e.g. 100 Omega.

In addition to bridge circuits, all other transducers that can be built up with ohmic resistors in a bridge circuit can be used in conjunction with this analog-digital encryptor. This applies in particular to resistance thermometers, ohmic displacement transducers on NC machines, angle measuring devices, etc.

Claims (7)

1.Analog-digital encoders for passive transducers with a common DC supply voltage supply for the transducer and a reference voltage source as well as with an integration device alternately acted upon by the output signal of the transducer or the reference voltage source with the help of an integration time or voltage controlled changeover switch and a polarity reversal switch for the supply voltage of the transducer and a preamplifier for the output signal of the transducer, characterized by the combination of the following features: a) the polarity reversal switch reverses the polarity of the reference voltage in addition to the supply voltage of the transducer, b) the preamplifier is in the signal path after the switch, c) the measurement cycle is controlled via logic elements in such a way that an integration of the measurement voltage over a specified integration time and a down-integration of the reference voltage up to a specified voltage source after reversing the polarity of the voltage supply and simultaneous switching from the reference voltage output to the encoder output results in a down-integration of the measurement voltage over the specified time and an integration of the reference voltage up to a predetermined threshold follows. 2. Analog-digital encryptor according to claim 1, characterized in that the integration device is followed by a Schmitt trigger, the two mutually inverse outputs of which are connected via delay elements to two inputs of an OR gate and the output of the OR gate at one input an AND gate whose other input is connected to the output of a clock pulse generator and whose output is connected to the counting input of a first counter and a second AND gate to the counting input of a second counter and a transmission output of the first counter is connected to one input of a flip-flop whose other input and a reset input of the first counter is connected to the output of the OR gate via an inversion element and the output of the flip-flop is connected to the second input of the second AND gate and a control input of the switch is, and that the inverting output of the Schmitt trigger a n is a control input of the polarity reversal switch and a transfer input of a buffer for the content of the second counter, as well as a reset input of the second counter. 3. Analog-digital encryptor according to claim 1 or 2, characterized in that the integration device is a Miller integrator. 4. Analog-digital encryptor according to claim 1 or one of the preceding claims, characterized in that an output of the buffer is connected to a numeric display. 5. Analog-digital encryptor according to claim 1 or one of the preceding claims, characterized in that the polarity reversal switch consists of four field effect transistors which are controlled in pairs by mutually inverse outputs of the Schmitt trigger. 6. Analog-digital encryptor according to claim 1 or one of the preceding claims, characterized in that the switch consists of four field effect transistors which are controlled in pairs by mutually inverse outputs of the flip-flop. 7. Analog-digital encryptor according to claim 2 or one of the preceding claims, characterized in that in front of the inputs of the OR gate there are delay elements which respond to the transition of the signals from logic "0" to "L" when the signals transition from "L" to logic "0", however, forward the signals without delay.