DE2743952C2 - System for the delivery of digital data corresponding to analog signals via data lines of a programmable control device - Google Patents

Description

6. System according to claim 5, characterized in that with the delivery of the cancellation signal to Time of the start of the delivery of a holding of the said link signals causing release signal is started, which is one compared to the duration of the cancel signal has a longer duration

7. System according to claim 6, characterized in that the cancellation signal from that of the Write signal derived release signal obtained by means of a monostable flip-flop (190) will.

8. System according to one of claims 1 to 7, characterized in that when digital data is provided with a number of bits exceeding the number of data lines available for digital data transmission (DO to DT) by the analog-signal conversion module (100), the output of the relevant bits is carried out by means of an output device (500) in two bit groups during two successive cycles

The invention relates to a system for outputting analog signals via digital data Data lines of a programmable control device, which one in particular by a microprocessor formed central unit with address lines, with bidirectionally operated data lines and with control lines for outputting a write signal includes when it occurs on the data lines Digital data can be passed on to selected addressed data recording devices.

There are already known converter circuits that convert analog signals into corresponding digital data, which work according to different conversion principles, such as the counting principle and the iterative principle. So far, however, no converter circuits have become known that in connection with a programmable Control device are operated, which one in particular by a microprocessor formed central unit with address lines, with bidirectionally operated data lines and with Control lines for outputting a write signal include when it occurs on the data lines occurring digital data can be forwarded to selected addressed data recording devices.

The invention is now based on the object of showing a way, as in a system of the above mentioned type a particularly simple and yet safe implementation of a number of analog signal input devices output analog signals can be made in digital data.

The object indicated above is achieved according to the invention in a system of the type mentioned at the beginning in that a separate analog-to-digital conversion module is connected to the central unit is which converts an analog signal supplied to it on the input side into a digital data signal for delivery to the Data lines only converts to the inclusion of a separate conversion signal and which to the The end of an analog-to-digital conversion is only followed by the conversion of a further analog signal into a Digital data signal enabling termination signal generated and that with the analog-digital conversion module a number of analog signal input modules are connected for the output of digital data analog signals to be converted to the analog-digital converter module by issuing appropriate addresses can be released by the central unit.

The invention has the advantage that a reliable implementation of the from made of a number of analog signal input devices output analog signals in digital data will. The analog signals emitted by the analog signal input modules are transmitted after the Multiplex principle implemented in digital data including an especially easily available one in an advantageous manner

programmable control device, namely a microprocessor, can be used.

Further expedient refinements of the present invention emerge from the subclaims.

The invention is explained in more detail below with reference to drawings, for example

Fig. 1 shows schematically in a circuit diagram a programmable control device, which has a microprocessor used as a central unit to which the present invention is particularly applicable, schematically illustrating a manner in which the preferred embodiment of the present invention in the programmable control device is included; is

F i g. FIG. 2 shows a status diagram for one in the one in FIG. 1 used a standard microprocessor type 8080 from Intel;

F i g. 3 illustrates in a standard timing diagram the lines on various lines for one for the Use in the system shown in Figure 1 contemplated microprocessor of the Intel type 8080 occurring logic signals;

F i g. 4 is a circuit diagram illustrating the preferred embodiment of the present invention Invention for generating a selected analog output signal;

Fig.5 illustrates in a pulse and voltage diagram certain pulses and voltages, as they are preferred in the case of the one shown in Fig.4 Embodiment of the invention occur or are used, as well as some voltages that are shown in FIG. 6A_ 6B and circuits shown in FIG. 6C occur;

F i g. 6A, 6B and 6C illustrate one as a whole Analog-to-digital conversion circuit used for the JS application is provided in the illustrated in Figure 4 preferred embodiment of the invention;

F i g. 7 schematically shows an address of the type used in the operation of the circuit shown in FIG. 4 shown preferred Embodiment is used; .

F i g. 8 illustrates in a simplified link diagram, like certain impulses in the in F i g. 4 illustrated preferred embodiment of the Invention control input data locking in this embodiment;

Fig.9 illustrates in a timing diagram an erase and release or write pulse, the logic arrangement shown in Figure 8 and a corresponding linkage arrangement in the case of the FIG. 4 illustrated preferred embodiment of the Invention controls

The general control device system is explained in more detail below. FIGS. 1, 2 and 3 serve to illustrate a programmable control device A, which is used to control machines, processes and other systems on input information from inputs and on existing states or other parameters This control system uses the module and method according to the present invention. The input signals, states and parameters are fed to the control device A from various external connections and locations which are capable of providing binary information as single bits or as a plurality of bits, that is to say bytes. These external connections can be switches, coding disks or decoding disks, lamps, decoded analog data and binary-coded states. In accordance with normal practice, the control device contains memory locations and the processing is carried out in accordance with a program which is stored as a plurality of steps or instructions in such a system memory. Certain memories with random access are provided for storing the intermediate information or data. These memories can also be used for some program storage, although a program read-only memory is generally used to store the program information or program steps.

As in Fig. 1, the programmable controller A is a digital processing system that includes a plurality of separate and distinct plug-in modules that are interconnected by a plurality of control lines generally included in a motherboard interconnection system. Remote input / output modules are an exception to this. The basic modules and the control lines for these modules are shown schematically in FIG. 1 illustrates in which a central unit module (CPU) or module C711 uses a standard microprocessor as its central unit The microprocessor has a number of output address connections, a number of bidirectional data connections, setting devices which allow the chip to be set in a variety of known states, and devices which provide a status code at the beginning of each separate command on the data lines. Although a variety of microprocessors having these standard characteristics could be used, the embodiment illustrated by Figures 1, 2 and 3 contemplates the use of an Intel 8080 microprocessor having sixteen address ports and eight bidirectional data ports. Controller A closes the various ones Introduces concepts relating to the use of a microprocessor to process input and output information for the purpose of controlling a preprogrammed series of events of a machine, process, etc. In the embodiment shown, the input information is digital information, both at the input and at the output. In order to carry out conversion processes between analog signals and digital signals, however, converters at the interface between the device shown in FIG. 1 and the various analog inputs and / or analog outputs can be used. The central processing unit module 10 is connected to the other modules in order to process the input and output information on the lines D ₀ to D ₇ . A brief explanation of the separate modules should be sufficient to illustrate their intended use in connection with the central processing unit 10 as well as the overall operation of the programmable controller A.

In order to first program and test the control device A , a module 20 with direct access is provided which takes over the control of the various control lines connected to the central unit module 10

To program system A by an external device, as illustrated schematically by a digital computer 22. In the exemplary embodiment shown, the computer is connected to the direct access module 20 via lines 24 shown schematically. When a hold request signal is output from the module 20 to the CPU module 10, the computer 22 or other external control devices receive the control n of the address brakeline, a transfer marking line DBINP, the read / write line and the data lines Do through Dj, as well as other lines shown in FIG. 1 are indicated by arrows. When this occurs, the central processing unit is essentially separated from the remainder of the controller and the computer 22 can load memory, ie program the controller, and actually operate the controller, such as during debugging and troubleshooting. The random access module is used to load all memories of system A with the desired logic, to set inputs and outputs to the desired states, to read the contents of the memory or the various input and output circuits selectively, to reset control device A , between - to provide stop and sequence operations for the control devices A and to check the status of all memory positions and registers of the control device A, including the registers of the microprocessor MP in the central processing unit 10. The random access module is used for the flow of data to and from System A under the control of an external unit which includes a computer, external tape readers, a teleprinter, etc.

In order to effect the transfer of control to the module 20, the microprocessor MP of the module 10 is put into the hold state (HOLD), which will be discussed further below. The external programming device such as a computer or a tape reader, will send via the data lines Db to Di data to and from the control device A, and the location of the data is controlled by the address lines Ao through A \ s the fact that the microprocessor of module 10 is brought into the hold state (HOLD) instead of the hold state (HALT), the functions of the microprocessor can be taken over by the module 20 by a programmed signal or a programmed request. Furthermore, the controller can be restored by the microprocessor by means of a simple command without complex programming is required if the microprocessor goes into a halt state (HALT) it is not necessary to provide a trigger pulse to the controller of the system A through module 10 again. As soon as the hold state (HOLD) is triggered, the central unit module 10 takes over the control via the lines shown in FIG. 1 again. This represents a suitable way of giving the control device A direct access for programming and testing and then for enabling the control of the control device, which is separate from the module 20

The central processing unit 10 can be interrupted by external conditions in order to interrupt the program and in order to transfer control via the microprocessor to a subroutine stored in a fan memory. This is a standard interrupt feature of most 8-bit microprocessors. However, the control device A contains a large number of separate interrupt expansion modules, three of which are indicated schematically as interrupt expansion modules I, H, HI or 30, 32, 34. The difference between the first expansion module and the following expansion modules is that the release connection £ of the module 30 is assigned a link signal 1, which in practice is a voltage of 5 V in the control device or in system A. Modules 32,34 and any additional modules contain at the connection fine input enable link signal, which is controlled by the state of the previous interrupt expansion modules connected expansion modules 32, 34 etc. In each of the interrupt expansion modules in the illustrated embodiment there are 16 separate interrupt inputs, which are illustrated schematically as a plurality of single pole, grounded switches 30a-30x, 32a-32 * and 34a-34jt, respectively. This interrupt inputs can be logic inputs that receive information corresponding to a selected subroutine prompts the transition of the module 10 in the disconnected state for the purpose of processing Accordingly causes the actuation of an input to the microprocessor MP of the module 10 to perform an interrupt and proceed to the subroutine which is to be processed or processed Then the control is returned to the execution program of the control device or of system A. By using this interrupt expansion arrangement, a large number of selectable subroutines can be provided and canceled by issuing an interrupt request to one of the multiple logic inputs shown schematically. System A's executive or organizational program requires processing of a "look up" command or sequence for those data or link inputs and outputs under interrupt control only when an interrupt request has been received indicating that a particular port or ports are in use should be sampled and / or updated.

When an interrupt request by the central unit module from an AiBchniS of an expansion module is recorded, the micro-

ss processor goes into an interrupt state, and a certain subroutine is selected or "canceled" by data from the expansion module by an address appearing on the lines D _{0 -Dj.} Then the polling input signal or

eo output signal in agreement with the desired and required interrupt subroutl - ne processed. Thereafter, the subroutine makes an instruction transition back to the main program. If there is no interrupt request, the organization program is processed repeatedly without the interruption subroutines to be edited. Accordingly, the subroutines are only called and processed when necessary. the

to

is

20th

2s

30th

The number of expansion connections for modules 30 to 34 can be increased to larger values. the the only practical limitations are the storage capacity expanded to various capacities and the time available to process the interrupt subroutines.

By providing the interrupt expansion modules, the microprocessor of the system or of the control device A can be interrupted with a significantly greater frequency than is the case with known microprocessors is required, can be used for many separate input signals or states. This saves time and money and also allows subroutines which may be stored in the memories of system A to be used for a periodic purpose only. The versatility of system A is thereby greatly expanded while still using an easily available, relatively inexpensive microprocessor will.

The module 40 is a programmable read-only memory module, which is also referred to below as a PROM module. This PROM module is used in system A to permanently record the link status established by the link signals on lines A ₀ to Am at the various addressed locations. In practice, the organization program and the various subroutines are generally permanently stored in the various addressed memory locations within the PROM module 40. This memory module is used for long-term or permanent storage of the program; it uses MOS memory chips. which can be erased by exposure to ultraviolet light and which are programmable by separate devices, such as by a computer 22 or by a tape reading device via the random access module 20. In practice, the PROM module has a capacity of 4096 8-bit words. The number of words available in read-only memory module 40 can vary in accordance with the desired capacity of system A. In practice, due to the memory technology used in module 40, static, silicon-gated, erasable and electrically re-programmable MOS-based read-only memory chips are used

During normal operation of the control device Λ , data are output from the module 40 via the lines Cb to Lh. .Pitnngfn the parallel transmission of Binärriaten this leads I -only output a 8-bit word, which is by linking the signals on lines Aa- A s _t addressed in F i g. 1 it is indicated that the data volumes Cb- D ₁ in the PROM module 40 are bidirectional. This is only used for the purpose of loading the memory during the programming and test operation via the random access module 20. The Spekhercfaips of the module 40 are in practice not erasable under normal circumstances. Therefore, constant power supply to this particular module is not required to operate the

or the

so

ss

to get stuck. Even in some cases, a variety of different types of read-only memories could be used to store the program information for system A , as shown in FIG. 1 is shown schematically.

With particular reference to the memory module 50 comprising a random access memory (RAM), it should be noted that this memory module can be updated periodically while the system or the controller A is in use. Various random access memory modules could be used in the system. The random access memory module 50 includes some standard parity check circuitry 52 as shown in FIG. 1 is shown schematically as a result of which the to and from. checks information passed to the random access memory chips for parity, in accordance with normal practice, to make an error determination. In practice, the module 50 uses solid state random access memory chips with a capacity of 4096 8-bit words. In this module, an external battery supply is used to hold the information or the data in the various storage locations in the module 50 until the information or the data are changed in an intentional manner by the operation of the control device A. The semiconductor memory technology used in module 50 is an N-MOS technology leading to static random access memory. The module 50 can be addressed both for reading and for writing by means of the logic signals on lines Ao-A \%. This logic signal or address selects the desired address for the RAM module and routes the 8-bit word in question from the corresponding memory location in parallel to the data lines Da-Ch . The DBINP link signal and the A / W link signal determine whether or not to introduce data into the module 50, or whether or not to read data from the module concerned Another type of digitally programmable control device is known; accordingly, various systems can be used.

In addition to the PROM module! 40 and the RAM module 50, it is possible to provide an additional memory, which can be implemented as a PROM memory and / or as a RAM memory. The parity circuit 52 is in In practice, it is formed by such a type of circuit which supplies a 9-bit word and which provides a circuit arrangement which is required to generate and check a bit for an odd parity per word. When an 8-bit word is written into memory, the parity generator checks the word and generates a ninth bit, which is either a logic signal "1" or a logic signal "Θ" occurs so that the resulting 9-bit word always Contains an odd number of "!" link states or link signals If a word is out the memory is read, the parity check circuit makes a check to see if the word concerned still contains an odd number of "!" logic signals If the test circuit an even number of "!" link signals determined, the pressor is interrupted in accordance with normal microprocessor practice. It Other parity checking circuits or systems can be used to avoid errors in the Information can be ellt to which an access has been made

The programmable controller A uses a standard microprocessor which has eight data ports and sixteen address ports. This allows an 8-bit word or byte to be processed by the microprocessor at the same time. This capacity has clear advantages with regard to reading from different inputs and writing to different outputs. Linking processing of a single bit within an 8-bit word, such as spurious, or sparse, or inverting processing, however, presents a significant difficulty. A significant amount of software programming is required to link processing a single bit of an 8-bit word or byte. This requires storage space and extensive programming. This disadvantage becomes even more serious in the control of machines and a process, since a large number of simple logic functions are required Processing single-bit information with an 8-bit data capacity thus results in a considerable increase in program memory space and control complexity. If, for example, a single input signal is to be compared with a single output signal, the use of 8-bit input information is a disadvantage. When memory addresses or binary-coded data are transmitted or processed, the large number of data lines is an advantage. In order to overcome the disadvantages associated with the link processing, which are caused by the increase in the capacity of the microprocessor, a circuit arrangement is provided by the control device system A by means of which one-bit information is obtained which is transmitted on a selected data line, such as the data line Db, can be relationally processed in a manner similar to that of a single bit data processor. This makes it relatively easy to carry out an AND, OR and inversion logic operation at various inputs and outputs in order to implement logic functions that are considered to be more complex with the advent of the expanded 8-bit microprocessor. To illustrate the use of both the byte and bit modes, a byte input and output module 60 and a bit input and output ioda! The module 60 has a series of input words, each of which comprises eight data bits. These words are generated by various input devices, such as by an encoder disk network 62. Similarly, the output words from the module 60 are illustrated as display signals in a display unit 64. Accordingly the module 60 is used to input or output an information byte as an 8-Bh-word at the various input or output points.

A single information bit is input or output from the system driver or module 70 on the individual data Cb. If a bit operating mode is selected by the circuit arrangement which is constructed or designed in accordance with the present invention, then only the logic signal appearing on the line Db is thus processed. The link signals on the remaining bidirectional data lines are left out of consideration or ignored. In order to determine whether a single information bit is passed to the output units 80 via the system driver circuit 70 or not, the system driver circuit is controlled by the input line DBINP and the read / write

Line R / W controlled logic signal occurring. A supply voltage source 12 emits a direct voltage of 5 V for the operation of the logic arrangement in the system A and a direct voltage of 12 V for the operation of certain other components. The 2 V and 4 V lines from the supply voltage source 12 are used to deliver voltages through which the logic signals of the RAM memory are maintained if the supply voltage supply is unintentionally interrupted. These two lines are controlled by rechargeable batteries. Of course, a variety of other supply voltage devices could be used in accordance with the desired supply voltage requirements of the programmable controller A.

In the following some definitions regarding the control lines are given. Referring again to FIG. 1 it should be noted that there are shown a number of control lines which establish a connection between the central processing unit 10 and the various other modules which constitute the programmable controller system A or comprise. These control lines are located outside the central processing unit. In many cases, however, they correspond to certain connection connections of the microprocessor of the TVp Intel 8080 or are linked to those connections of the microprocessor, as in the case of the one shown

«Ο Embodiment of a programmable controller embodying the present invention is used. In consideration of the general operation of the programmable controller system A, let the basic function of each of those shown in FIG. 1 explained separately In the course of the description, the inverted form of a line designation indicates that a low link state - whether a pulse state or a permanent state - is present or a "yes" state is present

So is S o, for example, the read / ScnraB line labeled R / W indicates that there is a read status with a link signal "1" and that a write status exists with a link signal "0". This standard is used in most microprocessors

gen ss and similar digitally controlled digital processing facilities used Anla ben Utzt

A negative or a low potential 100 ns linkage pulse occurs on the synchronization signal line SYNC , which indicates the beginning of the respective eoeO machine cycle. This pulse is not programmable; it is used to lock the status word in the respective component or the respective modal, which requires a status word from the central unit for use during an entire general cycle that contains em or several words or

The external clock pulse ί 2 is from the internal

Central processing unit clock generator generated; he can do it can be used to synchronize the operation of the various modules. This impulse or this Signal can also be used as an accurate time base signal. In practice this has a clock signal either a frequency of 2.0 MHz or 3.0 MHz.

The address lines Λο - | 5, with the exception of the address line A, s actually all carry the logic signal "0". The logic signal on these lines is also used to provide the address for all memory and input / output modules for control system A. These address lines are generally output lines from module 10. If the random access module 20 is used, however, the lines in question are bidirectional lines which enable addresses to be entered into the module 10. Ao denotes the address bit with the lowest significance on the address lines

The direction of transmission of the data lines Cb-A is designated on the DBINP line. This control line is used to scan or forward data on the data bus lines from the respective module of system A.

The A / W line is used in system A to scan or route data on the data bus lines to the addressed memory locations. In view of the similarity between the Dfi / WP line and the Ä / W line, these lines are generally used together. The Z? B / W line is used to determine the direction of the data flow and to transfer the data to the To key or route the godparent bus lines. The Read / Sdifeib line R / W is used to determine whether this data is being written or read. By provision of two control lines, the data on the data bus line or the lines D ₉ -di during the pulse-wise reading and Sch s rub stable on the AE / W line.

The waiting line is used in conjunction with the standby line. These lines are available in connection with the microprocessor, which allows an additional period of time for reading slower Storage or input / output locations enabled If during an addressed output the module 10 does not have a link state or a Logic signal "1" picks up on the standby line, then the microprocessor enters the Wait for as long as that Stand-by line leads to a low link signal. In this state, the Wute ^ Lehung is on Link signal »0« generated as soon as the ready input signal is recorded, the microprocessor comes out of the waiting state, and A interference signal "1" occurs on the waiting line on. This feature is clearly shown in Fig.2, the refers to the operation of the Intel 80e0 type microprocessor

The output irr ι E denotes the content of an internal interrupt release fupflops in the microprocessor of the type Intel 8080. This internal flipflop can be set or reset by release and blocking Unterbrednmgsbefehls and causes the blocking of the admission or acceptance of subsequent UutetlHwliiingsituf requests the microprocessor, warn the relevant FGpftop is in the reverse state. The internal Ffipflop, which is formed on the chip itself, is automatically reset in order to block further interruptions at the time Tl of an instruction call cycle M \ and when an interruption from the microprocess or has been accepted

The WLD / 4 line is the hold or hold acknowledgment line. The link signal occurring on this line changes to a link signal "0" then over when a hold or hold request

ίο (HOLD REQUEST) is confirmed by the microprocessor MP . This hold request is supplied by the hold request line, as shown in Fig. 1. The hold state (HOLD) of the microprocessor transfers the address and data

The microprocessor closes in a high-impedance state, so that these connections enable control via the address lines A ₀ -A \ ₅ and via the data lines Da-Dj . These lines can be controlled by the access module 20 during programming and during the Durchte least. The signal on the // LDM line begins at time Ts for a read-memory or input cycle. For a memory write or output cycle or for an elite operation, there is a shift on the / TED / i line with the clock period following the Tj clock period. In practice, it is known that the signal on the / YLJM line which appears after a rising edge of a Φ1 pulse on the high impedance address lines and data lines occurs after the following edge of a Φ 2 pulse that occurs on the hold request Line (HOLD REQUEST) indicates that there is an external request to put the central unit and in particular the microprocessor chip into the hold state (HOLD). In this hold state, external devices can control the address and data lines as soon as the central processing unit has finished using these lines with regard to the processing of the existing or present machine cycle.The control is provided by the central processing unit via the DS / NP line and the R / W line also given up again. In other words, these lines can be controlled by the random access module 20 for programming or other external control functions. In summary it should be noted that. when a hold state (HOLD) is required, the microprocessor goes into hold state (HO LD) and issues an output signal via the // LXM line to display this hold state (HOLD). This state occurs after a certain cleaning up or a certain completion during a processed machine cycle. The relevant hold state will come into effect during the next machine cycle and hold the existing internal link with regard to the register states of the microprocessor chip.

A corresponding arrangement is used for the reset operation. A reset request is made from the supply voltage supply 12 or from the direct access module 20 on the reset request loan When this request is received by module 10, the microprocessor reset The content of the internal program counter of the 808Q microprocessor is reset in this state deleted After the reset impulse has occurred

start the program at a location with word 0 in memory. The internal INTE and HLDA Füp flops of the microprocessor chip are also reset. The internal accumulator, the stack pointer and the registers are not cleared. When the reset state is entered, the logic signal is shifted or changed on the reset line (RESET), whereby the various flip-flops and other logic devices within the system Λ are reset. This is used to put the control device system A into operation.

The bidirectional data bus lines or lines Db to D ~ j establish an 8-bit data connection to the central processing unit 10. In addition, these is lines are connected to the various memory modules and input / output modules. The modules, which only carry out bit functions, in contrast to byte functions, only use one of these lines, at least for data output. In the preferred embodiment, this is the line Do. During the first clock cycle of each machine cycle of the microprocessor, the central processing unit emits a status word via the data line or the bus line Db- Di . This status word is an 8-bit word which describes the current machine cycle. In this status word, the line Do carries the least significant bit in the preferred embodiment other numbers of data bits can be used without departing from the purpose of the present invention. However, when using an 8-data-bit microprocessor, the status word may have eight bits generated by the microprocessor in accordance with the command or instruction received from the program

In the now available microprocessors there is an interrupt property, as has been briefly described above. An interrupt property or possibility of the microprocessor allows its current setting or position to be stored in a program, to jump to a called subroutine, to process the subroutine and then jump back to the correct place in the program that was previously processed. In order to carry out this function, the microprocessor has an input INT, and the module 10 has various interrupt request connections INT0-INT7. The logic signal appearing at the / NT connection transfers the microprocessor to the interruption state. At this point in time the connection INTE (INTE-line) is fed in order to avoid subsequent interruptions until the selected subroutine in the INTE connection is postponed at the relevant point in time The lower priority interrupt subroutine has ended if the TNTE port has been reset by the processed subroutine. Heretofore, processing systems employing a microprocessor have had the ability to accommodate only a finite, relatively limited number of interrupt requests. This limitation was set by the limitations of the various codes available for subroutine selection or "subroutine prompting". System A uses a system which contains eight interrupt inputs via which the microprocessor is placed in the interrupt state. The interrupt connections INT0-INT3 and INT5-INT7 are illustrated in FIG. 1. In practice, these interrupt connections are assigned to external states, connections or parameters, which can be input or output signals. The priority of the interrupt requests runs in reverse order of the numbering with which the highest priority has the lowest number or the number of the lowest priority possessing t the highest number Accordingly, the FLVR state - is formed by a combination signal to zero when the supply voltage supply is switched off has been - represents the interruption with the highest priority. If this status is present, the program will go over to the subroutine “supply voltage supply switched off”, which is located at a selected memory location in the memory, regardless of other interruption statuses; in practice this memory location is given by the octal value 010. The next interrupt input signal is in practice the signal BOOT, which generates an interrupt request INT2 for a memory location in the memory. In this way, a minimal program for the initial operation of system A is available. This introductory minimal program is housed under the octal address 020 of the memory; it is "invoked" by various devices shown in FIG. 1 are indicated schematically as a push button switch or pushbuttons. The interrupt request INT3 establishes the module lock and parity state, which is processed in accordance with known practice in order to maintain the continuity of the various modules. The interrupt request INT4 is a real clock interrupt request by means of which the program is transferred to the memory location in the memory designated by the octal address 040. This will be explained in detail with regard to the interrupt functions of system A. The interruption or interrupt request INTS is a transmission interruption in the preferred embodiment of the invention. By this interrupt is a memory cell having the Oktalbezeichnung 050 is referred to in the memory This allows connection of external devices forth as 20 from the direct access module The interruption INT7, which has the lowest priority, transferred to the microprocessor in the disconnected state to external devices such as coding disks or coding wheels, lamps, switches and visual display devices or to write in these external devices. This leaves the interruption INT6 , which is used in connection with the modules 30, 32 and 35 to expand the scope of the interruption possibility in the system A. The receipt and processing of an INT6 interrupt request are acknowledged from the // V6 output. This signal line remains in the low link level state while the interruption device transmits a request from one of the modules 30 to 34 to the central processing unit 10. The call command becomes synchronous with a

Φ transmit 2-clock signals; it supplies the address in the memory under which a call is placed during a selected additional interrupt which is supplied by the added modules, of which only three are shown.

This description of the basic lines or command paths that run to and from the central processing unit 10 should suffice for a complete one Understanding of the invention, in which the use of an improved module is provided, which in ι ο Connection to a microprocessor-using programmable control device of the in Fi g. 1 is used schematically shown type. These output and input lines follow the nomenclature used by Intel Corporation for whose microprocessor chip labeled 8080 is used, that of the preferred embodiment of the present invention is used. A corresponding nomenclature is also used in others commercially available microprocessor chips are used that have the properties presented here as background information as well as explanatory information known per se in the field concerned The properties of this microprocessor chip are known per se. The module 10 could be an I-STROBE- or generate I-key pulse on a control line, and for the software delivery of a key pulse for the various inputs and outputs, if this should be necessary.

The status word for the microprocessor will now be considered in more detail. In the microprocessor as used in module 10, as in most microprocessors, a status word occurs at the data connections as the first word of the respective machine cycle. This status word indicates the operation to be performed by the microprocessor during the current machine cycle. Although a variety of status codes and status conditions could be provided, the diagram of FIG. Figure 2 illustrates the ten status words used in the Intel 8080 microprocessor. The data terminals perform this encoding, as specified in the vertical columns for each of the various types of machine cycles during the initial part of each cycle, the binary "status code to the terminals Lk-Eh g is in a status Verriegelungsschaltun with the introductory synchronizing locked on the SWC line

If the machine cycle is given by a command fetch, then the code word occurring on the data lines Da-D ₁ , which is held or locked in the status locking circuit, is given with 01000101. The one at each of the data connections during the initial part of the cycle occurring binary code indicates a state, as indicated in the column "status information" According to the microprocessor of the type Intel introduces 8080 used terminology, the link signal of the data bus Db the interrupt acknowledgment signal (INTA). This interlocking that ^b0 shows fung signal to, whether an interrupt request has been confirmed or acknowledged; It can be used to push a restart command on the data bus lines when the DBIN or Dß / A / P line is active or effective. The link signal occurring on the *> 5 line D \ during the initial part of the machine cycle indicates whether or not there is a write function. This status is denoted by W; the relevant status is indicated by a link signal 0 if data is written to the memory or to an output point in the machine cycle. If a logic signal 1 occurs on the command line D ₁ and is held or locked in the status interlocking circuit, then reading is carried out from a memory or from an input point. A logic signal 1 appearing on line Di during the instruction read portion of the cycle indicates that address bus lines Ao A \ s are holding the stack back address from the stack pointer of the microprocessor. This status, which is designated with STACK or with Stack , is only effective during a stack reading machine cycle or during a stack writing machine cycle.

If a logic signal 1 appears on the data line Ds during the initial micro cycle of a machine cycle, this indicates that a halt HALT has been acknowledged. As can be seen from FIG an interrupt acknowledgment during the stop is effected Otherwise, perform during the initial micro-cycle is designated by T] in Figure 3 these data bus a, a logic signal 0th During an output function, the logic signal on the line D * is given by a logic signal 1. This logic signal occurs when the machine cycle is in an output-write cycle Output device contain or lead and that the data bus line finally contains the output data during the cycle or leads when the line R / Wein link signal 0 leads The link signal occurring on the data line Cb represents a signal which indicates that the microprocessor is in the Pick-up or Fetch cycle for the first byte of an instruction is located. Accordingly, a logic signal 1 appearing on the line Ds during the initial part of the machine cycle indicates that an instruction is to be received from memory or another location. This represents the status Mi as it is shown in FIG F i g. 2 is illustrated. Status INP is obtained on data line A. A logic signal 1 occurring on this line during the status part of a machine cycle indicates that the address bus lines carry or contain the address of an input device and that the input data should be given on the data bus lines when the DBIN output of the microprocessor is active the DBINP line of the central unit module 10. The logic signal MEMR occurs on the data bus line Dj . A logic signal 1 occurring on this bus line during the status information part of the cycle indicates that the data bus lines are being used for a memory read operation.

During the status part of any cycle, the logic signal appearing on the data lines Dn-Di represents the in FIG. 2 indicated codes. This logic signal results from a function specific to the Intel 8080 microprocessor. The coding in question is only used here for the purpose of easier understanding of the

preferred embodiment of the present invention ac given.

Now, the basic instruction cycle for the central processing unit module is considered in more detail, the microprocessor used in the preferred embodiment of the present invention has a basic instruction cycle as illustrated in Figure 3. If the timing of the microprocessor through the input pulses Φ Ι, Φ 2. The first-mentioned input pulse sets fix the introductory part of a micro cycle; this part of the cycle is denoted by Tt-T _5. The micro-cycle Tw is used for the purpose of designating a wait state, which has been discussed above in connection with the interaction between the read link arrangement and the wait link arrangement The microprocessor switches to a wait state, as is characterized by the occurrence of a logic signal 1 on the wait line This means that a logic signal 0 occurs on the WAIT line.If the memory is then ready, a logic signal 0 occurs again on the wait line on, and the microprocessor continues in micro cycle T ₃ . A synchronization pulse labeled SYNC is available for each machine cycle. This synchronization pulse corresponds essentially to the internal synchronization pulse of the microprocessor of the type Intel 8080. The pulse is somewhat shaped. The pulses shown in FIG. 3 are those pulses which are introduced into the module 10 and led out of it. In this case, however, it is basically the impulses from the microprocessor itself. During each of the microcycles, the function indicated in the lower part of FIG. 3 takes place. Sometimes three microcycles are used. In other cases, many microcycles are required for a particular instruction. For example, if memory is accessed on the Intel 8080 microprocessor, then up to 18 microcycles can be used in normal operation. During the micro cycle Ti of a machine cycle, the logic signal is read on the lines Do-Dj. The address on lines M ₀ - Ai ₅ (at the address connections of the microprocessor MP) is supplied either from the internal program counter or from another register within the microprocessor.This address information is introduced into the program counter or into the program register during a previous machine cycle.The DBINP Line corresponds to the internal Dß / N line. This line is used to determine whether or not data are to be sent to the data lines Do-Di in a subsequent sub-cycle or micro-cycle of the machine cycle May require microcycles. The logic signal appearing on the lines indicated in FIG. 3 changes according to the type of command to be processed, in accordance with the practice known per se in the field of microprocessing. These link states are used in describing the preferred embodiment of the present invention

Referring to FIG. 1, it should be noted that System A includes an analog-to-digital converter module or A / D circuit 100, as best shown in FIGS. 6A, 6B, and 6C Conversion of an analog input voltage into digital output data or digital output data. According to the preferred embodiment of the invention, the obtained or converted digital data signal is multiplexed via the data lines Do-D,

A system directed in a yet to be described manner to be converted an analog signal s via the line 110, 112 is supplied with a Umsetzbzw. Converter signal ADC is provided on line 114 to enable the operation of the converter circuit

is 100 at the end of this pulse. After the conversion of the analog signals into digital data has been completed by the circuit 100, a logic signal 1 occurs on the reset line 116. Accordingly, an analog signal is routed together with a conversion signal on line 114 to circuit 100. Thereafter, a termination logic signal 1 is generated on reset line 116. Multiplex module 120 is present in system A , as shown in FIG. 1, different modules of these modules could be used to route a large number of analog input signals to the circuit 100 in multiplex mode. In the embodiment shown, module 120 is indicated as input module I, which is then followed in connection with FIG. 4 will be discussed in detail. This module is illustrated schematically in Figure 6A with analog input modules 122 and 124. Of course, several modules could be used to increase the possibilities of analog input. These modules are always the same modules, each comprising eight separate analog input circuits or input circuits TCO-TCl . Of course, any analog signal could be one of the

Input circuits TCO-TCI can be supplied without changing the operation of the input module 120. The input lines or the input circuits TCQ-TCJ route analog status signals to the module 120. These status signals can be a temperature signal, a speed signal, an acceleration signal, a position signal or any other signal which is inherently an analog signal. Referring to FIG. 6A, it should be noted that the other input modules 122, 124 are parallel are connected to lines UO, 112 in order to pass selected analog signals to the conversion circuit 100 by selectively closing the switches 126, 128 of a module. As in Fig. 4, only the input circuits at 7UO and TCl are shown in detail for the sake of clarity. In practice, however, eight separate inputs or input circuits TCO- TCJ are provided for each analog input module.

Returning to Fig. 6A, it should be noted that during operation the various analog input circuits or inputs TCO-TCJ of the analog input modules 120, 122 and 124 with the various analog data to be read and converted into digital data for use in system A Signals are applied. One of the modules 120, 122 and 124 is addressed and activated by a suitable address of the type shown in FIG. 7. An ADC conversion signal is provided on the line 114

which runs from the activated modules 120, 122 or 124 to the analog-digital circuit 100. The input module 120 reads the logic signal appearing from the data lines Da-Di and decodes it. This decoded information causes the selection 3 of one of the analog inputs 7 ″ CO- TCl and leads to the output of the selected signal via the analog signal lines 110, HZ Modules 120, ι ο 122 and 124 is connected The occurrence of this logic signal leads to the resetting of all modules for the subsequent selection and operation. In this way, several input modules can be multiplexed with the conversion circuit 100 is for the purpose of generation of digital data corresponding to a selected input analog state from the addressed analog input modules.

Let us now refer to FIG. 4, in which the preferred form of the analog input modules 120, 122 and 124 is schematically illustrated in only two analog input circuits TCQ-TCl . In practice, a larger number of input modules can be used, and each module contains Practice eight separate analog input circuits 7U0-TCl. For the purpose of describing the operation of module 120, the two input circuits 7UO and 7C7 are shown; thus the addition of further input circles parallel to ^ o the relevant input circles should be evident.

The module 120 will be explained in connection with a cycle for selecting and outputting an analog signal to the conversion circuit 100. This description of the operation of module 120, in conjunction with the components used in the preferred embodiment, will clearly illustrate the inventive concepts of the present invention. In Fig. 7 shows an address as it is used to select a predetermined module and the data lines via which one of the circuits or input circuits TC0-TC7 is selected. The address lines At-Ak are used to select the chassis in which the modules 120, 122, 124 are accommodated and the particular module during an input / output command from the system A shown in FIG. The address of the module is determined by its position in or on the chassis using the hard-wired digital data that is made available at the various chassis locations. This represents an input / output, ie an input / output address, which is to be distinguished from a memory address which is used to store data from the lines Do- ~ D ~ r. The address lines A ₆ -At ₀ , A ₁₂ , A _i} relate to the type of operation for processing data that is not contained in the module 120. From the system A , data is then transmitted via the data lines Ί% ~~ Εζ output when a write cycle is activated by the write pulse on the write line R / W. A module decoding or addressing circuit 130 is provided on the input side of the module 120. The address on the lines Aa-Aj and Au, A ₁ *, Au leads to the appearance of a ^ύ5 logic signal 0 on the CS line 132 when the chassis in which the module 120 is accommodated is to be activated on the address lines M. -Ai occurring link signal is compared with a hard-wired link signal in the mother card at the attachment point of the module 120 in order to output a comparison signal to the address circuit 130. Assuming that the addressing is correct, a logic signal 1 occurs on the output line 134 from the addressing circuit 130. The module 120 is activated by this logic signal. A write logic element 140, which is a NAN D logic element, has a first input 142 connected to the DÄ / NP line via an inverter 144. The second input 146 of the logic element 140 is connected to the line R / W via an inverter 148. A pulse appearing on this line generates a write signal for module 120. Assuming that module 120 has been addressed and that the central processing unit of system A has received a command to process a write operation in response to the output command, the DB performs / NP-Lehung a link signal 0. Finally, the write line R / W carries a write signal again, ά. H. a logic signal “0” for the input of the inverter 148. At this point in time, all input lines of the logic element 140 carry a logic signal 1. Accordingly, the output 150 of this logic element changes to logic state 0, which indicates a write mode .3 is generally 500 ns in length. Accordingly, a write pulse formed by a logic signal 0 with a duration of 500 ns is generated on line 150. An inverter 152 connects line 150 to line 154 at clock connection 2A of a monostable device 160. This device has a known time delay of 23 ms, as determined by the bias circuit A positive voltage jump on line 154 causes a positive pulse to appear at the <? - connection of line 162 of monostable device 160. This causes a logic pulse 1 with a duration of 2.3 ms at one input of the NAND element 164. The output of this logic element is connected to the A DC line 114. As far as described, no selection signal occurs on line 170. Accordingly, the output signal of the logic element 164 is a logic signal 1 which has not been switched over in order to trigger or actuate the circuit 100.

The logic element 180 is also controlled via the write line 150. A logic signal 0 occurring at this input of the logic element 180, which is a NAND element, leads to the output of a logic signal 1 on the output line or output line 18Z the inverter 184 inverts and leads to the output of a logic signal 0 on the line 186, which is connected to the negative clock terminal \ A of a monostable device 190. This monostable device gives a negative pulse with a duration of 100 ns on the one connected to the line 192 Output terminal ~ Q off. Thus, when a write signal is present on line 150, a line 192 occurring on the negative 100-ns pulse to a NAND gate 200 is supplied, which e has inen Äfldtsfe / AEingang The system jerk partially line leads during

of the operation of system A, a logic signal 1. Accordingly, a logic signal O occurring on line 192 causes a logic pulse 1 with a duration of 100 ns to be emitted from output 202 of logic element 100. Inverter 204 inverts this logic signal and supplies a logic pulse Ojm to the extinguishing line 206 connected to the clear terminal CL of a conventional 8-bit addressable lock decoder 210. This decoder is cleared to generate 0-7 zeros at all output terminals during the occurrence of a clear pulse on line 206. The logic signal appearing on the data line D ₃ controls the decoder 210. A logic signal 0 occurring at the connection E prevents the occurrence of a selection logic signal at any connection 0-7. The connection E of the locking decoder 210 is used to lock or hold a logic signal 1 at one of the output or output connections 0-7, in accordance with the binary logic signal on the input lines L \ Di and D ₁ , which are connected to the input connections a, b and c of the lock decoder 120 are connected. It is assumed that the logic signal on the line D3 is a logic signal 0. If a write pulse with a duration of about 500 ns occurs on the line 150, the locking decoder 210 is locked in order to decode the logic signal on the lines D ₀ -D ₂ . However, the clear terminal CL leads to an upper running or oversteer of the locking connection £ during the occurrence of the 100-ns-erase pulse on line 206. This concept is in Figure 8 and 9 illustrates Accordingly, when an address, such as g in F i. 7, occurs, and when the central processing unit generates a write signal, the locking decoder 210 is first cleared -aus-8-Decodieningjtes logic signal on the lines Dl-D ₂ fixed. This locking of a connection leads to the actuation or activation of one of the input circuits TC0-TC7. In this embodiment shown, only the input circuits 7UO and 7t 7 are illustrated. Accordingly, only the connections 0 and 7 are shown at the output of the decoder 210. The inverters 224, 226 invert the logic signal appearing on the lines ZZD and 222 in order to generate opposite logic signals on the lines 230 and 232, respectively. These last-mentioned lines, eight of which are used in the preferred embodiment, are connected to the input of a selection NAND gate 240. The on the data line Ds occurring during a module addressing logic signal controls the overall operation of the latch decoder 210. If the line A performs a logic 0 signal, line Th, when it comes to the data line of the system A of the latch decoder 210 performs an on terminal D Link signal 1. This enables locking decoder 210 to apply a link signal 1 to one of its outputs

to save. In the course of this explanation of the preferred Embodiment of the module 120 is assumed that the decoder 210 by a logic signal 1 on the connection ^ is released

If none of the circuits at the output of the locking decoder 210 in the module 120 can be made ineffective, the link signal on the lines D _{3 is} made a link signal 0 in order to generate a link signal 0 at the selected output of the decoder 210. A logic signal 0 occurring at all output connections of the locking decoder 210 leads to the generation of a logic signal 1 at all inputs of the selection logic element 240 and a logic signal 0 on a selection line 170. This logic signal 0 is also generated during the deletion cycle of the decoder 21G when one of the output connections 0-7 has been selected during a write command by the decoded logic signal of the lines D ₀ -D ₂ , the state of the selection line 170 changes to a logic signal 1. This logic signal leads in combination with the logic signal on the line 162 to generate a negative pulse the AOC line 114. This finally causes the conversion circuit 100 to convert the analog signal between the lines UO, 112 into a digital output code, in a manner to be described in more detail below.

Furthermore, an inverter 250 is controlled via the selection line 170, through which a logic signal 0 is generated the line 252 is generated when a selection has been made by the decoder 210. This logic signal 0 keeps the occurrence of a logic signal 1 on line 182 is maintained even if the write pulse on line 150 is finally during of the processing cycle disappears. Accordingly, the monostable becomes during a single write command Device 190 to a negative terminal M controlled by line 186 is not again clocked

If the link state on the line 170 changes to a selection link state 1 while a write address occurs, this link state or this link signal 1 releases the two transistor switches 126, 128 in the circuit 260. Accordingly, the switches 126, 128 of the module 120 are closed , whereby the selected analog state is switched through from the module 120 to the input of the conversion circuit 100. To provide an analog signal for use on lines 110, «2 za erisaiicn, ssd relay control networks 300, 302. The network 300 controls the circuit input switches CR 0 * CROb, CRT, and CRTb- The network 302 controls the output switches CR 10 " CR 10 e, CR 17" and CR 17 *. The transmission of analog data on lines 110, 112 from a selected circuit of circuits 7CO, 7C7 is determined by the operation of the re-control network values. In the embodiment shown, only two input circuits are shown. Each of these circuits 300, 302 contains only two relay control circuits. In practice, however, eight separate output circuits are used and each of the networks 300,302 contains eight separate relay circuits. With regard to the network 300 it should be noted that

that this network is used to open a selected set of input switches CR Ο » CR Ob, CR 7, and CR 7 _b in the input circuits TCQ, TCl. The relay circuit 310, when fed, opens the relay-controlled switches CR 0 " CR 0 ₆ in the input circuit TICO. The relay circuit 312 opens the contacts CK 7 » CRTb- when a certain analog input circuit TCO, TC7 is selected by the locking decoder 210, a logic signal O accordingly occurs on the input side of one of the inverters 314,316. As a result, a logic signal 0 occurs at the output of the relevant inverter and at the input of one of the circuits 310 or 312.

The circuits 310,312 are connected to the +12 V line 318. With the selected circuit TCO or TC7, a logic signal 1 accordingly switches off one of the relay circuits 310, 312. Since the switches of the relay circuits are kept closed by a logic signal 0 or by the lack of a selection state at the inverters 314, Ή6, the input switches that are controlled by the deactivated relay circuit open. With regard to those used in practice and shown in FIG. 4 schematically indicated relay circuits, it should be noted that only one relay circuit of the network 300 will be made ineffective. The other relay circuits remain in effect in order to keep the input contacts of the unselected circuit TCO- TC 7 in the closed state.

The relay circuits 320, 322 of the network 302 feed the selected relay circuit instead of disabling the selected relay circuit. The inverters 324, 326 invert the logic signal appearing on the lines 320 and 322, respectively. Accordingly, the analog states selected by the locking decoder 210 generate a logic signal 0 at the output of one of the inverters 324, 326. This logic signal 0 activates the selected relay circuits 320, 322 and closes the output switches CA 10 »CR XOb or the Output switch CR17 » CR \ 7b. The capacitors 340 of the circuits TCO ₁ TC7 are charged to the voltage determined by the thermocouple or by the other circuits TCO, 7C7 controlled by transducers. When one of the analog states is selected, the input switches are opened in that one of the relay circuits 310, 312 is inactive or de-energized. In a corresponding manner, the output switches of the selected circuit are closed in that a corresponding relay circuit of the relay circuits 52O, 3zz is fed or excited.

The voltage stored on the capacitor 340 of the input circuit TCO is selectively delivered to the lines 342, 344 when the switches CR 10 »CK ΙΟ * are closed. The output lines 342, 344 are connected in parallel to the lines 350, 352, which represent the input lines of the signal generation circuit SC of the module 120. The voltage stored on the capacitor 360 of the input circuit TC7 is output to the lines 362,364 via the output switches CR 17 »CK! 7j. These lines are connected to the signal generation circuit SC via the lines 350, 352. The remaining six circuits are also connected to lines 350, 352 when selected by decoder 210.

The signal generation circuit may be any circuit form to generate an analog signal having a fixed voltage across circuit 100 during the comparison. In practice, the fixed analog signal is generated by a constant current signal which is proportional to the voltage stored on one of the capacitors 340, 360. In the embodiment shown, the signal generation circuit SC contains a differential amplifier 400 which emits a constant output signal on line 401 which is proportional to the input voltage of capacitor 340 or capacitor 360. The base voltage of a transistor Q 2 , which is connected to a current control circuit 402 and to a voltage limiting circuit 404 in such a way that a proportional current is generated on the output line 406, is controlled via this output line. This current is proportional to the analog input voltage. Many lines can be used to convert an input voltage into a precisely controlled constant output current. This concept is used in accordance with the present invention so that the resistance or impedance on the output side of the module 120 and on the input side of the conversion circuit 100 in conjunction with the connection resistance will have a negligible effect on the signal which the module 120 receives from the module or the circuit 100. The current-generating circuit SC framed by dash-dotted lines in FIG. 4 has the parameters or component values specified for the various components. These values are inherently characteristic for the illustration of a system with the aid of which a constant current is generated which is proportional to an input voltage applied to lines 350, 352. Of course, any number of power signal generation circuits could be used for this purpose. As shown schematically in FIG. 6A, the input voltage on the lines 350, 352 is controlled by the differential amplifier 400 and by a current control arrangement 402 in order to obtain a selected constant current flow via the switches 126, 128 of the selected input analog module 120 . The closing of the output switches CR 10 » CR 10 /, and CR 17» CR V _{b of} the one selected circuit of the circuits TCO, TC 7 is delayed by a monostable device 410 by a period of 1.5 ms Input switches or input switches are open before the output switches CR 10 »CK 1O ₄ , or CR 17» CR Ub are closed by the supply of one of the circuits 320, 322. A variety of arrangements could be used for triggering the delay time. In the embodiment shown, the one monostable device 410 is activated or activated by a negative voltage jump occurring on the line 186 from the output of the inverter 184.As soon as a write signal occurs, a logic signal 0 appears at the (^ -connection of the monostable device 410. This reduces the base voltage of the transistor Qi , which prevents the +12 V supply voltage from being supplied to the line 328 on the output side of the circuits 320, 322 12V to the

230232/282

Line 328 released. This allows the triggering or actuation of the circuits 320, 322, whereby the output switches of the selected analog input circuit or analog input circuit CRO -CR 7 are closed. The circuits 310, 312 are connected directly to the +12 V supply voltage via the line 318. Accordingly, the circuits 310, 312 are put into operation as soon as a selection has been made by the decoder 210. With regard to the operation of the circuits 320, 322, however, there is a time delay during a known period of time in order to avoid the connection of the circuit SC to a measuring voltage source which could generate excessive currents or variable voltages.

The operation of the in F i g. The embodiment of the invention shown in FIG. 4 is further illustrated in FIG. 5, in which certain pulse sequences are shown. As can be seen, the input switches CR 7 shown are opened as soon as a selection signal has been generated by a monostable device 190. After a time delay controlled by the monostable device 410, the output switches CA 17 are then closed. The monostable device 190 controls the erase pulse during a period of time which is less than the operating time of the logic element 140. A monostable device 160 controls the end of the comparison signal ADC, which triggers or allows the comparison function in the circuit 100 to run

Reference is now made to FIGS. 6A, 6B and 6C, in which one type of analog-to-digital conversion circuit is illustrated Supplies voltage which is proportional to the constant current supplied via the switches 126, 128 of the activated module 120, 122 or 124. An integration circuit 450 having the functions shown in the integration voltage diagram according to FIG. 5 takes up the constant voltage present at the resistor 440 and controls the sawtooth waveform of the integration circuit during a fixed period of time. With regard to the in F i g. 5 integration voltage illustrated between the times 7Ί and 7}, it should be noted that this integration voltage leads to the charging of the integration circuit (capacitor) at a fixed rate that is defined within the integration circuit 450. At time T ₂ , the integration voltage curve has reached the capacitor threshold voltage at which the output a link signal i is effected via line 452 for a purpose to be described in more detail below. Thereafter, the voltage in the integrator rises at a rate that is determined by the voltage across the resistor 440. After a fixed period of time, the counter provided is reset at time 7a and the sawtooth voltage controls the state of charge so that the voltage discharge (of the capacitor) from the point M to a lower reference level at the point in time 7s. This discharge takes place at a fixed speed that is achieved by a constant reference voltage. is controlled. This fixed speed causes the voltage to reach the threshold voltage at time T _4. The interval between times T ₂ and T ₄ is characteristic of the magnitude of the voltage present at resistor 440. By operating a counter controlled with a fixed frequency during the period between times T ₂ and T ₄ , the counter becomes one of the voltage

the resistor 440 achieve a proportional counter position or count a proportional number of pulses. After the point in time T _{4 has been reached} , a logic signal 0 occurs on line 452, the purpose of which will be described in more detail below. Above

ίο the line 452 is controlled by one input of the NAND element 454. The other input of this AND element is connected to a fixed frequency oscillator or clock generator 456 via a line 458. As soon as the point in time T _{2 is} reached, the AND element 454 becomes effective in order to generate counting pulses with a fixed frequency on the line 455. A logic signal 1 occurs on line 460 between time T ₄ and time Ts. The A / D control combinatorial circuit 470 becomes this

used to change or shift the direction of the voltage in the integration circuit 450 after a fixed period of time (T _3). A Sägezahnsteuerimpuls generated by the well as a control circuit to b echar nenden circuit 470 to the end of the ADC pulse to set as is illustrated in Figure 5. Accordingly, the control logic circuit 470 is controlled by the positive slope of the ADC comparison signal upper control line 472 controls the control linkage

circuit the integration circuit 450 in a time relationship as shown in FIG. 5 illustrates in top accordance with a conventional practice in some respects via the clock line 455, the count of the counter 480 is caused to start a Rückstellei tung 482 has during the occurrence of AEDC pulse, the counter 480 is reset; the counter in question cannot count. The pulses coming from the oscillator 456 and transmitted via the logic element 454 are then fed to the counter 480 via the line 455. The counter is a 12-bit counter with output connections DBO-DBU. The counter 480 can have an overflow line 484, so that when the counting range is exceeded, as indicated by the connections DB 0- DB 11

can be read, a logic signal 1 occurs on this line This logic signal causes a logic signal 1 to appear on the return line 116, regardless of the termination of integration, which is caused by the

so the link signal is signaled on line 460. One at the end of the integration or at Link signal that occurs when an overflow condition is present 1 causes a logic signal 1 to appear on the one labeled »Reset« Reset line 116.

In the following, the output side of the circuit shown in FIG. 6A will be discussed in particular. The link signal at the connections DBO-DB ti shows the share or percentage

of the maximum counting range that is determined by the conversion circuit 100 has been recorded For an area of 100% there are at least ten ports necessary. The eleventh connection can indicate an overflow and the output of a link signal

of line 484 control. Another, with DBu The designated line can indicate a sub-area that would be present if no voltage was applied the resistance 440 lies This can then be the FaD,

if there is an open input circuit in an analog input circuit CRO-CR 7. If this is the case, a step in a line, such as line DB11, can occur !! Link signal can be read. Of course, other arrangements could also be provided in order to display the status of the circuit 100 at specific output connections, such as the connections DBO-DBW . All that is required is that a suitable digital code is provided to indicate the magnitude of the voltage across resistor 440.

The number of output terminals DBO-DB 11_ used by the circuit 100 exceeds the available data lines Do-Dt in the system A. For this reason, the output multiplexer circuit 500 is as shown in FIG. 6C is provided in order to use all digital data from the connections DB 0- DB 11. A logic signal 1 appearing on the line 116, which indicates that the conversion has been completed, activates the locking line 502, whereby the data at the connections DBO-DBW in the multiplexer circuit 500 are locked. The multiplexer circuit is then enabled via a line 510, which is controlled by hard-wired addressing on the input side of a module selection circuit or a module selector 512 on the basis of the mother card. This module selector corresponds to the selection circuit 130 according to FIG. The address appearing on lines A _{0 -Ai 5} is fed to an address decoder 516, which forwards the data on lines A ₀ -A ₃ to the control module selection circuit 512. The status or the signals of these address lines are or will be with the hardwired code signals occurring on lines 1, 2, 4 and 8 are compared.

In addition, the decoded information is passed from the address lines Aq-Am via the line 520 to enable the multiplexer 500, namely to select 8-bit information from selected connections DBO-DBW. These data are output via the bidirectional data lines D ₀ -Dj . The data from the remaining connections DBO-DBIl are then selected by means of a second address. In practice, the connections DB Q-DB 7 are selected with the first address for data output via the bidirectional data lines DO-D7. Then the next address is selected by means of a second address Group of output lines DJJ 8-DBIL selected. Accordingly, in a series of two steps, all the data from the conversion circuit can be output multiply via the bidirectional data lines 25-25. By providing two bytes of information from multiplexer circuit 500, an overall range of information data for use in system A can be provided. This exploitation can be used to replace heating elements, change a speed or change other functions that are monitored by measuring the voltage across the resistor 440. The circuit arrangements shown in FIGS. 6A, 6B and 6C as a whole illustrate the general operation and the circuit element structure of a conversion circuit 100 which can be used by the modal 120, as illustrated in FIG. Of course, modifications of this conversion circuit and its multiplex operation could be made as long as the conversion system receives analog data in the form of a stream, converts this data into digital form with a conversion pulse, provides the relevant data to output connections after conversion and then a conversion termination signal for use in the selection termination module 120

Returning to module 120, it should be noted that when a termination pulse is received on the reset line 116, the inverter 550 generates a link pulse 0 on the line 551. This link pulse 0 is a pulse that terminates the selection and actuates the monostable device 410 or triggers. Accordingly, the selection is for the lifting by means of corresponding control of the reset line the voltage on line 328 thereby lowered, the activated one of the circuits 320, 322 made ineffective Further, the closed switches CR 10 "CR 10t or switches CR 17 * CR 17 /, opened immediately. The selection-terminating pulse on line 551 also controls a monostable circuit 552 which is biased in the manner indicated in order to generate a 1.5 ms pulse corresponding to the pulse generated at the output of the monostable device 410. This pulse occurs at the (^ -connection; it is formed by a link pulse 0 As soon as this pulse disappears, ie after 1.5 ms, a clock control takes place at the plus connection \ b of the monostable circuit 190. This again becomes a 100-ns Output pulse generated on line 192 in order to delete the addressable locking decoder 120 by a link delete pulse 0 occurring on line 206. Accordingly, the disabled relay circuit of relay circuits 310, 312 is activated by the 12 V supply voltage via line 318 As a result, the input relay switches CR 0 _Λ CROb or the input relay switches CR 7 _Λ CR 7 _b

♦ ° closed depending on which of these switches were opened during an input select operation. Accordingly, no voltage is applied to lines 350, 352 of module 120. In addition, the lines 230, 232 now carry a link signal 1. As a result, a link signal 0 occurs on the selection line 170. The switches 126, 128 are open. The logic element 164 is rendered ineffective or blocked, and the logic element 180 is, as it were, unlocked by a logic signal 1 appearing on the line 252 for the reception of a subsequent write pulse on the line 150 any one of the McduJn 120, 122 and 124 can be selected for the input of a further analog state by the relevant module and to the conversion circuit 100. Only one conversion circuit needs to be used for all modules. Although three modules have been used for inputting analog information in the illustrated embodiment, in practice the signals from 16 modules can be decoded by the information on address lines A ₀ -A ₃ .

The module is together with the conversion circuit

100 a hardwired, self-sustaining component for use in system A After a selection has been requested, module 120 and circuit 100 function and wait

to

15th

then. The decoded information remains on the locked lines DBO-DB ti for the purpose of reading in subsequent or through subsequent cycles until it is unlocked by a new write cycle address on an input module together with the appearance of a circuit selection code on the lines D ₀ - D ₃ appears

For the purpose of biasing the monostable devices 160, 410 and 552, it is a constant Supply voltage of 5 V emitting supply voltage circuit 560 is provided, which a logic signal 1 or outputs a voltage of +5 V to the control line 562. In the embodiment shown, the Control voltage of + 5 V is used for the link and the supply voltage of + 12V is used for the Operation of relay control circuits 310, 312, 320 and 322 are used

As stated in the course of the description of the preferred embodiment, can be used in the Circuit arrangement various modifications can be made to the various parameters or to produce sizes and states that are used in the operation of the module 120, which according to FIG present invention is constructed

In accordance with the illustrated embodiment of the present invention, the system uses an automatic data link between the analog-to-digital conversion circuitry and the analog input circuitry via the ADC and "Reset" lines to reduce the number of programmed commands required to respond to the analog Input signal to receive a digital representation at the connections DB 0 - DB 11.

The system also uses an automatic data link between the analog-to-digital converter circuits and the analog input reset circuit to reset the selected analog input automatically to the unselected state, regardless of programmed Command. This increases the frequency with which a given input is accessed

25th

40 can be obtained while a desired one Transfer accuracy is maintained.

In conclusion, it should be stated in summary that the present invention creates a system is by what digital data that characterizes are for a selected analog signal, on a programmable data line. Control device in which a central processing unit is used, the output address lines, a selected number of bidirectional input / output data lines, a device for generating a write signal on a write line and Comprises means which, in response to the write signal, data from the data lines into selected ones Write address storage locations. The system includes a conversion circuit through which the analog input signal is converted into a digital data signal which occurs at output data connections and with the recording of a conversion signal and the simultaneous recording of an analog signal facilities are provided that provide a completion signal then generate when the conversion is complete In addition, there are at least two input analog signal modules provided, each of which facilities for Au. lame at least two analog states Also includes means are provided that a selected state of the analog states in convert an analog signal. In addition, selection devices are provided that one of the states on the Select generation of write signal. In addition, facilities are provided that one of the Activate or operate input modules. In addition, signal control devices are provided, which are based on the Control or actuation of a module towards the selected analog signal to the conversion circuit conduct. The selection devices are locked by locking devices until the Final signal is generated Finally, control devices are provided which control the actuating devices allow only one of the input modules to be actuated at a certain point in time.

In addition 5 sheets of drawings

Claims (5)

Patent claims: 1. System for the delivery of digital data corresponding to analog signals via data lines a programmable control device, which is formed in particular by a microprocessor Central unit with address lines, with bidirectional operated data lines and with control lines for outputting a write signal includes on its Occurrence of digital data occurring on the data lines to selected addressed data recording devices are conveyable, thereby marked, that a separate 'S analog to digital conversion module is connected (100) to the central unit (10) which ooting to him on the input side supplied analog signal into a Digitaldatensignai for delivery to the data lines only to di e Au of a separate conversion signal (ADC) converts and which, upon completion of an analog-digital conversion, generates a termination signal that only enables conversion of a further analog signal into a digital data signal,
and that a number of analog signal input modules (120,122,124) are connected to the analog-digital conversion module (100) which are used for the output of analog signals to be converted into digital data to the analog-digital conversion module (100) by outputting corresponding addresses from the central unit (10) can be released. 2. System according to claim 1, characterized in that the analog signal input modules (120, 122,124) with the analog signal conversion module (100) via a selectively actuatable switch arrangement (126,128) are connected. 3. System according to claim 1 or 2 , characterized in that the conversion signal (ADC) is derived from the occurrence of the address designating the respective analog signal input module (120; 122; 124) 4. System according to any one of claims 1 to 3, characterized in that a respective Current signal representing an analog signal before an analog-digital conversion into a corresponding « Voltage signal is implemented. 5. System according to one of claims 1 to 4, characterized in that each analog signal input module (120; 122; 124) contains an addressable locking decoder (210) which responds to the output of a write signal from the central unit (10) for holding logic signals defining analog signal output devices (TCO, TCl) is effectively controlled after it has previously been supplied with a clear signal derived from the relevant write signal