CA1118901A - System for converting analog signals to multiplexed digital data - Google Patents

Abstract

SYSTEM FOR CONVERTING
ANALOG SIGNALS TO MULTI-PLEXED DIGITAL DATA
Abstract of the Disclosure A system for providing digital data representative of a selected analog signal on the data lines of a programmable controller using a central processing unit having output address lines, a selected number of input/output bi-direc-tional data lines, means for creating a WRITE signal in a WRITE line and means responsive to the WRITE signal for writ-ing data from the data lines into the selected address loca-tions. The system comprises a conversion circuit for convert-ing the input analog signal to digital data on output data terminals upon receipt of a conversion signal simultaneously with an analog signal and means for creating a completion signal when the conversion is completed; at least two analog input modules, each of the modules including means for re-ceiving at least two analog conditions, means for converting a selected one of the analog conditions to an analog signal, selecting means for selecting one of the conditions upon creation of the WRITE signal, means for actuating one of the input modules, directing means responsive to the actuation of a module for directing the selected analog signal to the conversion circuit, means for latching the selecting means until creation of the completion signal; and, means for actuating the actuating means of only one of the input modules at any given time.

Description

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DISCLOSURE
The present invention relates to the art of program-mable controllers of the type using a microprocessor for a central processing unit and more particularly to a system for converting analog signals to digital data in such a program-mablecontroller.
The invention is particularly applicable for convert-ing analog input conditions, such as temperature controlled ~voltages, to digital data for the data lines of a micro- `
processor programmable controller, and it will be described with particular reference thereto however, this invention has somewhat broader applications and may be used for converting various analog signals to digital data for use on the data lines of various programmable controllers.
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BACKGROUND OF INVENTION
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In recent years,there has been~developed a series of ~
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microprocessors of the type used to process dig1ta1 data in -a manner similar to digital computers. These microprocessors are integrated circuit chips which generally include a series of output address lines, four or eight bi-directional data lines, and a series of command lines, such as READ, WRITE, WAIT, READY, HOLD and synchronization. r~ith the advent of this type of miniaturized device, digital processing of in-:
formation for a variety of applications has become possible and relatively inexpensive. Most development work has been ~ ;
directed toward the concept of utilizing the relatively limi~
ted terminals of a microprocessor to process the digital data ;
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. . . ," , . . ~, ',1 ;, ~ GD15-10-599 in a series of machine cycles di.vided into a series of micro cycles. As an example of one of many possible uses, a microprocessor has been incorporated into a programmable controller in a manner that recognizes the limitations of the microprocessor and provid,es substantial external hardwire modules ~o employ ; the limited functional characteristics of the microprocessor in a total system having the capabilities o~ inputting and o~tputting either bit or byte digital data. Consequently, the programmable controller using a microprocessor can con-trol various machines, processes9 and other sequential manip-ulations, This type of system, to be universal in nature, requires ~he use of a conversion circui~ for converting in~
put analog signals into digital information available on the `15 data lines of the microprocessor forming the central part or central processing unit of the programmable controller. Var-~ous circuits'are known for converting analog to digital in- i , ' formation~ These circuits incl~de a devlce ~or inputting ` an analog ~oltage and converting the magnitude of the volt-age into digitaL data on output terminals to be used by da~a lines of the system9 s,uch as a digitaL computer. These avail-. " able conNerting devices usually employ a multiple bit output ', data representative of the magnitude of the input analog sig- :
~a}. Generally, the dig~tal data ls ~he output of a binary ` 25 counter having several s~ages, such as twelve. Thus, a ull ,` scale conversion of an input voltage signal by such a convert- :~
-- ing c~rcuit requires ten output terminals to read between O
, . , and 999. This would gi~e a full scale conversion of the ~npu~
`~....... .s~gnal between 0~ a~d 99.9%. One additlanal ~erminal is,gen erally used to show that the counter has star~ed to ount. ,, ; . , .. . . . . . .

.` ' ~ , . , ~ 3 0~L i ) GD15_10_599 Consequently, eleven or twelve output data termlnals are employed at the outp~t of an analog conversion circuit of the general nature used in converting analog input v~lt~
age signals into output digital full scale readings. Such a conversion circuit is well adapted for digital computers having a greater number of data llnes; however, when using a programmable controller employing a microprocessor, there are insufficient data lines for accepting full scale digital . o~tput data for the input analog signalO Thus, if ten output terminals are required for a full scale reading3 a micro-processor having only four data terminals can not accept the digital information in its output form from a s~andard type - of conversion circuit. The same is true of the higher capac-ity microprocessor having eight da~a lines. For tha~ reason, 15 . efforts have been made to provide a standard conversion cir-.. ` cui~ for use in a microprocessor having a limited ~umber of data lines.
In systems to be controlled by a programm~ble controller, ` it ~s often necessary to input a large number of analog sig-nals, such as thermocouple voltages, speed analog signals and po~ition analog.signals. Consequently9 any analog system for genPral purpose use with a programmable controller must have ~ an analog input circuit for accepting a large ~umber of analog `~ signals and converting ~hem to digital data for use on the bl-`` ~5 dlrectional data lines of the mlcroprocessor. This has pre-`;~ 8ented a substantial amou~t of difficulty in adapting a micro-` processor for use in a programmable controller system. As a :` ~rst proposal for accomplishing this fea~, it was suggested ~ . .
that the number of digital ccn~erting circuits be increased ~s t~e input analog signal increased. This substantially ~ . . . .

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~ ~ ) GD15~10-5991 added to the size and c~st o a progra~nable controller, the advantage of which is the reduction in size and a low.capltal lnvestmentO Thus, such an expansion arrangement was coun~er-productive to the basic'concept of using a microprocessor in a programmable controller. The present invention relates to an analog system for input~in~ analog signals into a program-mable controller using a microprocessor, with its inherent limltations, which system allows a large number of input ana-log signals to be processed using only a single analog to digital conversion circuit.
STATEMENT OF INVENTION
In accordance with the present inven~ion,' there is pro-vided a system for providing digital data representative of a selected analog signal on the data lines of a programmable controller using a processing unit having output address lines, a selected number of input/output bi-directional data lines, means for creating a WRITE signal in a WRITE line and means ~' responsive to the WRITE signal for writing data from the data ' lines into selected addressed locations, The system comprises a conversion circuit for co~verting an lnput analog signal to ` digital data on output data terminals upon receipt o a con-version signal simultaneously wi~h an analog signal and means for creating a completion signal when 'the conversion is com ' pleted. The system also comprises an analog input module in-c~uding means for receiving at least two analog conditions, means or co~verting a selected one of the analog conditions to an analog signal, selecting means for selecting one condi-- , tion upon creation of the WRITE signal, directing means for directing the selected analog signal to the conversion circuit and means for latching the",selected means until creation of the .: , .

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~ GD15-10-5991 -completion signal.
By using this concept, a number of lnput modules can be incorporated and multiplexed lnto a s~ngle conversion circuit so that a great number of input analog signals can be processed in a programmable controller using ~h;s invention and controlled by a central processing unit of the microprocessor type.
: In accordance with another-aspect of the-invention, there is provided a system of the general type described above, which system employs a data latch for latching a signal select logic code upon receipt of a la~ch enabling signal. Also, this latch is cleared upon receipt of a clear signal. I~ accordance with one aspect of the i~vention, the enabling signal is created by the WRITE signal of the microprocessor and the clear sig-nal is created at the ini~ial stage of the enabling signal.
Consequently, a single program software command from the micro-processor to the analog input module clears ~he analog input module o~ any prior selected analog signal, allows data on the data lines of the microprocessor to settle on the input side of the data latch and then latches the incoming data, in de-~0 coded form~ onta ~he output terminals of the data latch. This coded data selects one-of several analog input signals con- -trolled by a single analog input module. In this manner, a 8ingle command to the programmable controller can be used to ~` . clear the latch and then set the latch to the desired current ~S analog signal to be processed. -~
` Other aspecSs of the present i~vention wLll be appreciated from a detailed descriptioll of the preferred émbodiment of the ~nvention.
" In accordance with the primarg object of the present in- `
vention there is provided a system for creating dLgital data , - 6 ~
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representative of a selected analog signal on the data lines of a programmable controller uslng a central processing unit, generally of the type employing a microprocessor, which system can selectively process a large number o~ input.analog signals to create representative dig1tal data on a single se~ of data terminals, Still a fur~her object of the present in~ention is the provision of -a system as described above, which system requires o~ly a single analog to digital con~ersion circuit. I
Yet another object of the present inver.tion is the pro-vision of a system as set forth above, which system can em-ploy readily available analog to digital conversion concepts.
. Still a urther object of the present invention is the provision of a system as defined above, which system can be used on a variety of microprocèssors.and other digital process-ing equipment without substantial modification o~ the equipment.
Still a further object of the present invention is the provision of a system as defined above, which system employs a reduced number of commands to process input analog signals, ~0 is generally universal in its use on digital equipment and can be incorporated in a single module connectable with existing . digital processing equipment.
Still a further object of the present invent~on is the provision of a system as defined above, which system employs an analog current signal at the analog to digital con~ersio~
- circuit to reduce the effect of circuit parame~ers on the .av~ilable analog si~nal at the co~version circui~.
. Another object of the present invention is the provision of a system as defined above, which system processes digital data having a greater number of bies than the data lines of .
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9 ~ GD15-10-5991 the pro~rammable controllers, These and other objects and advanta~es will become apparent from the following description ~aken together with the acoompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
In the drawings of this disclosure:
: FIGURE 1 is a schematic wiring diagram illustrating a programmable controller employing a microprocesso~ as a central processing unit of the type to which the present invention is particularly directed and illustrating, sche-~' matically,.a manner in which the preferred embodiment o the present invention is incorporated in~o the programmable con-troller;
FIGURE 2 is a status chart for a standard 8080 Intel microprocessor of the type using the system illustrated in FIGURE l;
FIGURE 3 is a standard pulse chart illustrating logic on ~arious lines of an Intel 8080 microprocessor of the type contemplated for use in the system illustrated in FIGUR8 l;
~20 FIGURE 4 is a wiring diagram illustra~ing the preferred embodiment of the present invention for creating a selected analog ou~put signal;
` FIGURE 5 is a pulse and voltage chart illustrating certai~
pulses and voltages employed in the preferred embodiment of the invention, as shown in FIGURE 4, and some voltages created in the circuit shown i~ FIGURES 6A, 6B and 6C;
FIGURES 6A, 6B and 6C are taken together to describe an .an~log to digital conversion circult of the type contemplated for use in the preferred embodiment of the invention as illus~
30 . trated in FIGURE 4; ..
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FIGURE 7 is a schematic illustration of an address of the type employed in operation of the preferred embodiment as shown in FIGURE 4;
FIGURE 8 is a simplified logic diagram illustrating how certain pulses in the preferred embodiment of the inven-tion shown in FIGURE 4 control the input data latch of this embodiment; and, FIGURE 9 is a pulse chart illustrating the clear and enable or write pulse controlling the logic in FIGURE 8 and corresponding logic in the preferred embodiment of the in-vention, as shown in FIGURE 4.

GENER~L CONTROLLER SYSTEM ~ ;~
Referring now to FIGURES 1, 2 and 3 wherein the show-ings are for the purpose of illustrating a programmable con-troller A for controlling machines, processes and other systemsin response to input information from inputs and existing con-ditions or other parameters. This controller system uses the ` ~
module and method of the present invention. The inputs, con- ;
ditions and parameters are directed to the controller A from various external terminals and locations which are capable of providing binary information as single bit or multiple bits, i.e. bytes. These external terminals may be switches, decoded thumbwheels, lights, .:

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decoded analog data and.binary coded conditions. In accord-ance with normal pract~ce the controller includes memory loca-tions and is processed in accordance wi~h a p~ogram stored as a plurality of steps or instructions in such system memory.
Certain random access memories are provided for storing inter-~ediate in~ormation or data, This memory can also be used for some program storage although a program read only memory is generally used for storage of the program information or steps, As illustrated in FI~URE 1, programmable controller A is a digital processing system including a plurality of separate s~d distinct plug-in modules ~nterconnected by a plurality . of control lines9 which are generally in a motherboard con-- necting system, exeep~ for remote input/output modules. The . .basic mcdules and control lines ~herefore are schematically illustrated in FIGURE 1 wherein a central processing unit ` module ~CPU) 10 or module CP711 employs a standard micro~
processor as i~s central con~rol unit, This microprocessor ls a known MOS integrated circuit chip which includes internal registers, counters, poin~ers and associated logic circuitry .well known in the art. The microprocessor has a number of ~` . . ou~put address terminals, a number of bi~direc~ional data . ` tenminals, means for set~ing the chip ~nto various k~own : .
: . 8tates and means for providing a sta~us code on .he da~a lines - a~ the start of each separate command. Although a variety of mlcroprocessors having these standard capabilities could be used, the embodiment illustrated in FIGURES 1, 2 and 3 invo~ves ~he - use of an Intel 8080 microprocessor which has sixteen address terminals and eight bi-directlonal data terminals. The con~ .
` ~oller A incorporates ~he various concepts relat~ng to the use of a microprocessor for processing input and output :~

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, , , ~ GD15-10-5991 informatlon tG control a preprogrammed series of events of a machlne 9 process, etc. The input information in the . illustrated embodiment is digital înformation both at the . ~nput and output; howeverj converters for conversion between analog and digital could be used to interface be~ween ~he . sys~em shown in FIGURE 1 and various analog inputs and/or outputs. The CPU module 10 is communicated with the other modules to process input and ou~put information on lines Do~D7~ A brief description of the separa~e modules ~ill be sufficient to illustrate their intended use with the CPU
. module 10 and th~ overall operation of programmable con-troller A.
- ` To initially progxam and debug ~he controller A, the~e . . ~s provided a direct access module 20 which takes over con- .
.`15 trol of several control lines connected to CPU module 10.
Thus, it is possible to directly program the memor;es in :
: controller or sys~em A by an external device, such as a .
. schematically represen~ed digi~al computer 220 In the illus-trated embodiment, the computer is connected to direct access module 20 by schematically represented lines 24. When a HOLD
. ` REQUEST signal is directed from module 20 to CPU module 10, . . computer 22, or other external control devices, obtains con-.. . .
" . . trol over the address lines, the input desig~atlon line DBI~P~ :
~he READ/WRITE line, and the Do~D7 data lines, and other lines . 25 shown by the arrows in FIGURE 1. When this happens, the CPU
. module is essentially disconnected from the rest of the con-; . troller and computer 22 can load memories, i~e. to pxogram - the controller, and actually operate the controller, as in de-.. bugging and troubleshooting.` The direct access module ~s used ; 30 eo load all memories o system A with the desired logic, set ' ' ' . . ' ' . ' ' . '.

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inputs and outputs to the desired conditions, selectively read - the contents of the memory or the various input and output circuits, reset controller A7 provide intermediate stop and run ope~rations for the controller A, and check the sta~us of all the memory positions and registers of controller A
.including the registers of the microprocessor MP in CPU
module 10. The direct access module is used for flow of .~ da~a to and from system A under the control of an external unit such as a cbmputer, external tape reading devices, teletype, etc.
Inlorder to accomplish transfer of con~rol to module 20, microprocessor MP of module 10 is placed into the HOLD
~- . state, which will be explained later. The external pro- .
grammerl such as a computer or tape reader, sends data to ; .;
. and from controller A through data lines Do-D7 and the lo-. . .
c~tlon of the~data is controlled by address lines Ao Als.
By placing the microprocessor of module 10 in the HOLD condi-tion or state, instead of the HALT state, the functions of . the microprocessor can be taken over by a programmed signal . ~ , . . .
.~ 20 or reque~t from module 20. Also, control by the microprocPssor ` ~: can be reestablished by a simple command without complex pro-.
; grammlng requlred when the microprocessor shifts to a HALT
state. It is not necessary ~o prov~de an initiation pulse . or agaln obtaining control over system A by module 10. As ;~
~oon as the HOLD conditian.is released, the CPU module 10 agai~ assumes control over the lines illustrated in FTGURE 1.
- This provides a convenient manner for giving direct access to : ......... ...the controller A for programming and debugging and then for releasing the controller for control, which is isolated from ~30 module 20. .- : . . . ...... -,: ....... . ~ . . . . ' , .
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CPU module 10 may be interrupted by ~x~ernal conditions to interrupt the program and shift control over the micro-processor to a memory stored subroutine. This is a standard INTERR~lPT feature of most eight bit microprocessors; however, 5- controller A includes a plurality of separate interrupt ex-pansion modules, three of which are schema~ically illustra~ed as interrupt expansion modules I, II3 III, or 30, 32 and 34, respectively. The difference between the first expansion module and subsequent expansion modules is that the enabled terminal E of module 30 is tied to a logic 1, ~hich in practice is five volts throughout controller or system A~ The subsequent modules 32, 34, and any additional modules, include an input enable logic at terminal E which is controlled by the condition of preceding interrupt expansion modules. This connection arrangement provides a priority level system wherein the ` : ~nterrupt inputs of module 30 have a priority over the interrupt inputs of subsequent interconnected expansion modules 32, 34, - etc. In each of the interrupt expansion modules, in-the illus-~ ~ trated embodiment, there are provided sixteen separate interrupt : 20 ~npu~s which are sche~atically illustrated as a plurality of single pole, grounded switches 30a-30x, 32a-32x and 34a-34x These ~nterrupt inputs can be logic inputs which contain in-formation requesting a shift of module 10 into the interrup~
-` : 8tate for processing of a selected subroutine. Thus, actuation of an ~npu~ wiLl cause the microprocessor MP of module 10 to `- interrupt and shift into the subroutine which is to be pxocessed~
Then contsol is returned to the executive progra~ of controller ` or system A. By using this interrupt expans~on arrangemen~, a great number of selectable subroutines can be provided and . 30 called by providing an interrupt request at one of the se~eral `~3 ' . . ' ' . .

`, schematically represented logic inpu~s. The executive program of sys~em A requires the processing of a l'look"
; . command or sequence or those data or logic inputs and ou~-puts under interrupt control only when an interrupt request is received indicating that a certain terminal or terminals should be scanned and/or updated, - When an interrupt request is received by the CPU module from a terminal of an expansion module, the microprocessor ~ifts to an interrupt state and data from the expansion , module selects or "calls" a given subroutine by an address on lines Do-D7, Then the calling input or output will be - processed according to the desired and requested interrupt - subroutine. Thereafter the subroutine will shift command back to the main program. I~ there is no interrupt request3 ; .
then the executive program is processed repeatedly without . ~ . .
,` , processing the interrupt subroutines. Consequently, the -~ subroutines are called and processed only when needed. The number of expansion terminals of modules 30-34 can be in-~ ` creased to larger values. The only practical limitations are ,~
20, the memory capacity which can be expanded to various capacities , and the time available for processing interrupt subroutines.
By providing the interrupt expansion modules~ the,micro-- processor of system or controller A can be interrupted a sub-stantia~ly greater number of times than is available on ~now~
,-: 25 microprocessors. Thus, the normal microprocessor interrup~
` : -, -concept of priorlty evaluation and jumpin~ to a subroutine - called by a particular interrupt can be used for many separate ~nputs or conditions. This saves programming time and allows - the use of subroutines which may be stored.into the memories of system A for only periodic use. The versatility of system A
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is thereby greatly expanded while stlll using a readily available, relative~y inexpensive microprocessor.
Module 40 is a programmable read only memory (PRO~I) .
module This PROM module is used in syste~ A for the purpose of retaining permanent logic at various addressed locations determined by the logic on lines Ao~A15. In prac~ice, the executive program and the various subroutines are generally, permanPntly stored at various addressed locations within PR~ module 400 This memory module is used for long term or permanen~ storage of the program and employs MOS memory chips that are erasable upon exposure to ultraviolet light and are programmable by means, such as computer 22 or a tape reading device through direct access module 200 In practice, . ` the PROM module has a capacity o~ 4,096 eight bit words. The number of words available in the read only memory module 40 ~ ; may vary according to the desired capacity of system A. In - practice, the memory technology used in module 40 is static .. silicon gate MOS erasable and electrically reprogrammable ~ read only memory chips~
During normal operation of controller A, data is directed . rom module 40 on li~es Do-D7. The parallel transmission of .. b~nary data on these lines provides an eLght bit word which . i8 addressed by the logic on lines ~o-A15. In FIGURE 1, it is ` " indicated that the data lines Do-D7 are bi-directional at PR~M
module 40. This is o~ly for the purposes of loading the memory during the programming and debugging operation through d~ ect - . `access module 200 The memory chips of module 40, in practice, , ~are not erasable under normal circumstances; therefore, con-tinuous applicatlon o~ power to this particular module is 30 not required for the purpose of retaining the stored logic.
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- lS.-. : ~ .. . .: , ~ GDl$-10-5991 Of course, a ~ariety of different types of read only m~mories could be used for storing the program infor~ation for system A, as schematlcally lllustrated in FIGURE 1.
~eferring now more particuarly ~o the random access memory (RAM) module 50, this memo~y module can be updated periodically during use of system or con~roller A Various random access memory modules could be used in system A~ The random access memory module 50 inc~ des a somewhat standard parity checking circuit 52 schematically illustrated in FIGURE
1. In this manner, information to and from the random access memory chips will be checked for parity in accordance with standard practice to determine an errora In practice, module 50 employs random access solid state memory chips with a capacity of 4,096 eight bit words. In this module, an external battery supply is used for retaining the information or data at the several locations on module 50, until the information or data is changed intentionally by operation of controller A.
The semiconductor memory technology used in module 50 is s~atic N-MOS ~andom access technology~ The module 50 is addressable for both reading and writing by the logic on lines Ao~AlS, which ; ~` address selects the desired address of the RAM module and directs the eight bit word from that ~ocation in parallel onto da~a .~ lines Do-D7. The DBINP logic and the Rf~ logir determines ` whether or not the data is being inserted or read from module 50~ Operation of a random access memory in conjunction with . - a microprocessor or other type of digital programmable con-troller is known an~ various systems could be employed.
I~ addition to the PROM module 40 and the RAM module 50, it is possible to-provide additional memory which may be in the form of PROM and/or R~M. The parity circuit 5~, in practice, .
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is of the type which provides a nine bit word and circultry necessary to generate and check one bit of odd parity for each word, When an eight bit word is written into the memory, parity generator tests the word and generates a mnth bi~ which will be either a logic 1 or a logic 0 such that the resulting nine bit word will always contain an odd number of logic 1 conditions.
When a word is read from the memory, parity check circuitry checks to be certain tha~ the word still contains an odd number of logic l signalsO If the check circuit encounters an even number of logic 1 signals, the processor is interrupted in accordance with ~andard microprocessor practice, Other parity checking circuits or systems could be employed so that errors in the accessed in~ormation can be detected, Programmable controller A employs a standard microprocessor ` 15 which has eight data terminals and sixteen address terminals.
,. In this manner, an eight bit word or byte can be serviced simultaneously by the microprocessor, This capacity provides distinct advantages with respec~ to a reading of several inputs and writing into several outputs, However, the logic process-ing of a single bit in an eight bit woxd such as ANDing9 ORing, ` or INVERTing, presents substantial difficultyO A substantial ` amount of software programming is required to logic process `,-" a ~ingle bit of an eight bi~ word or byte. This requires ~emory space and e~tensive programming. This disad~antage is even more serious in controlling machines and process because a great number of s;mple logic functions are req~ired~ In . . ..
- duplicating a standard relay logic diagram or laddex diagram `` - ~uch of the processing is logic processing of single bit in-formation. Thus, to process this single `bit information with an eight bit data capacity drastically lncreases program :`, ' . ` . ` `
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storage space and control complexity For instance, when a s~ngle input is to be compared with a single OUtp-lt~ the ~se of eight bit input information is a disadvantage. ~hen memory addresses or binary c oded data is being ~ransferred or processed, then the large number of data lines is beneficial. To overcome logic processirg disadvantages caused by increasing the capacity of the microprocessor, controller system A provides-circuitry for obtaining one bi~ information which can be logic processed on a preselect~d data line, such as line Do, ;n a manner similar 10 , to a single bit da~a processor Thus, it is a relatively simple process to AND, OR and INVERT logic at various inputs and out~
puts to provide logic functions which a~e rendered more complex - ;~
. - with the advent of the expanded eight bit microprocessor~ T3 - - lllustrate the use of both the .byte and bit modes of opera-tion, there is illustrated a byte input and output module 60 and a bit inp~ and output module 70. Module 60 has a ` ` series of input words each of which has eight data bits. These " - words are created by various inputs, such as thumbwheel net-work 62. In a like manner, the output words from module 60 are illustrated as display signals in a display unit 64. Thus, `` module 60 is used to input and output a byte of information as an eight bit word into various input or output ioca~ions.
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single bit of information is inputted or output~ed from ~ `. thR system dri~er or module 70 on a single data line Do~ Thus, when a bit mode of opera~ion is selec~ed by circuitry, con~
;8tructed i~ accordance with tke present invention, ~he logic `;of line Do only ~s processed. The logic on the other bi-- directional data lines is ignored, To determine whe~her or ` ~ ~ot there is a single bit of information directed to ~he ou pu~
`iO units 80 through system dri~er 70, the system driver is controlled . . . . - .

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by the logic on the inpu~ line DBINP and ~he READ/WRITE
line R~. A power supply 12 provides five volts D.C. for operation of the loglc in sys~em A and twelve volts D.C. for - the operation of certain other components The 2 volt and 4 volt lines from the power supply 12 are used for retaining the logic of the RAM when power is inadverten~ly interrupted.
These t~o lines are controlled by rechargeable batteries. Of course, a variety of other power supplies could be provided in accordance with the desired power requirements of programmable controller A.
-. CONTROL LINE DEFI~IITIO~S
Referring again to FIGURE 1, a number o~ control lines are illustrated as communicating between CPU module 10 and . the various other modules comprising the programmable con-troller system A. These control lines are external of the . CPU module; however, in many instances they correspond to or are logically associated with certain communicating terminals on the 8080 Intel microprocessor used in the illustrated embodi-` me~nt o~ a programmable controller using the present invention.
To apprecia~e the general operation of programmable controller sys~em A, thè basic function of each of the lines illustra~ed ` ~n FIGURE 1 wilL be described separately. Throughout the speci~fication the inverted form of a line designation indicates that . ` a low log~c condition, whether pulse or con~inuous, is the true or "yes" condition. For instance, the READ~ line labe~ed ` - R~ indicates that the read condition is a logic 1 and the wri~e` ~ -condition is a logic 0. This convention is used in most equipment employing microprocessors and similar digitally controlled numer-:~ ~cal processing devices. . -` The ~ynchronizing signal line S~NC consists of a lOOns ~ , .
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- . ~ . .

89 ~ ~ GDlS-10-5991 negative or low logic pulse i.ldic~Ling the beginning of each B080 machine cycleO This pulse is not programmable and is used to latch the status word in each component or module which requires status information from the CPU for use during S a total machine cycle which may contain one or more words, The external clock pulse 02 is crea~ed by the CPU internal clocking generator and can be used to syn~hro~ize the operation - of the various modules. The signal may also be used as an accurate time base. In practice, this clock has either a ~0 2~0 MHz or a 3.0 MXz frequency.
The address lines Ao_~l5 are al~ logic 0 true, except for AlS. The logic on these lines is used tn provide the address to all memories and I/0 modules for controller system ` A. These addre~s lines are generally output lines from module 10; however, when using the direct access ~odule 20, they are - . : bi-directional and allow input of addresses to module 1OJ ~0 is the lèast significant address bit in the addressing lines.
The DBINP line indicates the direction of communica~ion o~ the data lines Do-D7. This control line is used to gate data onto the data bus lines from each of the modules of ~` 6ystem A. ~
The R~ line is used in system A to gate data on the ~` '` data buses to the ~ddressed locations. In view of the simi-" larity between`the DBINP line and ~he R~W line, they are gen- ~ ;
erally used together. The DBINP line is used to determine the : direction of data flow and to gate the data onto the data buses.
; The READ/WRITE line R/W is used to de~ermine whether this da~a 'i8 written or read. 8y proYiding these two control tines~ the data on the data bus or lines Do-Dj is stable during the reading and writing pulse on the R~R line.
. .
, :
, ,` : : ' - , . . :
, , . , . . , ~, ;~ O

" 'i . r GDlS-10-S991 . The WAIT line is used in connection with the READY line.
These lines are communicated with ~he microprocessor~ whlch allows an additional amount of time for reading slower ~emory or I~O (input/outpu~) locations, If during an addressed output, the module 10 does no~ receive a loglc 1 ~o~dition on the READY
line, the microprocessor will enter a WAIT state as long as the READY line is at a low logic. In ~his state, a logic O
~ created on the WAIT line. As soon as the RE~DY input is received, the microproeessor passes out of the WAIT state and a logic l appears on the WAIT line, This fe~ture is clearly illustrated in FIGURE 2 which rela~es to the operation of.the 8080 Intel microprocessor, The INTF~ output indicates the content of an internal interrupt enable flip-flop on the 8080 microprocessor chip.
This internal flip-flop may be set or reset by enable and dis-sble interrupt instructions and inhibits subsequent interrupt calls from being accepted by the microprocessor when the flip~ :
flop is in the reset condition. The internal flip-flop which ~s produced on the chip itself is automatically reset to dis-able further interrupts at the ~ime Tl o~ an Instruction Fetch ` cycle Ml and when an interrupt has been accepted by the micro-: ` processor.
`` -` The ~LDA line is the Hold Acknowledge line. This liae `` 8hifts to a logi~ O when a HOLD REQUEST is acknowledged by the microprocessor ~P. This HOLD REQUEST ls from the li~e .
` - HOLD REQUEST~as shown in FIGURE 1. The HO~D condition or t~ge of the m~croprocessor shif~s the address and data ` ~erminals of the microprocessor to a high impedance state`
so that these terminals release co~srolover She address l~nes 30 ~ Ao-A15 and the data lines Do_~7; These lines can be controlled `'`` ` ` ` `. ' . `` ' ' ` '' : . ` ' :

2~ .

~ 9 ~ ~ GD15~10~5991 .
- by the access module 20 during programming and debugging. The ~ignal on the HLDA line begins at time T3 for a read memory or input cycle, For a write in memory or an output cycle or operation, the HLDA line is shif~ed a~ the clock period follow-5` ing the T3 clocking period. In practice, it is known that the signal on the HLDA line appears after a rising edge of 01 of the high impedance on the address lines and data lines occurs af~er the ollowing edge of 02. The HOLD REQUEST lir.e indica~es ~hat there has been ~n external request to shift the CPU, and more particularly the microprocessing chip, into the ~OLD condition or state, In this HOLD condition or state, external devices can control the address and data lines as soon as the CPU
module has completed its use of ~hese lines for processing the existing or current machine cycle. Control is also re-linquished by the CPU module over the DBINP line and the RtW
ine. In other words, these lines may be controlled by the direct ` access module 20 for programming or other external control func-.
. .` . tions. In summary~ when a HOLD state is requested, the micro-processor shifts into the HOLD condition or state and gives an output signal on the HLDA line to indicate ~his HOLD condition.
; Th~s condition occuxs after a certa;n amount of clean-up during a machine cycle being processed~ The HOLD condition or state ..
. comes into being at the next machine cycle and holds the ex~st- -`~ ` ing internal logic on register condi~ions of the microprocessor ` 25 ~ chip. . `
`. - A similar arrangement i~ used for the reset operation.
.
:.` A Reset Request is created by the power supply 12 or by the . dlrect access module 20 on the RESET REQUEST line. When this ~` .. request is received by module 10, the microprocessor is reset.
; 30 In this condition~ the content of the internal program counter - ~ , , . ' . .

~ 22 - .. .

~ 9 ~ GD15-10-5991 , of the 8080 microprocessor is cleared. After the reset pulse, the program will star~ at a location word zero in the memory.
: The internal INTE and HLDA fl;p-flops of the microprocessor chip are also reset. The internal aceumulato~, stack pointer, and registers are no~ clearedO When the reset condition is entered, the logic on the RESET line is shif~ed to reset the various flip-flops and other logics throughout system A. This arrangement is used for starting controller system A into opera~ion The bi-directional data buses or lines Do D7 provide eight bit data communication to and from CPU module 10. In addition, these lines are communicated with the various memory modules ; and I/O modules. The modules which perform only bit functions, - as opposed to byte functions, utilize only one of these lines, at least for outputting data. In the preferred embodiment~
: this line is Do~ During the first clock cycle of each machine cycle of the microprocessor, the CPU module ou~puts a status ` word on the data line or bus Do~D7. This status word is an : eight bit word which describes the current machine cycle. In this status word~ the Do line, in the preferred embodiment, is the least significant bit. The present invention relates to a micxoprocessor o~ the type utilizing eight bits of data;
~" however, a different number of data bits can be employed with- I
out departing from the intended scope of the invention. With .
an eight data bit microprocessor the status word can have eight bits generated by the microprocessor according to the iDstruction or command received from the program.
: In microprocessors now available, there is a~ INT~RRUPT
capability which is briefly described above. An INTE~RUPT
capability of the microprocessor allows it to s~ore lt5 presen~

- . , . ~ ' , , ' . ' . .' ' ' ;
. ' ' ' . , . ` , . , , !
~ ~3 _ ~

~ GD15-10-5991 posit~on in a program9 jump to a called subroutine, process the subroutine and then jump back to the proper location in the program that was being previously processed. To perform th~s function, the microprocessor has an INT input and module 10 has several interrupt request terminals INT 0-INT 7 Logic on the INT terminal shifts the microprocessor in~o the interrupt state. At that time, the INTE terminal (INT~ line) is energized to prevent subsequent interrupts, until the selected subroutine has reset the INTE terminal at the proper time. A higher priority interrupt can take over operation of the controller before a lower level priority in~errupt subroutine is completed, if the INTE has been reset by the processed subroutine. In the past, processing systems u~ilizing the microprocessor have in-Yolved the capability of recei~ing only a finite, relatively limited number of interrup~ requests. This limitation has been : dictated by the limitations of ~he various codes available for subroutine selection or "call'~ System A employs a system which includes eigh~ interrupt inputs which will shif~ the ` microprocessor Into the interrupt state~ In EIGURE 1, interrupts INT 0-INT 3 and INT 5-INT 7 are illustrated In practice, these .
` i~terrupts are assigned to external conditions, terminals or parameters, which may be inputs or outputs The priority of ` the interrupt requests is in reverse order to the numbering, : w~th the highest priority having the lowest number The lowes~
priority has the highest number; therefore, the PWR condi~ion, which is a logic 0 when power has been turned off, is the highest priority interruptq In this condition, irrespective of other interrupt conditions, the program will shift into the . "power off" subroutine which is found at a selected position ` in memory, which in practice is octal 010. In practlce, the ., ', ' `` '' "'.,'.` ,'.`. .'' ' , .. . - 24 ~
. . ..
,~ . . , , ;

, GD15~10-5991 next interrupt Lnput is the ~OOT which creates interrupt request INT 2 to a lo~ation in memory. In this manner, a minimum pro-gram is available for initial operation of sys~em A~ This initial minimum program is located at octal 020 of memory and is "called"
by various means sehematically represented as a pushbutton in FIGURE 1. In~errupt request INT 3 is the module in~erlock and parity check condition, which is operated in accordance wi~h known practice to maintain continuity of the various modules.
The INT 4 interrupt request is a real clock interrupt xequest, which shifts the program to the octal 040 position in memory.
This will be described in more detail with respect to the interrupt functions of system A. INT S is a communication ~nterrupt, in the preferred embodiment of the invention.
- Thls interrupt genera~es a location oc~al 050 in memory.
This allows communication from`external means, such as the -. direc~ access module 20~ The interrup~ I~T 7, which has the lowest priority, places the microprocessor into ~he interrupt ~` st~te to read or write from ex~ernal devices~ such as thumb~
wheels, ligh~s, switches and visual display devices, This ~0~ leaves INT 6, which is usPd with modulPs 30, 32 and 34 to ex~
~`` pand the amount of interrupt capability in system A. The IIV6 output acknowledges the receip~ and processing o~ an INT 6 . ` interrupt request. ~his signal line remains at a low logie " ` while the interrupting de~ice transmits a call from one of the modules 30-34 to the CPU module 10. The call instruc~ion is transm~tted synchronously with a 02 clock signal and provides the address in memory to which a call is placed during a se-lected additional interrupt provided by the add-on modules, ` only three of which are shown.
This description of the basic lines or command paths ~ . .
,; , . ,. . : .
~ 25 ~
, . . . . . . .
. ~ ~ . . .

~ O~ D15 10-5991 directed to and from CPU module 10 will be sufflcient for a full appreciatlon of the ~nvention which contemplates ~n impxnved module used with a microprocessor progra~mable controller of the type schematically shown in FI~URE 1. These output and input lines correspond in nomenclature used by Intel Corpora~ion for its 8080 microprocessor chip used in ~he preferred embodiment of the present invention. Corresponding nomenclature is used in other commercially available micro-processor chips which have ~he charac~eristics set forth gen-erally herein as background and explanatory information well known in the field. The characteristicg of this microprocessor chip are well known. Module 10 could produce an I-STROBE con-trol line for software production of a strobe to t~e various inputs and outputs, if desired.
STATUS WORD FOR MICROPROCESSOR
` . In ~he microprocessor utilized in module 10, as in mos~
microprocessors, a status word appears on the data terminals at the first of each machine cycle. This status word indica~es the operation ~o be performed by the microprocessor during ~ the~c~rrent machine cycle. Although a variety of s~atus codes " ` ~ and conditions could be provided~ the ten status words of the I~el 8080 microprocessor are illustrated in the chart shown ~`- in FIGURE 2. The data terminals have the coding indicated ~ the vertical columns for each of the various types o machine cycles during the ~nitlal part o~ the cycle. TAe binary status code on terminals Do~D7 is latched in~o a staSus la~ch at the ~ni~lal synchroniæation pulse in the SYNC line.
- `; . ` When the machine cycle is an I~STRUCTION FETCH, the coding on data lines Do D7 as latched into ~he status latch will be 01000101. The binary code on each of the data terminals during ;.

. . . : . : , . ..................... . ....... ...
... . . . . ......... . . ...... . ....... .
~ 26 - ;

~ GDlS-10-$991 the initial part of the cycle indicates a condition, as set forth in the status information column. In accordance with In~el 8080 terminology, the logic o~ data ~us Do is the inter~
rupt ~cknowledge (INTA). This logic indicates whether an interrupt request has been acknowledged and can be used to ga~e a restart instruction onto the data buses when the DBIN
or DBINP line is active. The logic on the Dl line during the :
initial part of the machine cycle indicates whether or not there is a writing function This status is labeled W and is a logic 0 when the machine cycle will wri~e data into memory or into an output location. When a logic 1 appears on the Dl instruc-tion line and is latched a~ the status latch, a memory or in-; put location is read. A logic 1 onlthe D2 line during the instruction read portion of the cycle indicates that the i5 address buses Ao-Al5 hold the push down stack address from -` ~ the stack pointer of the mi~roprocesspr. This status labeled STACK, ls active during only a STACK READ or a STACK WRITE
` machine cycle.
~hen a logic 1 appears upon the D3 data l~ne during the 20 ` ~nitial micro cycle of a machLne cycle, this indicates that ; ~ALT has been acknowledged. As can be seen in FIGURE 2, this occurs during a Halt Acknowledge machine cycle or an Interrupt Acknowledge While Halt machine cycle. Otherwise, during the initial micro cycle, which is labeled Tl in FIGURE 3, this data ~5 bus D3 is a logic 0. During an output func~ion, the`logic sn line D4 is a logic 1. This occurs when the machine-cycle îs an Output Write cycle. A logic 1 on the D4 data line indicates that -- the address buses conta~n the address o~ a~ output device and ` : that the data bus will ultimately~ during the cycle, contain the output data whe~ the R~ line is at a logic 0. The logic ,: " . . . .
-- ; , . , , - ' '" . .' , ' . , ' ' ,. ' ' ` , . .

G~15~10-5991 on data line D5 provides a signal to indicate that ~he microprocessor is in the FETCH cycle for the first byte of ~n instruction. Thus, a logic 1 on D5 during the initial por~ion of the machine cycle indicates that an instruc~ion is to be obtained from memory or another location. This is the status Ml iLlustrated in FIGURE 2. The status I~P is con-tained upon data line D6. A logic 1 on this line during the status portion of a machine cycle indicates that the ad~ress buses contain the address of an input device and the input data should be placed upon the data buses when the DBIN out-put o~ the microprocessor is active, This output of course corresponds to the DBINP line of the CPU module 10. MEMR -~ ;
logic appeals upon the D7 data bus. A logic 1 on this bus during the status infoxmation portion of the cycle designates that the da~a buses will be used for a memory read operation~
During the status por~ion of any cycle, the coding upon data lines Do-D7 are the codes indicated in FIGURE 2. This ~ coding is an inherent function of the 8080 microprocessor ` . and is set forth only for the purpose of a more convenient.
arrangement for understanding the preferred embodiment of the " . present invention. . . . .
BASIC INSTRUCTION CYCLE
. FOR CPU MODULE
. . :. .. .
` .- : The microprocessor employed in the preferred embodiment ~25 of the present invention has a basic instruction cycle as - . illustrated in FIGURE 3. The microprocessor is timed by the ; input pulses 01~ 02, the first of which determines the initial .~ , . . ~
. portion of a micro cycle labeled Tl-T5. The micro cycle TW
~' ` i8 se~ forth for the purpose of deslgnating a wait condition 30 ~ which was deccribed earlier with respect to the interplay - : . , . ~ .- . .
- - , . - . .' ' . , , , . . . . , . ~ .
~: . . , , ; . . l ` ';`,. ' '' ", ' '.'', ,".''' , '' ''' ''.'''.' ':', .'. '' lli ~ 9 ~ l ~ GD15-10-5991 between ~he READY loglc and the WAIT loglc1 If a memory is not ready, then the microprocessor goes into a WAIT state represented by a logic 1 on the WAIT line, i . e . a l~gic O
on the WAIT line. When the memory is then ready~ the WAIT
line shifts back to a logic 0 and ~he microprocessor continues ~nto micro cycle T3. For each machine cycle there is a ~ynchroni2ing pulse labeled SYNC~ This synchronization pulse corresponds èssentially to the internal synchronizing pulse of the 8080 microprocessor. The pulse has been shaped some-what. The pulses shown in FIGURE 3 are those entering and leaving the module 10; however, they are basically the pulses rom the microprocessor itself. During each of the micro cycles, the function set forth a~ the lower portio~ of FIGURE
` 3 takes place. S~ometimeS three micro cycles are used. In other 1~ instances, many micro cycles are required for a particular - instruction. For instance, ~n an Intel 8080 when ~Semory ~s accessed, as many as eighteen micxo cycles may be used i~ ~ormal operation. ~uSring the Tl micro cycle of a machine cycle, tbse logic on lines Do-D7 is read. The address on lines -A15 (a~ the address terminals of microprocessor MP) is pro-`vided by either the internal program counter or ano~her xegis~er within the microprocessor. This address information is placed .
` ~ ; into the program counter or register during a prior machine ` cycle. The DBINP l~ne corresponds to the internal DBIN line.
' 25 This determlnes whe~her or not data is placed on the data llnes Do~D ~ in a subsequent portion or micro cycle of the chine cycle. Dur~ng the initial portion, the data at the data terminals of the microprocessor indicates the type o~ cycle `` to be processed during the machine cycte which may require se~eral micro cycles. The log~c on the llnes desîgnated in .. .
" . . .
.. . ..

: 29 :; ' , :, `"`''` ' ' D15~10~5991 FIGURE 3 changes according to the type of instructlon to be processed in accordance with well known prac~ice in the micro-processing art. These logic conditions will be employed throughout the description of the pre~erred embodiment o~ the present inven~ionO .
PREFERRED EMBOD~NT
' Referring now to FIGURE 1, system A incl,udes an analog to digital con~ersion module or circuit 100, b~st shown in FIGURES 6A, 6B and 6Co This circui~ includes somewhat common concepts in converting an input analog voltage to output digi-" tal data, In accordance with the prefPrred embodiment of the - invention, the resulting or converted digital data is multio plexed onto data lines Do D7 of sys~em A, in a manner to be described later. An analog signal to be converted is imposed ` 15 across lines 1103 112. A conversion signal AD5 is provided in 11ne 114 to start the operation of conversion circuit 100 at the end of this pulse. After the conversion ~rom analog to digital data has been completed by circuit 100, a logic 1 appears in the T.C. RESET line 116. Thus, an analog signal together wlth a conversion signal in line 114 is directed to circuit 100. Thereafter~ a logic 1 comple~ion signal is 'created in the T.C. RESET line 116. Multiplexing module 120 i8 provided in system A, as shown in FIGU~E 1. Several of . the~e modules could be used to ~ul~lplex a large number of analog input signals ~o circuit 100. In the lllustrated em-bodiment, module 120 is indicated to be the input module I, which will be explained in de~ail ~n FI'GURE 4. This module .i8 illustrated schem~tically in FIGU~E 6A with analog input ` modules 122 and 124. Of course~ several modules could be used to increase the analog input capabilities. Each of these modules , , . ~ 30 - . :

, l~L~ GD15-10-5991 is the same and includes eigh~ separate analog input cir-cuits TC0-TC7. Of course, any analog signal could be con-nected to one of the input circuits TC0-TC7 without changing the operation of input module 120, The inpu~ lines cr cir-. 5 cuits TC0-TC7 direct analog conditions to module 120, which conditions can be ~emperature, speed, acceleration~ position - or any other signal that is analog in nature~ Referring now - to FIGURE 6A, ~he other input modules 122~ 124 are connected ~n parallel with lines 110, 112 for directing selected analog signals to the conversion circuit 100 by selectively closing switches 126, 128 of a moduleO As will be indicated in FIGURE
4, only the input circuits at TC0 and TC7;are illustrated in detail for the purposes of simplici~y. However, in practice, . eight separate inputs TC0-TC7 are provided on each analog in- -: 15 put module.
; . In operati~n, referring again to FIGURE ÇA, the several analog inputs TC0-TC7 of analog input modulesil20, 122 and 124 are-connected to various analog signals to be read and converted into digital data for use in system A. By an ap-propriate address, of the type shown in FIGURE 7, one of the - modules 1209 122 and i24 i8 addressed and active, This pro~
vides a ADC conversion signal i~ line 114 exeending from the ;
.` actuated modules 120, 12~ or 124 to the analog to digital ~.
circuit 100. -Input module 120 reads and decodes the logic `:25 on data lines Do-D3. This decoded information selects one of the analog inputs TC0-TC7 and applies the selected signal across analog signal lines 1109 112. After conversion has been completed, a logic 1 appears in the T.C. RESET line 116, which :
. is communicated to all modules 120, 122 and 124. This resets . all of the modules for subsequent selection and operation. In . .
`` . . - 31 -: . .
.. .. . . .... ..

~ ~ '' GDlS-10-5991 this manner, several input modules can be multiplexed to the conversion circuit 100 for cxeation of digi~al data corresponding to a selected input analog condition from the addressed analog input modules.
Referring now to FIGURE 4, the- preferred embodiment of - the analog input modules 120~ 122 and 124 is schematically illustra~ed with only t~o of analog'input circuits TC0-TC7 being shown. 'A larger number of input modules could be used and each module, in practice, includes eight separate analog input circuits TC0-TC7. The two circuits TC0 and TC7 are shown for the purpose of describing the operation o module 120 and the addition of other input circuits in parallel is quite apparent, ' Module 120 will be described in connection with a oycle ' for selecting and directing an'analog si~nal to the conversion circuit 100. This description of the operation of module 1203 together with the components used ln the preferred embodiment, will clearly illustrate the inventive concepts of the present invention. In FIGURE 7, there is illustrated an address used 'for selecting a given module and the data lines selec~ing one o~'circuits TC0-TC7. 'Address lines Ao~A15 are used to select the chassis in which modules 120, 122, 124 are located and the particular module during an input/output command from the system A ~llustrated in FIGURE lo The addxess of the module ~s determ~ned by its position in the chassis by the use of hardw~red di~it~al data provided at the various chassis loca-tions. This is an input/output i.e. I/0 address as distinguished from a memory address used to store data from lines Do-D7~ Ad-8 Alo~ A12, A13 relate to the type o~ operation for processing data which is not involved in the module 120.
Data is provided .
.
' - 32 '' ::~' . ' ' ." ' ''" ' ' . ~

,~ GD15-10-5991 by system A on ~he data. lines Vo-D7 when a WRITE; cycle is actlva~ed by the WRITE pulse in the WRITE line R/R, A module decod~ ng or addressing circuit 130 ls pro-vided at the input side of module 120, The address on lines A4 7 and All' Al4~ Al5 pro~ides a logic 0 in CE line 132 when the chassis into which mo~ule 120 is located is to be activated. The logic on address lines Ao-A3 is compared with hardwired logic in the motherboard at the mounting location of module 120 to provide a comparison at address circuit 130.
Assuming that the addressing is proper, a logic 1 appears in the output line 134 from addressing circuit 130. This activates module 120. A WRITE gate 140 is a NAND gate ha~ing a first input 1~2 connected by inverter 144 to the DBINP line. The second input 146 of gate 140 is the output of inverter 148 connected to the Rf~ line. A pulse in this line produces a WRITE signal to msdule ;~ 120. Assuming that module 1~0 has been addressed and the CPU
of system A has been commanded to process a WRITE to output command, the DBINP line is at a logic 0. Ultimately, the WRITE line R~ shifts to a WRITE signal, i.e~ logic 09 at the 2Q input of inverter 148. At this time, all input lines to gate 140 are at 8 logic 1; therefore, output 150 o~ this gate is sh~fted to the WRITE mode, i.e. a logic 0. The WRITE pulse, as shown in FIGURE 3 is ge~erally 500 ns in length. Thus, a 500 ns logic 0 WRITE pulse is created in line 1500 An ~nverter 152 connect~ line 150 wi~h line 154 at ~he clocking terminal 2A of one shot device 160. This de~ice has a known time delay of 2.3 ms, as indicated by the biaslng circuits. A positi~e .transition ~n line 1$4 causes a positive pulse in ~he Q terminal at line 162 of one shot device 150. This applies a logic l pulse~
for 2.3 ms at one input of NA~D gate 164a the output of which is .
33 ~
r ,` ' ` ' - . ., ` ' ', ' ' '` ' ., ADC line 114. As so far described, there is no sel~ct signal in the line 170; there~ore, the output of gate 164 is at a logic 1 and has not been toggled to actuate circuit 100.
The WRITE line 150 also controls gate 180. A logic 0 at this input of gate 180, which is a NAND gat~ produces a logic 1 in output line 182. This logic 1 is inverted by in~erter 184 to produce a logic 0 condition in line 186, which is connected to the negative clocking termi~al lA of a one device shot ~o~ This one shot device has a negatlve pulse of 100 ns at the Q output terminal connected to line 192. Thus 3 when there is a WRITE
signal in line 150, a 100 ns negative pulse appears in line 192 which is directed to a NAND ga~e 200 having a RESET input.
; The system RESET line is at a logic 1 during operation of system A. Thus, a logic 0 pulse in line 192 causes a logic 1 ` 15 pulse of 100 ns in output 202 of gate 200. Inverter 204 in-verts this logic to produce a logie 0 pulse in the CLEAR line 206 connected to the CLEAR terminal C~ of a s~andard eight bit addressable latch decoder 210. This decoder is cleared to pro-. ` duce all zeros at output terminals 0-7 during a CLEAR pulse in line 206. The lo~ic on data line D3 controls decoder 210~ A
logic 0 at terminal E prevents a select logic on any terminal 0-7. The E terminal of latch decoder 210 làtehes a logic 1 . i~ one of the output terminals 0-7~ in accordance with the binary logic on input lines Do~ Dl and D2 connected to the ~nput terminals a9 b and c of latch decoder 120. This assumes that the logic on line D3 is a logic 0. When there is a WRITE
.pulse of approximately 500 ns in line 150, latch decoder 210 ~ . i~ latched to decode the logic on lines Do~D2; howeYer, the CLEAR terminal CL overrides the latch termi~al E for the 100 ns CLEAR pulse in line 206. This concept i5 shown ~n FIGURES 8 and , .

- . . . . , . . . . ~ , --- ~
, I j GD15-10-S99l 9. Consequently, when an address as shown ~n FIGURE 7 appears and the CPU creates a WRITE signal, latch decod~r 210 is first cleared. During th-is same WRITE signal, a logic 1 signal is latched into one of the output terminals 0-7 of decoder 210.
The selected terminal is determined by a one of eight decoding of the logic on lines ~o~D2O This latching of one terminal : actuates one of the.input circuits TC0, TC7. In this illus-trated embodiment, only input circuits TC0 and TC7 are illus-trated. Thus, only terminals 0 and 7 are illustrated at the output of decoder 210, Select line 220 is connected to output terminal 0 and line 222 is connected to output terminal 7J In-verters 224, 226 invert the logic in lines 22Q, 222, respectively, to produce the opposite logic in lines 230~ 232, respectively.
The~e letter linesg eight of which are used in the preferred embodiment, are connected to the input of a se~.ect NAND gate 240. The logic on the data line D3, during module addressing, controls the overall operation of ~he latch decoder 210. If D3 is a logic 0, D3, which is the data line of system A at terminal D of latch decoder 210, is at a logic 1. This enables gate 210 to store a logic 1 to one of its outputs. Throughout this discussion of the preferred embodiment of module 120, it is assumed that decoder 120 is enabled by a logic 1 at ~he E terminal.
terminal.
If none of the circuits at the output of latch ~ :
decoder 210 on module 120 is to be deactivated, the logic on lines D3 is set to logic 0 to produce a logic 0 at the selected output of decoder 210. A logic 0 on all output terminals of latch decoder 210 produces a logic 1 ak all inputs of select gate 240 and a logic 0 in a selec~ line 170. This logic 0 is created during the CLEAR cycle of decoder 210 also~ If one of ``' " ''~ ''' ' "' ' . ' " ' ', ~ . 35 ~ ~ 7~ GD15-10-5'391 s t 3L~

~he output terminals 0-7 has been selected during a WRITE
command by ~he deeoded logic of lines Do-~2, the select l~ne 170 shifts to a logic 1. This logic combines wi~h the logic on line 162 to produce a negative pulse in the X~
line 114. This eventually causes co~vers;on circui~ 100 to be actuated for converting the analog signal between lines -: 110, 112 into a digital output code, in a manner to be de-scribed later.
Select line 170 also controls inverter 250 to produce a logic 0 in line 252 when there has been a selection by decoder 210. This logic 0 maintains a logic 1 in lLne 182 even though the WRITE pulse in line 150 ultimately disappears during the processing cycle Thus, during a single WRITE
command, one shot device 190 is no~ clocked again at a negative terminal lA controlled by line 186.
When line 170 ~hifts to a selec~ logic 1 condition during a WRITE address, this logic 1 enables both transistor switches 126, 128 in switching circuit 260 Thus, switches 126, 128 of module 120 are closed to connect the selected analog condi-2~ tion from module 120 to the.input of the conversion circuit 100.
To obtain the analog signal for use across lines 110, 112, there ` are provided relay control networks 300, 302. Network 300 con-trols the circuit input switches CP~Oa~ CROb, CR7a and CR7b. Ne~
, ~ork 302 controls output switches CRlOa, CRlOb, CR17a, and CR1 The transfer of analog data to lines 110, 112 from a selected one of the circuits TC0, TC7 is determined by ~peration of the relay control networks. In the illustrated embodiment, only two input circuits are shown. Thus, each of the circuits 300, .
302 includes only two relay control circuits. However~ in practice, eight separate input circuits are used, and each of .-.. .

~ - 36 -.
.. : . . . , .: ,. . " . , . . . , ., ,, , , ; ... . ..... . .
.

~ ~ GD15-10-5991 the networks 300, 302 includes eight separate relay clrcuits.
Referring now to ~he network 30~, this network is used to open a selected set of input switches cROa, CROb, cR7a and CR7b, on the input circuits TC0, TC7. Relay circuit 310, when energized, opens relay controlled switches CROa, CROb in input circuit TC0. Relay circuit 31~, when energized, opens contac~s CR7a, CR7b. Thus, when a given analog input circuit TC0, TC7 is selected by latch decoder 2103 a logic 0 appears at the input side of one of the inverters 314, 316. This produces a logic 1 at the output of ~he inverter and at ~he input of one of the circuits 310~ 312, respectively. Circuits 310~ 312 are connected to the + 12 volt line 318. Thus, for the selected c~rcuit TC0 or TC7 a logic 1 turns off one of the relay cir-cuits 310, 312. Since the switches of the relay circuits are held closed by a logic 0 or no select condition at inYerters 314, 316, the input switches control~ed by the deactivated relay circuit opens. In the light relay cireuits used in prac~ice and graphically indica~ed in FIGURE 4, only one relay circuit of network 300 will be deactivated. The remaining will stay activated to hold ~he input con~acts of the non-se- ;
lected circuit TCo-TCi in the closed condition.
Relay circuits 320, 322 of network 302 energize the se-` lected relay circuit, instead o~ deactivating the selected ~elay circuit. Inverters 324, 326, ~nvert the logic on lines - 320, 322, respecti~ely. Thus, the analog conditions selected by latch decoder 210 produce a logic~O at the output of one of the inverters 324, 326. This logic 0 acti~ates the selected relaycircuits 320, 322 to cause closing of the output switches CRlOa, CRlOb or the output switches CR17a~ CR17b. Capacitors 340 360 of circuits TC0~ TC7 are charged ~o ~he voltage determined :' '` . ,, ., '. `
, ~ ~ 37 ~

~ lS-10-S')~l by thermocouple or other transducer controlling circuits TC0~ TC7~ When one of the analog conditions is selected~
the input switches are opened by de-energizing one of the relay circuits 310, 312. In a like manner, ~he output -switches of the selected circuit are closed by energizing a correspond-ing one of the relay circuits 320, 322.
The voltage stored in capacitor 340 of input circuit TC0 is selectively applied to lines 342, 344 when swi~ches CR10 , CRlOb are closed. Output lines 3429 344 are connected in parallel across lines 350, 352 which are the input of the signal creating circuit SC of module 120. Output switches CRl7a, CR17b apply the voltage stored across capacitor 360 of input circuit TC7 to lines 362, 364. These lines are con-nected to signal creating circuit SC by lines 350, 352. The other six circuits are also connected across lines 350, 352 when selected by decoder 210.
The signal creating circuit can take any form to produce an analog signal of a fixed voltage ac~oss circui~ 100 during comparison. In practice the fixed analog signal is produced by a constant current-signal proportional to the stored voltage on one of the capacitors 340, 360. In the illustrated embodi~
ment, signal creating circuit SC includes differential amplifier ` 400 which creates a constant output in line 401 proportional to the~input voltage of capacitox 340 or capacitor 360. This output line controls the base voltage of transistor Q2 which ` ~8 coupled with a current controlling circuit 402 and a voltage limiting circuit 404 so that a proportional current is created ~n the output line 406. This current is proportional to the ` lnput analog voltage. Many circuits could be provided for converting an input voltage to an accurately controlled constant .
.

_ 3~ _ .. . ' ' ~ . . .-. .. .. .; ., ~ . ..
. .

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.

~ GD15-lO-S99l output current. This c~ncept is used in accordance with the present in~ention so that the resistance or impedance at the output side of module 120 and the input side of conversion circuit 100, to~ether with the interconnecting resistance, ; 5 will have negligible effect on the signal being received ~rom module 120 by module or circuit 100 The current generating : circuit SC, shown in phantom lines in FIGURE 4, has the param-Pters indicated by the various components These parameters are represen~ative in nature to show a system for creating a constant current proportional to inpu~ voltage across lines 350, 352. Of course, any number of current signal creating circuits could be used for ~his purpose. As shown sche-matically in FIGURE 6A, the input voltage across lines 350, 352 is controlled by di~ferential amplifier 400 and a current . control arrangement 402 to produce a selected constant current flow through switches 126, 128 of the selected input analog ~ :
module 120. Closing the outpu~ switches CRlOa, CRlOb and CR17à, CR17b of the selected one of circuits TC0, TC7 is de-layed by 1.5 ms through a one shot device 410. In this manner, ` it is assured that the input switches are opened before the .` ~ output switches CRlOa, ~RlOb or CR17a, CR17b are closed by ~- . energizing one of the circuits 320, 322. A variety of arrange- :
ments could be used for actuation delay In the illustrated `~ ` `embo~iment, the one shot de~ice 410 is energized by the negative 25 ` transition in line 186 at the output of inverter 184. Thus, as . ` - 800n as there is a WRITE signal, a logic 1 appears at the Q
~- : - terminal of one shot device 410. This reduces the base voltage ., . ., ~
-:. on transistor Ql to prevent ~he application o~ the ~ 12 volt ~ power supply to line 328 at the ou~put side of circuits 320, 322.
30. After the time delay logic 1 pulse at the Q terminal, a full , . . . . . . .
, . ~ . - . . . . . .
..
,, . . ~. , . . _ 39 _ . .
`. .. :`. '-.' ' ,' : ' . ' '' , . . . . . .

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,, ~ GD15-10~5991 ' ' .

12 volts is a plied ~o line 328 This allows actuation of circuits 320, 322 to close the output switches of the se-lected analog input circuit CR0-CR7. Circuits 310, 312 are directly connected to a ~ 12 volt power supply ~hrough line 318. Consequently, circuits 310, 312 are operated as soon as a selection has been made by decoder 210. Circuits 320, 322 are delayed for ~ known period of time to prevent connection of circuit SC with a measuring voltage source which could produce excessive currents or variable voltages.
The operation of the embodiment of the invention shown in FIGURE 4 is set forth in FIGURE 5 wherein certain pulse forms are shown. As can be seen, the representative input switches CR7 are opened as soon as a select signal has been created by a one shot device 190 After a time delay controlled by one shot 410, the output switches CR17 are then closed. One shot 190 controls the clear pulse for a ~ime less than the opera-tion of gate 140. One shot 160 controls the end of the compare signal ADC which starts the comparing function in circuit lOOo Referring now to FIGURES 6A, 6B and 6C, one type of analog to digital conversion circuit is illustrated. In thi~ circuit, `tak~ng ~he three figures together, there is provided an analog input resistor 4~0 which creates a voltage proportional to the constant current supplied across switches 126, 128 of the - ~ctivated module 120, 122 or 124. Integration circuit 450 ~5 having the characteristics shown in the integration voltage chart of FIGURE 5, accepts the constant voltage across re-sistor 440 to control the ramp of the integrating circuit for a fixed period of time. Referring now to the integration voltage shown in FIGURE S, between times Tl and T2 the in~egra-tion circuit (capacitor) charges at a fixed rate determined .

internally of integration circuit 450, ~ time T2~ the integration voltage curve has reached the capacitor thresh~
old voitage which will cause a logic 1 in line 452 for a purpose to be described later, Thereafter, the volta~e in-S creases ln the integrator at a rate determined by the voltage across resistor 440. After a fixed time, T3 ~ the counter is reset and the ramp control changes state to cause discharge of voltage (capacitor) from point M to a lower reference level at time T5. This discharge is at a.fixed rate controlled by a constant re~erence voltage. This fixed rate causes the voltage to reach the threshold voltage at time T4.
The spacing between time T2 and T4 is indica~ive of the magni-tude of the voltage across resistor 440. By operating a fixed - frequency controlled counter for the time between T2 and T~9 the counter will count to a number proportional to ~he voltage acxoss resistor 440. After reaching time T4, line 452 shifts to a logic 0 for a purpose to be described later. Line 452 controls one input of AND ga~e 454. The other input is a : fixed.frequency oscillator or clock 456 connected to a line 458. ~hus, as soon as time T2 is reached, gate 454 is active to create fixed frequency counting pulses in line 455~ Between time T4 and time T5, ~ logic 1 appears in line 460~ The A/D
control logic 470 is used to shift the direction of vol~age in integration circuit 450 after a fixed 'time T3. A ramp control ~25 pulse is created by control 470 and starts a~ the end of the ADC pulse, as shown in FIGURE S. Thus, the control logic 470 is controlled by the positive going portion of the ADC compari- ;
80n signal. Control line 472 directs the ramp control logic to integration circuit 450 in a time relationship shown in FIGURE
~30 3. In accordance with somewhat common practice, clock line 45S
causes counting of a counter 480 having a reset line 482. During - . I

-. . ~ 41 -.

n~ ~ ~
f ~ ` GD15 10-5991 the ADC pulse, counter 480 is reset and can not count. There-after, pulses from oscillator 456 pass~ng through gate 454 are directed to counter 480 by line 455 The counter is a 12 blt counter having output terminals DB0-DBll. An over scale line 484 can be provided by counter 480 so that if the scale to be read from terminals DB0-DBll has been exceeded, a logic ; l appears in this line. This wlll cause a logic 1 in the T.C~
RESET line 116, irrespective of the co~pletion of integration ~hlch is signalled by the logic on line 460. A logic 1 at the completion of integration or at an overflow condition causes a ` log~c 1 in T.C. RESET line 115c Referring now more particularly ~o the output side of circuit shown in FIGURE 6A; the logic on terminals DBO~DBlL
` indicates the percentage of maximum scale which has been re-corded by the conversion circuit lOOo At least ten terminals are required to provide a 100% of scale. The eleventh tenminal can indicate over scale and control the logic OR line 484.
Another line, indicated as DBll, can indicate under range which - would occur when no voltage is applied across resistor 440.
This can occur whe~ there is an open circuit at the input of an analog input circuit CR0-CR7p When this happens, a logiC
o~ a line, such as DBll, can be read. Of course, other arrange-ments could be provided for indica~ing the status of circuit 100 on certain ou~put terminals such as DBO-DBll. It is only necessary that an appropriate digital code be provided indicating the magnitude of the voltage acros~ resistor 440.
The number of output terminals DB0-DBll used by c;rcuit ~ 100 exceeds the available data lines Do~D7 in s~stem A For that reason, the output multiplexing circuit 500, shown in FIGURE 6C, ls provided for using all digital data from the .
. - 42 -.
. - . . ..... .
: , . .

03L ~ Gl)1~ 59'Jl DB0-DBll terminalsl A logic 1 in line 116 which indicates that onversion has been completed, activates the latch line 502 to latch the da~a on terminals DB0-DBll in~o multi-plexing circuit 500. ThereaftPr, the multiplexing circuit is enabled by a line 510 controlled by motherboard hardwired addressing atthe input to a module select circuit 512~ similar to select circuit 130 of FIGURE 4. The ~ddress on lines Ao-A15 is directed to address decoder 516 which passes through the data on lines Ao-A3 to control module select circuit 512. The condition of these address lines is compared with the hardwired code on lines 1, 2, 4 and 8 In addition, decoded information from address lines Ao~A is passed through line 520 to enable multiplex 500 to select eight bit information from selected terminals DBO-DBll~ This data is applied across the Do-D7 bi-directional data lines. A second address ~hen selects the da~a from remaining terminals DBO-DBll~ In practice,the first address selects DBO-DB7 for application on ~he bi-directional data line DO-D7~ Thereafter, a second address selects the next group of outpu~ lines DB8-DBllo Thus, in a series of two steps, the total data from the conversion circuit can be mul~iplexed onto the bi-directional data lines Do-D7. By providing ~wo bytes of information from multiplexing circui~ 500, the total range o~ the data information can be provided for use in system A.
This use can be employed to change h~ating elements, change ~5 speed, or change other functions which are monitored by measur~
ing the voltage across resistor 440. The circuitry shown in FIGURES 6A, 6B and 6C are taken together to show the general .operation and element composition of a conversion circuit 100, which can be employed by the module 120 shown in FIGURE 4~ Of coursej modifications of this conversion circuit and its , . '' ` ` ; , ' ` '' . :
.- - 43 -" . ' ` ~ `` ', " ' ' `., " . ,'., . ' ; ,., ' ,, ..., , . .: , . . .

~ ~ GDlS~10-5991 multiplexing could be incorporated, as long as the conver~
sion system accepts analog data in current form? converts this data into digital form at a conversion pulse, provides this data on output terminals after conversion has taken place, and then provides a conversion completion signal for use in deselecting module 120.
Referring again ~o module 120~ upon receipt of a comple-tion pulse in the T.C. RESET line 116, inverter 550 produces a log~c 0 pulse in line 551 This logic 0 pulse is a de-select pulse which actuates one shot device 410. Thus, on de-selection by the T~C. RESET line, the vol~age of line 328 is reduced. This deactivates the activated one of circuits 320, 322. Immediately the closed switches CRlOa, CRlOb, or switches CR17a, CR17b are opened. The deselecting pulse in line 551 also operates one shot circuit 552, biased as indicated, to produce a 1.5 ms pulse similar to the puIse created at the output of one shot device 410. This pulse appears at the Q outpu~ and is a logic 0. Thus, as soon as this pulse disappears, i.e a~ter 1.5 ms, ~he positive terminal lB of one shot circuit 190 is clocked. This again creates a 100 ns output pulse in line 192 to clear the address-able latch decoder 120 by a logic 0 CLEAR pulse in line 206 Thus, the deactivated one of relay circuits 310, 312 is activated by the 12 volt power supply at line 318~ This ~hen closes in-2S - put relay switches CRa, CRb or input relay switches CR7 , CR7b, according to which of these s~itches had been opened during an input select operation. Thus, no voltage is applied across lines 350, 352 of module 120. In addition, lines 230, 232 are now at a logic 1. This produces a logic 0 in the select line 170. Switches 126 9 128 are opened. Gate 164 is disabled and , ;. . .
.. . . - . . . ..

~. '~ (il)1~ - ll) - ) `J J L

gate 1~0 is unlatched by a logic 1 in lin~ 252 for receiving a subsequent WRITE pulse in line 150 After deselection, any of ~he modules 120, 12~ and 124 can be selected for in-putting ano.ther analog condition through th~ module and to S the conversion circuit 130. Only one conversion circuit need be used for all the modules. Although three modules have - been used for inputtin~ analog information in the illus~rated embodiment, in practice, sixteen modules can be decoded by the information on address lines Ao-A3.
The moduleg together with conversion circuit 100, is a `` hardwired self stopping component for use in ~ystem A. After a selection has been requested, module 120 and circuit 100 per-form their functions and then wai~. The decoded information remains in the latched lines DBO-DBll for readi.ng by subsequent cycles until unlatched by a~new WRITE cycle address to an input module together with a circuit select code on lines Do-D3.
For the purpose of biasing one shot devices 160~ 410 and 5529 a constant 5 vol~ power supply circuit 560 is provided to ` f~x a lo~ic 1 or + 5 volt condition in control line 562. In the illustrated embodiment~ + 5 volt con~rol is used for the logic and the ~ 12 ~olt power supply is used for operatin~
the relay control circuits 310, 312, 320 and 322.
As indicated during the description of the preferred " ` embodiment, various modifications may be made in the circuitry employed to produce the various parameters and conditions em-ployed in the operation of the module 120 constructed in accord-.. ance with the present invention.
: . ' . . .
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..
. ' - '` ,, . ' ` '`' :.' .
.
_ 45 --" ' . : ' . , . . ,,; ' . . : ' `, ' .

1118~0~ D15-10-5991 In accordance with the illustrated embodlment of the present invention9 the system employs automatic communication `between the analog to digital conversion circuits and the analog lnput circuits by lines ADC and T.C. RESET to reduce the number of programmed commands necessary to obtain a digital representation, at terminals, DBO~DBll, Or the analog input signal.
Also, the system employs automatic communication between the analog to digital conversion circuits and the analog input circuit T.C. RESET, to automatically return the selected analog input to the deselected state independent of programmed commands, thereby increasing the number of times a given input may be accessed while maintaining a desired conversion accuracy.

' ~, . ~ ' 1 . . '`:,~ .;

Claims (58)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A system for providing a digital data representative of a selected analog signal on the data lines of a programmable controller using a central processing unit having output address lines, a selected number of input/output bi-directional data lines, means for creating a write signal in a write line and means responsive to said write signal for writing data from said data lines into selected addressed locations, said system comprising: a conversion circuit for converting an input analog signal to digital data on output data terminals upon receipt of a conversion signal simultaneously with an analog signal and means for creating a completion signal when said con-version is completed; and at least two analog input modules, each of said modules including means for receiving at least two analog conditions, means for converting a selected one of said analog conditions to an analog signal; selecting means for selecting said one condition upon creation of said write signal, actuating means for actuating one of said input modules, directing means responsive to actuation of said module for directing said selected analog signal to said conversion circuit, and means for latching said selecting means until creation of said completion signal; and, means for actuating said actuating means of only one of said input modules at any given time.

2. A system as defined in claim 1 wherein said selecting means includes a decoder having an input side for receiving coded data from said data lines, an output side for creating a selector signal in one of at least two select lines, and means responsive to said selector signal in one of said select lines for actuating said directing means.

3. A system as defined in claim 2 including means respon-sive to said write signal for enabling said decoder.

4. A system as defined in claim 3 including means re-sponsive to said write signal for creating a clear signal generally simultaneous with the start write signal and having a duration substantially less than said write signal and means for clearing said decoder with said clear signal,

5. A system as defined is claim 4 including means for creating said conversion signal in response to said write signal.

6. A system as defined in claim 5 including a time de-lay device having an input controlled by said write signal and a time delayed output signal and means responsive to said output signal for creating said conversion signal.

7. A system as defined in claim 6 including decoder clearing means responsive to said completion signal for clearing said decoder.

8. A system as defined in claim 7 including a time delay circuit having an input controlled by said completion signal and a time delayed output signal and means responsive to said time delayed output of said time delay circuit for actuating said decoder clearing means.

9. A system as defined in claim 8 including means for creating said analog signals as current signals having variable values.

10. A system as defined in claim 9 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

11. A system as defined in claim 1 including means for creating said conversion signal in response to said write signal.

12. A system as defined in claim 1 including a time de-lay device having an input controlled by said write signal and a time delayed output signal and means responsive to said output signal for creating said conversion signal.

13. A system as defined in claim 11 including decoder clearing means responsive to said completion signal for clearing said decoder.

14. A system as defined in claim 7 including a time delay circuit having an input controlled by said completion signal and a time delayed output signal and means responsive to said time delayed output of said time delay circuit for actuating said decoder clearing means.

15. A system as defined in claim 1 including means for creating said analog signals as current signals having variable values.

16, A system as defined in claim 15 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

17. A system as defined in claim 2 including means for creating said analog signals as current signals having variable values.

18. A system as defined in claim 17 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

19. A system as defined in claim 3 including means for creating said analog signals as current signals having variable values.

20. A system as defined in claim 19 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

21. A system as defined in claim 11 including means for creating said analog signals as current signals having variable values.

22. A system as defined in claim 21 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

23. A system as defined in claim 2 including means re-sponsive to said write signal for creating a clear signal generally simultaneous with the start write signal and having a duration substantially less than said write signal and means for clearing said decoder with said clear signal.

24. A system as defined in claim 1 wherein said con-version circuit includes means for creating digital data having more bits than said selected number of input/output lines and an output data terminal for each of said bits and means for connecting some of output data terminals to said data lines during a first reading cycle and means for connecting the re-mainder of said output data to said terminals to said data lines during a second reading cycle.

25. A system as defined in claim 24 including means for creating said analog signals as current signals having variable values.

26. A system as defined in claim 25 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

27. A system as defined in claim 26 wherein said selecting means includes a decoder having an input side for receiving coded data from said data lines, an output side for creating a selector signal in one of at least two select lines, and means responsive to said selector signal in one of said select lines for actuating said directing means.

28. A system as defined in claim 24 wherein said selecting means includes a decoder having an input side for receiving coded data from said data lines, an output side for creating a selector signal in one of at least two select lines, and means responsive to said selector signal in one of said select lines for actuating said directing means.

29. A system as defined in claim 28 including means responsive to said write signal for enabling said decoder.

30. A system as defined in claim 28 including means for creating said analog signals as current signals having variable values.

31. A system as defined in claim 30 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

32. A system for providing digital data representative of a selected analog signal on the data lines of a programmable controller using a central processing unit having output address lines, a selected number of input/output bi-directional data lines, means for creating a write signal in a write line and means responsive to said write signal for writing data from said data lines into selected addressed locations, said system comprising: a conversion circuit for converting an input analog signal to digital data on output data terminals upon receipt of a conversion signal simultaneously with an analog signal and means for creating a completion signal when said conversion is completed; an input module including means for receiving at least two analog conditions, means for converting a se-lected one of said analog conditions to an analog signal;
selector means for selecting said one condition upon creation of said write signal, directing means for directing said se-lected analog signal to said conversion circuit, means latch-ing said selecting means until creation of said completion signal; and a decoder means for actuating said selecting means.

33. A system as defined in claim 32 including means responsive to said write signal for enabling said decoder.

34. A system as defined in claim 33 including means re-sponsive to said write signal for creating a clear signal generally simultaneous with the start write signal and having a duration substantially less than said write signal and means for clearing said decoder with said clear signal.

35. A system as defined in claim 34 including means for creating said conversion signal in response to said write signal.

36. A system as defined in claim 34 including a time de-lay device having an input controlled by said write signal and a time delayed output signal and means responsive to said output signal for creating said conversion signal.

37. A system as defined in claim 32 including means for creating said conversion signal in response to said write signal.

38. A system as defined in claim 32 including a time de-lay device having an input controlled by said write signal and a time delayed output signal and means responsive to said output signal for creating said conversion signal.

39. A system as defined in claim 32 including means for creating said analog signals as current signals having variable values.

40. A system as defined in claim 39 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

41. A system as defined in claim 33 including means for creating said analog signals as current signals having variable values.

42. A system as defined in claim 41 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

43. A system as defined in claim 37 including means for creating said analog signals as current signals having variable values.

44. A system as defined in claim 43 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

45. A system as defined in claim 32 wherein said con-version circuit includes means for creating digital data having more bits than said selected number of input/output lines and an output data terminal for each of said bits and means for connecting some of output data terminals to said data lines during a first reading cycle and means for connecting the re-mainder of said output data to said terminals to said data lines during a second reading cycle.

46. A system as defined in claim 45 including means for creating said analog signals as current signals having variable values.

47. A system as defined in claim 46 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

48. A system for providing digital data representative of a selected analog signal on the data lines of a programmable controller using a central processing unit having output address lines, a selected number of input/output bi-directional data lines, means for creating a write signal in a write line and means responsive to said write signal for writing data from said data lines into selected addressed locations, said system com-prising: a conversion circuit for converting an input analog signal to digital data on output data terminals upon receipt of a conversion signal simultaneously with an analog signal and means for creating a completion signal when said con-version is completed; and an analog input module including means for receiving at least two analog conditions; means for converting a selected one of said analog conditions to an analog signal; selecting means for selecting said one condition upon creation of said write signal, directing means for direct-ing said selected analog signal to said conversion circuit, said selecting means including a data latch means with input terminals for receiving a select logic code, output terminals, means for clearing said data latch means to an inoperative state on said output terminals upon creation of a clear signal, and means for latching a decoded enabling signal corresponding to said logic code at one of said output terminals upon creation of a latching signal; said selecting means also including means for selecting one of said conditions in response to said enabling signal in a given one of said output terminals; and means responsive to a single write signal for creating a clear signal and then an enable signal.

49. A system as defined in claim 48 wherein said clear signal has a duration substantially less than said enabling signal.

50. A system as defined in claim 49 wherein said clear signal and enabling signal are concurrent for at least a portion of said clear signal and said enabling signal and said clear signal takes precedence over said enabling signal.

51. A system as defined in claim 50 including means for creating said analog signals as current signals having variable values.

52. A system as defined in claim 51 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

53. A system as defined in claim 48 including means for creating said analog signals as current signals having variable values.

54. A system as defined in claim 53 including means on said conversion circuit for converting said current signals into voltage amplitude signals.

55. A system as defined in claim 48 including means for creating a second clear signal in response to said completion signal.

56. A system as defined in claim 55 including means for delaying said second clear signal for a selected time after said completion signal.

57. A system as defined in claim 55 including means for creating said analog signals as current signals having variable values.

58. A system as defined in claim 57 including means on said conversion circuit for converting said current signals into voltage amplitude signals.